2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_pipe.h"
24 #include "r600_public.h"
26 #include "evergreen_compute.h"
29 #include "sb/sb_public.h"
32 #include "pipe/p_shader_tokens.h"
33 #include "util/u_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_screen.h"
36 #include "util/u_simple_shaders.h"
37 #include "util/u_upload_mgr.h"
38 #include "util/u_math.h"
39 #include "vl/vl_decoder.h"
40 #include "vl/vl_video_buffer.h"
41 #include "radeon_video.h"
42 #include "radeon_uvd.h"
43 #include "util/os_time.h"
45 static const struct debug_named_value r600_debug_options
[] = {
47 { "nocpdma", DBG_NO_CP_DMA
, "Disable CP DMA" },
50 { "nosb", DBG_NO_SB
, "Disable sb backend for graphics shaders" },
51 { "sbcl", DBG_SB_CS
, "Enable sb backend for compute shaders" },
52 { "sbdry", DBG_SB_DRY_RUN
, "Don't use optimized bytecode (just print the dumps)" },
53 { "sbstat", DBG_SB_STAT
, "Print optimization statistics for shaders" },
54 { "sbdump", DBG_SB_DUMP
, "Print IR dumps after some optimization passes" },
55 { "sbnofallback", DBG_SB_NO_FALLBACK
, "Abort on errors instead of fallback" },
56 { "sbdisasm", DBG_SB_DISASM
, "Use sb disassembler for shader dumps" },
57 { "sbsafemath", DBG_SB_SAFEMATH
, "Disable unsafe math optimizations" },
59 DEBUG_NAMED_VALUE_END
/* must be last */
66 static void r600_destroy_context(struct pipe_context
*context
)
68 struct r600_context
*rctx
= (struct r600_context
*)context
;
71 r600_isa_destroy(rctx
->isa
);
73 r600_sb_context_destroy(rctx
->sb_context
);
75 for (sh
= 0; sh
< (rctx
->b
.chip_class
< EVERGREEN
? R600_NUM_HW_STAGES
: EG_NUM_HW_STAGES
); sh
++) {
76 r600_resource_reference(&rctx
->scratch_buffers
[sh
].buffer
, NULL
);
78 r600_resource_reference(&rctx
->dummy_cmask
, NULL
);
79 r600_resource_reference(&rctx
->dummy_fmask
, NULL
);
81 if (rctx
->append_fence
)
82 pipe_resource_reference((struct pipe_resource
**)&rctx
->append_fence
, NULL
);
83 for (sh
= 0; sh
< PIPE_SHADER_TYPES
; sh
++) {
84 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, sh
, R600_BUFFER_INFO_CONST_BUFFER
, NULL
);
85 free(rctx
->driver_consts
[sh
].constants
);
88 if (rctx
->fixed_func_tcs_shader
)
89 rctx
->b
.b
.delete_tcs_state(&rctx
->b
.b
, rctx
->fixed_func_tcs_shader
);
91 if (rctx
->dummy_pixel_shader
) {
92 rctx
->b
.b
.delete_fs_state(&rctx
->b
.b
, rctx
->dummy_pixel_shader
);
94 if (rctx
->custom_dsa_flush
) {
95 rctx
->b
.b
.delete_depth_stencil_alpha_state(&rctx
->b
.b
, rctx
->custom_dsa_flush
);
97 if (rctx
->custom_blend_resolve
) {
98 rctx
->b
.b
.delete_blend_state(&rctx
->b
.b
, rctx
->custom_blend_resolve
);
100 if (rctx
->custom_blend_decompress
) {
101 rctx
->b
.b
.delete_blend_state(&rctx
->b
.b
, rctx
->custom_blend_decompress
);
103 if (rctx
->custom_blend_fastclear
) {
104 rctx
->b
.b
.delete_blend_state(&rctx
->b
.b
, rctx
->custom_blend_fastclear
);
106 util_unreference_framebuffer_state(&rctx
->framebuffer
.state
);
108 if (rctx
->gs_rings
.gsvs_ring
.buffer
)
109 pipe_resource_reference(&rctx
->gs_rings
.gsvs_ring
.buffer
, NULL
);
111 if (rctx
->gs_rings
.esgs_ring
.buffer
)
112 pipe_resource_reference(&rctx
->gs_rings
.esgs_ring
.buffer
, NULL
);
114 for (sh
= 0; sh
< PIPE_SHADER_TYPES
; ++sh
)
115 for (i
= 0; i
< PIPE_MAX_CONSTANT_BUFFERS
; ++i
)
116 rctx
->b
.b
.set_constant_buffer(context
, sh
, i
, NULL
);
119 util_blitter_destroy(rctx
->blitter
);
121 if (rctx
->allocator_fetch_shader
) {
122 u_suballocator_destroy(rctx
->allocator_fetch_shader
);
125 r600_release_command_buffer(&rctx
->start_cs_cmd
);
127 FREE(rctx
->start_compute_cs_cmd
.buf
);
129 r600_common_context_cleanup(&rctx
->b
);
131 r600_resource_reference(&rctx
->trace_buf
, NULL
);
132 r600_resource_reference(&rctx
->last_trace_buf
, NULL
);
133 radeon_clear_saved_cs(&rctx
->last_gfx
);
138 static struct pipe_context
*r600_create_context(struct pipe_screen
*screen
,
139 void *priv
, unsigned flags
)
141 struct r600_context
*rctx
= CALLOC_STRUCT(r600_context
);
142 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
143 struct radeon_winsys
*ws
= rscreen
->b
.ws
;
148 rctx
->b
.b
.screen
= screen
;
150 rctx
->b
.b
.priv
= NULL
; /* for threaded_context_unwrap_sync */
151 rctx
->b
.b
.destroy
= r600_destroy_context
;
152 rctx
->b
.set_atom_dirty
= (void *)r600_set_atom_dirty
;
154 if (!r600_common_context_init(&rctx
->b
, &rscreen
->b
, flags
))
157 rctx
->screen
= rscreen
;
158 LIST_INITHEAD(&rctx
->texture_buffers
);
160 r600_init_blit_functions(rctx
);
162 if (rscreen
->b
.info
.has_hw_decode
) {
163 rctx
->b
.b
.create_video_codec
= r600_uvd_create_decoder
;
164 rctx
->b
.b
.create_video_buffer
= r600_video_buffer_create
;
166 rctx
->b
.b
.create_video_codec
= vl_create_decoder
;
167 rctx
->b
.b
.create_video_buffer
= vl_video_buffer_create
;
170 if (getenv("R600_TRACE"))
171 rctx
->is_debug
= true;
172 r600_init_common_state_functions(rctx
);
174 switch (rctx
->b
.chip_class
) {
177 r600_init_state_functions(rctx
);
178 r600_init_atom_start_cs(rctx
);
179 rctx
->custom_dsa_flush
= r600_create_db_flush_dsa(rctx
);
180 rctx
->custom_blend_resolve
= rctx
->b
.chip_class
== R700
? r700_create_resolve_blend(rctx
)
181 : r600_create_resolve_blend(rctx
);
182 rctx
->custom_blend_decompress
= r600_create_decompress_blend(rctx
);
183 rctx
->has_vertex_cache
= !(rctx
->b
.family
== CHIP_RV610
||
184 rctx
->b
.family
== CHIP_RV620
||
185 rctx
->b
.family
== CHIP_RS780
||
186 rctx
->b
.family
== CHIP_RS880
||
187 rctx
->b
.family
== CHIP_RV710
);
191 evergreen_init_state_functions(rctx
);
192 evergreen_init_atom_start_cs(rctx
);
193 evergreen_init_atom_start_compute_cs(rctx
);
194 rctx
->custom_dsa_flush
= evergreen_create_db_flush_dsa(rctx
);
195 rctx
->custom_blend_resolve
= evergreen_create_resolve_blend(rctx
);
196 rctx
->custom_blend_decompress
= evergreen_create_decompress_blend(rctx
);
197 rctx
->custom_blend_fastclear
= evergreen_create_fastclear_blend(rctx
);
198 rctx
->has_vertex_cache
= !(rctx
->b
.family
== CHIP_CEDAR
||
199 rctx
->b
.family
== CHIP_PALM
||
200 rctx
->b
.family
== CHIP_SUMO
||
201 rctx
->b
.family
== CHIP_SUMO2
||
202 rctx
->b
.family
== CHIP_CAICOS
||
203 rctx
->b
.family
== CHIP_CAYMAN
||
204 rctx
->b
.family
== CHIP_ARUBA
);
206 rctx
->append_fence
= pipe_buffer_create(rctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
207 PIPE_USAGE_DEFAULT
, 32);
210 R600_ERR("Unsupported chip class %d.\n", rctx
->b
.chip_class
);
214 rctx
->b
.gfx
.cs
= ws
->cs_create(rctx
->b
.ctx
, RING_GFX
,
215 r600_context_gfx_flush
, rctx
, false);
216 rctx
->b
.gfx
.flush
= r600_context_gfx_flush
;
218 rctx
->allocator_fetch_shader
=
219 u_suballocator_create(&rctx
->b
.b
, 64 * 1024,
220 0, PIPE_USAGE_DEFAULT
, 0, FALSE
);
221 if (!rctx
->allocator_fetch_shader
)
224 rctx
->isa
= calloc(1, sizeof(struct r600_isa
));
225 if (!rctx
->isa
|| r600_isa_init(rctx
, rctx
->isa
))
228 if (rscreen
->b
.debug_flags
& DBG_FORCE_DMA
)
229 rctx
->b
.b
.resource_copy_region
= rctx
->b
.dma_copy
;
231 rctx
->blitter
= util_blitter_create(&rctx
->b
.b
);
232 if (rctx
->blitter
== NULL
)
234 util_blitter_set_texture_multisample(rctx
->blitter
, rscreen
->has_msaa
);
235 rctx
->blitter
->draw_rectangle
= r600_draw_rectangle
;
237 r600_begin_new_cs(rctx
);
239 rctx
->dummy_pixel_shader
=
240 util_make_fragment_cloneinput_shader(&rctx
->b
.b
, 0,
241 TGSI_SEMANTIC_GENERIC
,
242 TGSI_INTERPOLATE_CONSTANT
);
243 rctx
->b
.b
.bind_fs_state(&rctx
->b
.b
, rctx
->dummy_pixel_shader
);
248 r600_destroy_context(&rctx
->b
.b
);
256 static int r600_get_param(struct pipe_screen
* pscreen
, enum pipe_cap param
)
258 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
259 enum radeon_family family
= rscreen
->b
.family
;
262 /* Supported features (boolean caps). */
263 case PIPE_CAP_NPOT_TEXTURES
:
264 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
265 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
266 case PIPE_CAP_ANISOTROPIC_FILTER
:
267 case PIPE_CAP_POINT_SPRITE
:
268 case PIPE_CAP_OCCLUSION_QUERY
:
269 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
270 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE
:
271 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
272 case PIPE_CAP_TEXTURE_SWIZZLE
:
273 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
274 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE
:
275 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
276 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
277 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
278 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
279 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
281 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
282 case PIPE_CAP_PRIMITIVE_RESTART
:
283 case PIPE_CAP_CONDITIONAL_RENDER
:
284 case PIPE_CAP_TEXTURE_BARRIER
:
285 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
286 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
287 case PIPE_CAP_TGSI_INSTANCEID
:
288 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
289 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
290 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
291 case PIPE_CAP_START_INSTANCE
:
292 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
293 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
294 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
295 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
296 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
297 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
298 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
299 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
300 case PIPE_CAP_SAMPLE_SHADING
:
301 case PIPE_CAP_CLIP_HALFZ
:
302 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
303 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
304 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
305 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
306 case PIPE_CAP_TGSI_TXQS
:
307 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
308 case PIPE_CAP_INVALIDATE_BUFFER
:
309 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
310 case PIPE_CAP_QUERY_MEMORY_INFO
:
311 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
312 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
313 case PIPE_CAP_CLEAR_TEXTURE
:
314 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
315 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
316 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
317 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
320 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET
:
321 /* Optimal number for good TexSubImage performance on Polaris10. */
322 return 64 * 1024 * 1024;
324 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
325 return rscreen
->b
.info
.drm_major
== 2 && rscreen
->b
.info
.drm_minor
>= 43;
327 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
328 return !R600_BIG_ENDIAN
&& rscreen
->b
.info
.has_userptr
;
330 case PIPE_CAP_COMPUTE
:
331 return rscreen
->b
.chip_class
> R700
;
333 case PIPE_CAP_TGSI_TEXCOORD
:
336 case PIPE_CAP_FAKE_SW_MSAA
:
339 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
340 return MIN2(rscreen
->b
.info
.max_alloc_size
, INT_MAX
);
342 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
343 return R600_MAP_BUFFER_ALIGNMENT
;
345 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
348 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
351 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
352 if (family
>= CHIP_CEDAR
)
354 /* pre-evergreen geom shaders need newer kernel */
355 if (rscreen
->b
.info
.drm_minor
>= 37)
359 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
362 /* Supported except the original R600. */
363 case PIPE_CAP_INDEP_BLEND_ENABLE
:
364 case PIPE_CAP_INDEP_BLEND_FUNC
:
365 /* R600 doesn't support per-MRT blends */
366 return family
== CHIP_R600
? 0 : 1;
368 /* Supported on Evergreen. */
369 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
370 case PIPE_CAP_CUBE_MAP_ARRAY
:
371 case PIPE_CAP_TEXTURE_GATHER_SM5
:
372 case PIPE_CAP_TEXTURE_QUERY_LOD
:
373 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
374 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
375 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
376 case PIPE_CAP_TGSI_CLOCK
:
377 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
378 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
379 return family
>= CHIP_CEDAR
? 1 : 0;
380 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
381 return family
>= CHIP_CEDAR
? 4 : 0;
382 case PIPE_CAP_DRAW_INDIRECT
:
383 /* kernel command checker support is also required */
384 return family
>= CHIP_CEDAR
&& rscreen
->b
.info
.drm_minor
>= 41;
386 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
387 return family
>= CHIP_CEDAR
? 0 : 1;
389 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES
:
392 case PIPE_CAP_MAX_GS_INVOCATIONS
:
395 /* shader buffer objects */
396 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE
:
398 case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS
:
401 /* Unsupported features. */
402 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
403 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
404 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
405 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
406 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
407 case PIPE_CAP_USER_VERTEX_BUFFERS
:
408 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
409 case PIPE_CAP_VERTEXID_NOBASE
:
410 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
411 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
412 case PIPE_CAP_SHAREABLE_SHADERS
:
413 case PIPE_CAP_DRAW_PARAMETERS
:
414 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
415 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
416 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
417 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
418 case PIPE_CAP_GENERATE_MIPMAP
:
419 case PIPE_CAP_STRING_MARKER
:
420 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
421 case PIPE_CAP_TGSI_VOTE
:
422 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
423 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
424 case PIPE_CAP_NATIVE_FENCE_FD
:
425 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
426 case PIPE_CAP_TGSI_FS_FBFETCH
:
428 case PIPE_CAP_INT64_DIVMOD
:
429 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
430 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
431 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
432 case PIPE_CAP_TGSI_BALLOT
:
433 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
434 case PIPE_CAP_POST_DEPTH_COVERAGE
:
435 case PIPE_CAP_BINDLESS_TEXTURE
:
436 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
437 case PIPE_CAP_QUERY_SO_OVERFLOW
:
438 case PIPE_CAP_MEMOBJ
:
439 case PIPE_CAP_LOAD_CONSTBUF
:
440 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
:
441 case PIPE_CAP_TILE_RASTER_ORDER
:
442 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
443 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
444 case PIPE_CAP_FENCE_SIGNAL
:
445 case PIPE_CAP_CONSTBUF0_FLAGS
:
446 case PIPE_CAP_PACKED_UNIFORMS
:
447 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS
:
448 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES
:
449 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES
:
450 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES
:
451 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES
:
452 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE
:
453 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS
:
454 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS
:
457 case PIPE_CAP_DOUBLES
:
458 if (rscreen
->b
.family
== CHIP_ARUBA
||
459 rscreen
->b
.family
== CHIP_CAYMAN
||
460 rscreen
->b
.family
== CHIP_CYPRESS
||
461 rscreen
->b
.family
== CHIP_HEMLOCK
)
464 case PIPE_CAP_CULL_DISTANCE
:
467 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
468 if (family
>= CHIP_CEDAR
)
472 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
473 if (family
>= CHIP_CEDAR
)
478 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
479 return rscreen
->b
.has_streamout
? 4 : 0;
480 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
481 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
482 return rscreen
->b
.has_streamout
? 1 : 0;
483 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
484 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
487 /* Geometry shader output. */
488 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
490 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
492 case PIPE_CAP_MAX_VERTEX_STREAMS
:
493 return family
>= CHIP_CEDAR
? 4 : 1;
495 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
496 /* Should be 2047, but 2048 is a requirement for GL 4.4 */
500 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
501 if (family
>= CHIP_CEDAR
)
505 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
506 if (family
>= CHIP_CEDAR
)
510 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
511 /* textures support 8192, but layered rendering supports 2048 */
513 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
514 /* textures support 8192, but layered rendering supports 2048 */
517 /* Render targets. */
518 case PIPE_CAP_MAX_RENDER_TARGETS
:
519 /* XXX some r6xx are buggy and can only do 4 */
522 case PIPE_CAP_MAX_VIEWPORTS
:
523 return R600_MAX_VIEWPORTS
;
524 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
525 case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS
:
528 /* Timer queries, present when the clock frequency is non zero. */
529 case PIPE_CAP_QUERY_TIME_ELAPSED
:
530 return rscreen
->b
.info
.clock_crystal_freq
!= 0;
531 case PIPE_CAP_QUERY_TIMESTAMP
:
532 return rscreen
->b
.info
.drm_minor
>= 20 &&
533 rscreen
->b
.info
.clock_crystal_freq
!= 0;
535 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
536 case PIPE_CAP_MIN_TEXEL_OFFSET
:
539 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
540 case PIPE_CAP_MAX_TEXEL_OFFSET
:
543 case PIPE_CAP_MAX_VARYINGS
:
546 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
547 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600
;
548 case PIPE_CAP_ENDIANNESS
:
549 return PIPE_ENDIAN_LITTLE
;
551 case PIPE_CAP_VENDOR_ID
:
552 return ATI_VENDOR_ID
;
553 case PIPE_CAP_DEVICE_ID
:
554 return rscreen
->b
.info
.pci_id
;
555 case PIPE_CAP_ACCELERATED
:
557 case PIPE_CAP_VIDEO_MEMORY
:
558 return rscreen
->b
.info
.vram_size
>> 20;
561 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
562 return rscreen
->b
.chip_class
>= R700
;
563 case PIPE_CAP_PCI_GROUP
:
564 return rscreen
->b
.info
.pci_domain
;
565 case PIPE_CAP_PCI_BUS
:
566 return rscreen
->b
.info
.pci_bus
;
567 case PIPE_CAP_PCI_DEVICE
:
568 return rscreen
->b
.info
.pci_dev
;
569 case PIPE_CAP_PCI_FUNCTION
:
570 return rscreen
->b
.info
.pci_func
;
572 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS
:
573 if (rscreen
->b
.family
>= CHIP_CEDAR
&& rscreen
->has_atomics
)
576 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS
:
577 if (rscreen
->b
.family
>= CHIP_CEDAR
&& rscreen
->has_atomics
)
578 return EG_MAX_ATOMIC_BUFFERS
;
582 return u_pipe_screen_get_param_defaults(pscreen
, param
);
586 static int r600_get_shader_param(struct pipe_screen
* pscreen
,
587 enum pipe_shader_type shader
,
588 enum pipe_shader_cap param
)
590 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
594 case PIPE_SHADER_FRAGMENT
:
595 case PIPE_SHADER_VERTEX
:
596 case PIPE_SHADER_COMPUTE
:
598 case PIPE_SHADER_GEOMETRY
:
599 if (rscreen
->b
.family
>= CHIP_CEDAR
)
601 /* pre-evergreen geom shaders need newer kernel */
602 if (rscreen
->b
.info
.drm_minor
>= 37)
605 case PIPE_SHADER_TESS_CTRL
:
606 case PIPE_SHADER_TESS_EVAL
:
607 if (rscreen
->b
.family
>= CHIP_CEDAR
)
614 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
615 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
616 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
617 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
619 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
621 case PIPE_SHADER_CAP_MAX_INPUTS
:
622 return shader
== PIPE_SHADER_VERTEX
? 16 : 32;
623 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
624 return shader
== PIPE_SHADER_FRAGMENT
? 8 : 32;
625 case PIPE_SHADER_CAP_MAX_TEMPS
:
626 return 256; /* Max native temporaries. */
627 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
628 if (shader
== PIPE_SHADER_COMPUTE
) {
629 uint64_t max_const_buffer_size
;
630 pscreen
->get_compute_param(pscreen
, PIPE_SHADER_IR_TGSI
,
631 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
632 &max_const_buffer_size
);
633 return MIN2(max_const_buffer_size
, INT_MAX
);
636 return R600_MAX_CONST_BUFFER_SIZE
;
638 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
639 return R600_MAX_USER_CONST_BUFFERS
;
640 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
642 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
644 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
645 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
646 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
647 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
649 case PIPE_SHADER_CAP_SUBROUTINES
:
650 case PIPE_SHADER_CAP_INT64_ATOMICS
:
651 case PIPE_SHADER_CAP_FP16
:
653 case PIPE_SHADER_CAP_INTEGERS
:
654 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
656 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
657 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
659 case PIPE_SHADER_CAP_PREFERRED_IR
:
660 return PIPE_SHADER_IR_TGSI
;
661 case PIPE_SHADER_CAP_SUPPORTED_IRS
: {
663 if (shader
== PIPE_SHADER_COMPUTE
)
664 ir
= 1 << PIPE_SHADER_IR_NATIVE
;
665 if (rscreen
->b
.family
>= CHIP_CEDAR
)
666 ir
|= 1 << PIPE_SHADER_IR_TGSI
;
669 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
670 if (rscreen
->b
.family
== CHIP_ARUBA
||
671 rscreen
->b
.family
== CHIP_CAYMAN
||
672 rscreen
->b
.family
== CHIP_CYPRESS
||
673 rscreen
->b
.family
== CHIP_HEMLOCK
)
676 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
677 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
678 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
679 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
680 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
682 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
683 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
684 if (rscreen
->b
.family
>= CHIP_CEDAR
&&
685 (shader
== PIPE_SHADER_FRAGMENT
|| shader
== PIPE_SHADER_COMPUTE
))
688 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
689 if (rscreen
->b
.family
>= CHIP_CEDAR
&& rscreen
->has_atomics
)
692 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
693 /* having to allocate the atomics out amongst shaders stages is messy,
694 so give compute 8 buffers and all the others one */
695 if (rscreen
->b
.family
>= CHIP_CEDAR
&& rscreen
->has_atomics
) {
696 return EG_MAX_ATOMIC_BUFFERS
;
699 case PIPE_SHADER_CAP_SCALAR_ISA
:
701 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
702 /* due to a bug in the shader compiler, some loops hang
703 * if they are not unrolled, see:
704 * https://bugs.freedesktop.org/show_bug.cgi?id=86720
711 static void r600_destroy_screen(struct pipe_screen
* pscreen
)
713 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
718 if (!rscreen
->b
.ws
->unref(rscreen
->b
.ws
))
721 if (rscreen
->global_pool
) {
722 compute_memory_pool_delete(rscreen
->global_pool
);
725 r600_destroy_common_screen(&rscreen
->b
);
728 static struct pipe_resource
*r600_resource_create(struct pipe_screen
*screen
,
729 const struct pipe_resource
*templ
)
731 if (templ
->target
== PIPE_BUFFER
&&
732 (templ
->bind
& PIPE_BIND_GLOBAL
))
733 return r600_compute_global_buffer_create(screen
, templ
);
735 return r600_resource_create_common(screen
, templ
);
738 struct pipe_screen
*r600_screen_create(struct radeon_winsys
*ws
,
739 const struct pipe_screen_config
*config
)
741 struct r600_screen
*rscreen
= CALLOC_STRUCT(r600_screen
);
747 /* Set functions first. */
748 rscreen
->b
.b
.context_create
= r600_create_context
;
749 rscreen
->b
.b
.destroy
= r600_destroy_screen
;
750 rscreen
->b
.b
.get_param
= r600_get_param
;
751 rscreen
->b
.b
.get_shader_param
= r600_get_shader_param
;
752 rscreen
->b
.b
.resource_create
= r600_resource_create
;
754 if (!r600_common_screen_init(&rscreen
->b
, ws
)) {
759 if (rscreen
->b
.info
.chip_class
>= EVERGREEN
) {
760 rscreen
->b
.b
.is_format_supported
= evergreen_is_format_supported
;
762 rscreen
->b
.b
.is_format_supported
= r600_is_format_supported
;
765 rscreen
->b
.debug_flags
|= debug_get_flags_option("R600_DEBUG", r600_debug_options
, 0);
766 if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE
))
767 rscreen
->b
.debug_flags
|= DBG_COMPUTE
;
768 if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE
))
769 rscreen
->b
.debug_flags
|= DBG_ALL_SHADERS
| DBG_FS
;
770 if (!debug_get_bool_option("R600_HYPERZ", TRUE
))
771 rscreen
->b
.debug_flags
|= DBG_NO_HYPERZ
;
773 if (rscreen
->b
.family
== CHIP_UNKNOWN
) {
774 fprintf(stderr
, "r600: Unknown chipset 0x%04X\n", rscreen
->b
.info
.pci_id
);
779 /* Figure out streamout kernel support. */
780 switch (rscreen
->b
.chip_class
) {
782 if (rscreen
->b
.family
< CHIP_RS780
) {
783 rscreen
->b
.has_streamout
= rscreen
->b
.info
.drm_minor
>= 14;
785 rscreen
->b
.has_streamout
= rscreen
->b
.info
.drm_minor
>= 23;
789 rscreen
->b
.has_streamout
= rscreen
->b
.info
.drm_minor
>= 17;
793 rscreen
->b
.has_streamout
= rscreen
->b
.info
.drm_minor
>= 14;
796 rscreen
->b
.has_streamout
= FALSE
;
801 switch (rscreen
->b
.chip_class
) {
804 rscreen
->has_msaa
= rscreen
->b
.info
.drm_minor
>= 22;
805 rscreen
->has_compressed_msaa_texturing
= false;
808 rscreen
->has_msaa
= rscreen
->b
.info
.drm_minor
>= 19;
809 rscreen
->has_compressed_msaa_texturing
= rscreen
->b
.info
.drm_minor
>= 24;
812 rscreen
->has_msaa
= rscreen
->b
.info
.drm_minor
>= 19;
813 rscreen
->has_compressed_msaa_texturing
= true;
816 rscreen
->has_msaa
= FALSE
;
817 rscreen
->has_compressed_msaa_texturing
= false;
820 rscreen
->b
.has_cp_dma
= rscreen
->b
.info
.drm_minor
>= 27 &&
821 !(rscreen
->b
.debug_flags
& DBG_NO_CP_DMA
);
823 rscreen
->b
.barrier_flags
.cp_to_L2
=
824 R600_CONTEXT_INV_VERTEX_CACHE
|
825 R600_CONTEXT_INV_TEX_CACHE
|
826 R600_CONTEXT_INV_CONST_CACHE
;
827 rscreen
->b
.barrier_flags
.compute_to_L2
= R600_CONTEXT_CS_PARTIAL_FLUSH
| R600_CONTEXT_FLUSH_AND_INV
;
829 rscreen
->global_pool
= compute_memory_pool_new(rscreen
);
831 /* Create the auxiliary context. This must be done last. */
832 rscreen
->b
.aux_context
= rscreen
->b
.b
.context_create(&rscreen
->b
.b
, NULL
, 0);
834 rscreen
->has_atomics
= rscreen
->b
.info
.drm_minor
>= 44;
835 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
836 struct pipe_resource templ
= {};
839 templ
.height0
= 2048;
841 templ
.array_size
= 1;
842 templ
.target
= PIPE_TEXTURE_2D
;
843 templ
.format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
844 templ
.usage
= PIPE_USAGE_DEFAULT
;
846 struct r600_resource
*res
= r600_resource(rscreen
->screen
.resource_create(&rscreen
->screen
, &templ
));
847 unsigned char *map
= ws
->buffer_map(res
->buf
, NULL
, PIPE_TRANSFER_WRITE
);
851 r600_screen_clear_buffer(rscreen
, &res
->b
.b
, 4, 4, 0xCC);
852 r600_screen_clear_buffer(rscreen
, &res
->b
.b
, 8, 4, 0xDD);
853 r600_screen_clear_buffer(rscreen
, &res
->b
.b
, 12, 4, 0xEE);
854 r600_screen_clear_buffer(rscreen
, &res
->b
.b
, 20, 4, 0xFF);
855 r600_screen_clear_buffer(rscreen
, &res
->b
.b
, 32, 20, 0x87);
857 ws
->buffer_wait(res
->buf
, RADEON_USAGE_WRITE
);
860 for (i
= 0; i
< 256; i
++) {
861 printf("%02X", map
[i
]);
867 if (rscreen
->b
.debug_flags
& DBG_TEST_DMA
)
868 r600_test_dma(&rscreen
->b
);
870 r600_query_fix_enabled_rb_mask(&rscreen
->b
);
871 return &rscreen
->b
.b
;