src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "pipe/p_context.h"
  28 #include "tgsi/tgsi_scan.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "tgsi/tgsi_util.h"
  31 #include "util/u_blitter.h"
  32 #include "util/u_double_list.h"
  33 #include "util/u_format.h"
  34 #include "util/u_format_s3tc.h"
  35 #include "util/u_transfer.h"
  36 #include "util/u_surface.h"
  37 #include "util/u_pack_color.h"
  38 #include "util/u_memory.h"
  39 #include "util/u_inlines.h"
  40 #include "util/u_upload_mgr.h"
  41 #include "vl/vl_decoder.h"
  42 #include "vl/vl_video_buffer.h"
  43 #include "os/os_time.h"
  44 #include "pipebuffer/pb_buffer.h"
  45 #include "r600.h"
  46 #include "r600d.h"
  47 #include "r600_resource.h"
  48 #include "r600_shader.h"
  49 #include "r600_pipe.h"
  50
  51 /*
  52  * pipe_context
  53  */
  54 static struct r600_fence *r600_create_fence(struct r600_pipe_context *ctx)
  55 {
  56         struct r600_fence *fence = NULL;
  57
  58         if (!ctx->fences.bo) {
  59                 /* Create the shared buffer object */
  60                 ctx->fences.bo = (struct r600_resource*)
  61                         pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM,
  62                                            PIPE_USAGE_STAGING, 4096);
  63                 if (!ctx->fences.bo) {
  64                         R600_ERR("r600: failed to create bo for fence objects\n");
  65                         return NULL;
  66                 }
  67                 ctx->fences.data = ctx->ws->buffer_map(ctx->fences.bo->buf, ctx->ctx.cs,
  68                                                        PIPE_TRANSFER_WRITE);
  69         }
  70
  71         if (!LIST_IS_EMPTY(&ctx->fences.pool)) {
  72                 struct r600_fence *entry;
  73
  74                 /* Try to find a freed fence that has been signalled */
  75                 LIST_FOR_EACH_ENTRY(entry, &ctx->fences.pool, head) {
  76                         if (ctx->fences.data[entry->index] != 0) {
  77                                 LIST_DELINIT(&entry->head);
  78                                 fence = entry;
  79                                 break;
  80                         }
  81                 }
  82         }
  83
  84         if (!fence) {
  85                 /* Allocate a new fence */
  86                 struct r600_fence_block *block;
  87                 unsigned index;
  88
  89                 if ((ctx->fences.next_index + 1) >= 1024) {
  90                         R600_ERR("r600: too many concurrent fences\n");
  91                         return NULL;
  92                 }
  93
  94                 index = ctx->fences.next_index++;
  95
  96                 if (!(index % FENCE_BLOCK_SIZE)) {
  97                         /* Allocate a new block */
  98                         block = CALLOC_STRUCT(r600_fence_block);
  99                         if (block == NULL)
 100                                 return NULL;
 101
 102                         LIST_ADD(&block->head, &ctx->fences.blocks);
 103                 } else {
 104                         block = LIST_ENTRY(struct r600_fence_block, ctx->fences.blocks.next, head);
 105                 }
 106
 107                 fence = &block->fences[index % FENCE_BLOCK_SIZE];
 108                 fence->ctx = ctx;
 109                 fence->index = index;
 110         }
 111
 112         pipe_reference_init(&fence->reference, 1);
 113
 114         ctx->fences.data[fence->index] = 0;
 115         r600_context_emit_fence(&ctx->ctx, ctx->fences.bo, fence->index, 1);
 116         return fence;
 117 }
 118
 119
 120 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 121                 unsigned flags)
 122 {
 123         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 124         struct r600_fence **rfence = (struct r600_fence**)fence;
 125         struct pipe_query *render_cond = NULL;
 126         unsigned render_cond_mode = 0;
 127
 128         if (rfence)
 129                 *rfence = r600_create_fence(rctx);
 130
 131         /* Disable render condition. */
 132         if (rctx->current_render_cond) {
 133                 render_cond = rctx->current_render_cond;
 134                 render_cond_mode = rctx->current_render_cond_mode;
 135                 ctx->render_condition(ctx, NULL, 0);
 136         }
 137
 138         r600_context_flush(&rctx->ctx, flags);
 139
 140         /* Re-enable render condition. */
 141         if (render_cond) {
 142                 ctx->render_condition(ctx, render_cond, render_cond_mode);
 143         }
 144 }
 145
 146 static void r600_flush_from_st(struct pipe_context *ctx,
 147                                struct pipe_fence_handle **fence)
 148 {
 149         r600_flush(ctx, fence, 0);
 150 }
 151
 152 static void r600_flush_from_winsys(void *ctx, unsigned flags)
 153 {
 154         r600_flush((struct pipe_context*)ctx, NULL, flags);
 155 }
 156
 157 static void r600_update_num_contexts(struct r600_screen *rscreen, int diff)
 158 {
 159         pipe_mutex_lock(rscreen->mutex_num_contexts);
 160         if (diff > 0) {
 161                 rscreen->num_contexts++;
 162
 163                 if (rscreen->num_contexts > 1)
 164                         util_slab_set_thread_safety(&rscreen->pool_buffers,
 165                                                     UTIL_SLAB_MULTITHREADED);
 166         } else {
 167                 rscreen->num_contexts--;
 168
 169                 if (rscreen->num_contexts <= 1)
 170                         util_slab_set_thread_safety(&rscreen->pool_buffers,
 171                                                     UTIL_SLAB_SINGLETHREADED);
 172         }
 173         pipe_mutex_unlock(rscreen->mutex_num_contexts);
 174 }
 175
 176 static void r600_destroy_context(struct pipe_context *context)
 177 {
 178         struct r600_pipe_context *rctx = (struct r600_pipe_context *)context;
 179
 180         rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
 181         util_unreference_framebuffer_state(&rctx->framebuffer);
 182
 183         r600_context_fini(&rctx->ctx);
 184
 185         util_blitter_destroy(rctx->blitter);
 186
 187         for (int i = 0; i < R600_PIPE_NSTATES; i++) {
 188                 free(rctx->states[i]);
 189         }
 190
 191         u_vbuf_destroy(rctx->vbuf_mgr);
 192         util_slab_destroy(&rctx->pool_transfers);
 193
 194         if (rctx->fences.bo) {
 195                 struct r600_fence_block *entry, *tmp;
 196
 197                 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rctx->fences.blocks, head) {
 198                         LIST_DEL(&entry->head);
 199                         FREE(entry);
 200                 }
 201
 202                 rctx->ws->buffer_unmap(rctx->fences.bo->buf);
 203                 pipe_resource_reference((struct pipe_resource**)&rctx->fences.bo, NULL);
 204         }
 205
 206         r600_update_num_contexts(rctx->screen, -1);
 207
 208         FREE(rctx);
 209 }
 210
 211 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 212 {
 213         struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context);
 214         struct r600_screen* rscreen = (struct r600_screen *)screen;
 215
 216         if (rctx == NULL)
 217                 return NULL;
 218
 219         r600_update_num_contexts(rscreen, 1);
 220
 221         rctx->context.winsys = rscreen->screen.winsys;
 222         rctx->context.screen = screen;
 223         rctx->context.priv = priv;
 224         rctx->context.destroy = r600_destroy_context;
 225         rctx->context.flush = r600_flush_from_st;
 226
 227         /* Easy accessing of screen/winsys. */
 228         rctx->screen = rscreen;
 229         rctx->ws = rscreen->ws;
 230         rctx->family = rscreen->family;
 231         rctx->chip_class = rscreen->chip_class;
 232
 233         rctx->fences.bo = NULL;
 234         rctx->fences.data = NULL;
 235         rctx->fences.next_index = 0;
 236         LIST_INITHEAD(&rctx->fences.pool);
 237         LIST_INITHEAD(&rctx->fences.blocks);
 238
 239         r600_init_blit_functions(rctx);
 240         r600_init_query_functions(rctx);
 241         r600_init_context_resource_functions(rctx);
 242         r600_init_surface_functions(rctx);
 243         rctx->context.draw_vbo = r600_draw_vbo;
 244
 245         rctx->context.create_video_decoder = vl_create_decoder;
 246         rctx->context.create_video_buffer = vl_video_buffer_create;
 247
 248         switch (rctx->chip_class) {
 249         case R600:
 250         case R700:
 251                 r600_init_state_functions(rctx);
 252                 if (r600_context_init(&rctx->ctx, rctx->screen)) {
 253                         r600_destroy_context(&rctx->context);
 254                         return NULL;
 255                 }
 256                 r600_init_config(rctx);
 257                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 258                 break;
 259         case EVERGREEN:
 260         case CAYMAN:
 261                 evergreen_init_state_functions(rctx);
 262                 if (evergreen_context_init(&rctx->ctx, rctx->screen)) {
 263                         r600_destroy_context(&rctx->context);
 264                         return NULL;
 265                 }
 266                 evergreen_init_config(rctx);
 267                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 268                 break;
 269         default:
 270                 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
 271                 r600_destroy_context(&rctx->context);
 272                 return NULL;
 273         }
 274
 275         rctx->ctx.pipe = &rctx->context;
 276         rctx->ctx.flush = r600_flush_from_winsys;
 277         rctx->ws->cs_set_flush_callback(rctx->ctx.cs, r600_flush_from_winsys, rctx);
 278
 279         util_slab_create(&rctx->pool_transfers,
 280                          sizeof(struct pipe_transfer), 64,
 281                          UTIL_SLAB_SINGLETHREADED);
 282
 283         rctx->vbuf_mgr = u_vbuf_create(&rctx->context, 1024 * 1024, 256,
 284                                            PIPE_BIND_VERTEX_BUFFER |
 285                                            PIPE_BIND_INDEX_BUFFER |
 286                                            PIPE_BIND_CONSTANT_BUFFER,
 287                                            U_VERTEX_FETCH_DWORD_ALIGNED);
 288         if (!rctx->vbuf_mgr) {
 289                 r600_destroy_context(&rctx->context);
 290                 return NULL;
 291         }
 292         rctx->vbuf_mgr->caps.format_fixed32 = 0;
 293
 294         rctx->blitter = util_blitter_create(&rctx->context);
 295         if (rctx->blitter == NULL) {
 296                 r600_destroy_context(&rctx->context);
 297                 return NULL;
 298         }
 299
 300         r600_get_backend_mask(&rctx->ctx); /* this emits commands and must be last */
 301
 302         return &rctx->context;
 303 }
 304
 305 /*
 306  * pipe_screen
 307  */
 308 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 309 {
 310         return "X.Org";
 311 }
 312
 313 static const char *r600_get_family_name(enum radeon_family family)
 314 {
 315         switch(family) {
 316         case CHIP_R600: return "AMD R600";
 317         case CHIP_RV610: return "AMD RV610";
 318         case CHIP_RV630: return "AMD RV630";
 319         case CHIP_RV670: return "AMD RV670";
 320         case CHIP_RV620: return "AMD RV620";
 321         case CHIP_RV635: return "AMD RV635";
 322         case CHIP_RS780: return "AMD RS780";
 323         case CHIP_RS880: return "AMD RS880";
 324         case CHIP_RV770: return "AMD RV770";
 325         case CHIP_RV730: return "AMD RV730";
 326         case CHIP_RV710: return "AMD RV710";
 327         case CHIP_RV740: return "AMD RV740";
 328         case CHIP_CEDAR: return "AMD CEDAR";
 329         case CHIP_REDWOOD: return "AMD REDWOOD";
 330         case CHIP_JUNIPER: return "AMD JUNIPER";
 331         case CHIP_CYPRESS: return "AMD CYPRESS";
 332         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 333         case CHIP_PALM: return "AMD PALM";
 334         case CHIP_SUMO: return "AMD SUMO";
 335         case CHIP_SUMO2: return "AMD SUMO2";
 336         case CHIP_BARTS: return "AMD BARTS";
 337         case CHIP_TURKS: return "AMD TURKS";
 338         case CHIP_CAICOS: return "AMD CAICOS";
 339         case CHIP_CAYMAN: return "AMD CAYMAN";
 340         default: return "AMD unknown";
 341         }
 342 }
 343
 344 static const char* r600_get_name(struct pipe_screen* pscreen)
 345 {
 346         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 347
 348         return r600_get_family_name(rscreen->family);
 349 }
 350
 351 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 352 {
 353         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 354         enum radeon_family family = rscreen->family;
 355
 356         switch (param) {
 357         /* Supported features (boolean caps). */
 358         case PIPE_CAP_NPOT_TEXTURES:
 359         case PIPE_CAP_TWO_SIDED_STENCIL:
 360         case PIPE_CAP_GLSL:
 361         case PIPE_CAP_DUAL_SOURCE_BLEND:
 362         case PIPE_CAP_ANISOTROPIC_FILTER:
 363         case PIPE_CAP_POINT_SPRITE:
 364         case PIPE_CAP_OCCLUSION_QUERY:
 365         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 366         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 367         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 368         case PIPE_CAP_TEXTURE_SWIZZLE:
 369         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 370         case PIPE_CAP_DEPTH_CLAMP:
 371         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 372         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 373         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 374         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 375         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 376         case PIPE_CAP_SM3:
 377         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 378         case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
 379         case PIPE_CAP_PRIMITIVE_RESTART:
 380         case PIPE_CAP_CONDITIONAL_RENDER:
 381         case PIPE_CAP_TEXTURE_BARRIER:
 382                 return 1;
 383
 384         /* Supported except the original R600. */
 385         case PIPE_CAP_INDEP_BLEND_ENABLE:
 386         case PIPE_CAP_INDEP_BLEND_FUNC:
 387                 /* R600 doesn't support per-MRT blends */
 388                 return family == CHIP_R600 ? 0 : 1;
 389
 390         /* Supported on Evergreen. */
 391         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 392                 return family >= CHIP_CEDAR ? 1 : 0;
 393
 394         /* Unsupported features. */
 395         case PIPE_CAP_STREAM_OUTPUT:
 396         case PIPE_CAP_TGSI_INSTANCEID:
 397         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 398         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 399                 return 0;
 400
 401         /* Texturing. */
 402         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 403         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 404         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 405                 if (family >= CHIP_CEDAR)
 406                         return 15;
 407                 else
 408                         return 14;
 409         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 410                 return rscreen->info.drm_minor >= 9 ?
 411                         (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
 412         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 413                 return 32;
 414
 415         /* Render targets. */
 416         case PIPE_CAP_MAX_RENDER_TARGETS:
 417                 /* FIXME some r6xx are buggy and can only do 4 */
 418                 return 8;
 419
 420         /* Timer queries, present when the clock frequency is non zero. */
 421         case PIPE_CAP_TIMER_QUERY:
 422                 return rscreen->info.r600_clock_crystal_freq != 0;
 423
 424         case PIPE_CAP_MIN_TEXEL_OFFSET:
 425                 return -8;
 426
 427         case PIPE_CAP_MAX_TEXEL_OFFSET:
 428                 return 7;
 429
 430         default:
 431                 R600_ERR("r600: unknown param %d\n", param);
 432                 return 0;
 433         }
 434 }
 435
 436 static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
 437 {
 438         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 439         enum radeon_family family = rscreen->family;
 440
 441         switch (param) {
 442         case PIPE_CAP_MAX_LINE_WIDTH:
 443         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 444         case PIPE_CAP_MAX_POINT_WIDTH:
 445         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 446                 if (family >= CHIP_CEDAR)
 447                         return 16384.0f;
 448                 else
 449                         return 8192.0f;
 450         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 451                 return 16.0f;
 452         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 453                 return 16.0f;
 454         default:
 455                 R600_ERR("r600: unsupported paramf %d\n", param);
 456                 return 0.0f;
 457         }
 458 }
 459
 460 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 461 {
 462         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 463         switch(shader)
 464         {
 465         case PIPE_SHADER_FRAGMENT:
 466         case PIPE_SHADER_VERTEX:
 467                 break;
 468         case PIPE_SHADER_GEOMETRY:
 469                 /* TODO: support and enable geometry programs */
 470                 return 0;
 471         default:
 472                 /* TODO: support tessellation on Evergreen */
 473                 return 0;
 474         }
 475
 476         /* TODO: all these should be fixed, since r600 surely supports much more! */
 477         switch (param) {
 478         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 479         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 480         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 481         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 482                 return 16384;
 483         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 484                 return 8; /* FIXME */
 485         case PIPE_SHADER_CAP_MAX_INPUTS:
 486                 if(shader == PIPE_SHADER_FRAGMENT)
 487                         return 34;
 488                 else
 489                         return 32;
 490         case PIPE_SHADER_CAP_MAX_TEMPS:
 491                 return 256; /* Max native temporaries. */
 492         case PIPE_SHADER_CAP_MAX_ADDRS:
 493                 /* FIXME Isn't this equal to TEMPS? */
 494                 return 1; /* Max native address registers */
 495         case PIPE_SHADER_CAP_MAX_CONSTS:
 496                 return R600_MAX_CONST_BUFFER_SIZE;
 497         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 498                 return R600_MAX_CONST_BUFFERS;
 499         case PIPE_SHADER_CAP_MAX_PREDS:
 500                 return 0; /* FIXME */
 501         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 502                 return 1;
 503         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 504         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 505         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 506         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 507                 return 1;
 508         case PIPE_SHADER_CAP_SUBROUTINES:
 509                 return 0;
 510         case PIPE_SHADER_CAP_INTEGERS:
 511                 if (rscreen->chip_class == EVERGREEN)
 512                         return 1;
 513                 return 0;
 514         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 515                 return 16;
 516         case PIPE_SHADER_CAP_OUTPUT_READ:
 517                 return 1;
 518         default:
 519                 return 0;
 520         }
 521 }
 522
 523 static int r600_get_video_param(struct pipe_screen *screen,
 524                                 enum pipe_video_profile profile,
 525                                 enum pipe_video_cap param)
 526 {
 527         switch (param) {
 528         case PIPE_VIDEO_CAP_SUPPORTED:
 529                 return vl_profile_supported(screen, profile);
 530         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 531                 return 1;
 532         case PIPE_VIDEO_CAP_MAX_WIDTH:
 533         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 534                 return vl_video_buffer_max_size(screen);
 535         case PIPE_VIDEO_CAP_NUM_BUFFERS_DESIRED:
 536                 return vl_num_buffers_desired(screen, profile);
 537         default:
 538                 return 0;
 539         }
 540 }
 541
 542 static void r600_destroy_screen(struct pipe_screen* pscreen)
 543 {
 544         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 545
 546         if (rscreen == NULL)
 547                 return;
 548
 549         rscreen->ws->destroy(rscreen->ws);
 550
 551         util_slab_destroy(&rscreen->pool_buffers);
 552         pipe_mutex_destroy(rscreen->mutex_num_contexts);
 553         FREE(rscreen);
 554 }
 555
 556 static void r600_fence_reference(struct pipe_screen *pscreen,
 557                                  struct pipe_fence_handle **ptr,
 558                                  struct pipe_fence_handle *fence)
 559 {
 560         struct r600_fence **oldf = (struct r600_fence**)ptr;
 561         struct r600_fence *newf = (struct r600_fence*)fence;
 562
 563         if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
 564                 struct r600_pipe_context *ctx = (*oldf)->ctx;
 565                 LIST_ADDTAIL(&(*oldf)->head, &ctx->fences.pool);
 566         }
 567
 568         *ptr = fence;
 569 }
 570
 571 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
 572                                     struct pipe_fence_handle *fence)
 573 {
 574         struct r600_fence *rfence = (struct r600_fence*)fence;
 575         struct r600_pipe_context *ctx = rfence->ctx;
 576
 577         return ctx->fences.data[rfence->index];
 578 }
 579
 580 static boolean r600_fence_finish(struct pipe_screen *pscreen,
 581                                  struct pipe_fence_handle *fence,
 582                                  uint64_t timeout)
 583 {
 584         struct r600_fence *rfence = (struct r600_fence*)fence;
 585         struct r600_pipe_context *ctx = rfence->ctx;
 586         int64_t start_time = 0;
 587         unsigned spins = 0;
 588
 589         if (timeout != PIPE_TIMEOUT_INFINITE) {
 590                 start_time = os_time_get();
 591
 592                 /* Convert to microseconds. */
 593                 timeout /= 1000;
 594         }
 595
 596         while (ctx->fences.data[rfence->index] == 0) {
 597                 if (++spins % 256)
 598                         continue;
 599 #ifdef PIPE_OS_UNIX
 600                 sched_yield();
 601 #else
 602                 os_time_sleep(10);
 603 #endif
 604                 if (timeout != PIPE_TIMEOUT_INFINITE &&
 605                     os_time_get() - start_time >= timeout) {
 606                         return FALSE;
 607                 }
 608         }
 609
 610         return TRUE;
 611 }
 612
 613 static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 614 {
 615         switch ((tiling_config & 0xe) >> 1) {
 616         case 0:
 617                 rscreen->tiling_info.num_channels = 1;
 618                 break;
 619         case 1:
 620                 rscreen->tiling_info.num_channels = 2;
 621                 break;
 622         case 2:
 623                 rscreen->tiling_info.num_channels = 4;
 624                 break;
 625         case 3:
 626                 rscreen->tiling_info.num_channels = 8;
 627                 break;
 628         default:
 629                 return -EINVAL;
 630         }
 631
 632         switch ((tiling_config & 0x30) >> 4) {
 633         case 0:
 634                 rscreen->tiling_info.num_banks = 4;
 635                 break;
 636         case 1:
 637                 rscreen->tiling_info.num_banks = 8;
 638                 break;
 639         default:
 640                 return -EINVAL;
 641
 642         }
 643         switch ((tiling_config & 0xc0) >> 6) {
 644         case 0:
 645                 rscreen->tiling_info.group_bytes = 256;
 646                 break;
 647         case 1:
 648                 rscreen->tiling_info.group_bytes = 512;
 649                 break;
 650         default:
 651                 return -EINVAL;
 652         }
 653         return 0;
 654 }
 655
 656 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 657 {
 658         switch (tiling_config & 0xf) {
 659         case 0:
 660                 rscreen->tiling_info.num_channels = 1;
 661                 break;
 662         case 1:
 663                 rscreen->tiling_info.num_channels = 2;
 664                 break;
 665         case 2:
 666                 rscreen->tiling_info.num_channels = 4;
 667                 break;
 668         case 3:
 669                 rscreen->tiling_info.num_channels = 8;
 670                 break;
 671         default:
 672                 return -EINVAL;
 673         }
 674
 675         switch ((tiling_config & 0xf0) >> 4) {
 676         case 0:
 677                 rscreen->tiling_info.num_banks = 4;
 678                 break;
 679         case 1:
 680                 rscreen->tiling_info.num_banks = 8;
 681                 break;
 682         case 2:
 683                 rscreen->tiling_info.num_banks = 16;
 684                 break;
 685         default:
 686                 return -EINVAL;
 687         }
 688
 689         switch ((tiling_config & 0xf00) >> 8) {
 690         case 0:
 691                 rscreen->tiling_info.group_bytes = 256;
 692                 break;
 693         case 1:
 694                 rscreen->tiling_info.group_bytes = 512;
 695                 break;
 696         default:
 697                 return -EINVAL;
 698         }
 699         return 0;
 700 }
 701
 702 static int r600_init_tiling(struct r600_screen *rscreen)
 703 {
 704         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 705
 706         /* set default group bytes, overridden by tiling info ioctl */
 707         if (rscreen->chip_class <= R700) {
 708                 rscreen->tiling_info.group_bytes = 256;
 709         } else {
 710                 rscreen->tiling_info.group_bytes = 512;
 711         }
 712
 713         if (!tiling_config)
 714                 return 0;
 715
 716         if (rscreen->chip_class <= R700) {
 717                 return r600_interpret_tiling(rscreen, tiling_config);
 718         } else {
 719                 return evergreen_interpret_tiling(rscreen, tiling_config);
 720         }
 721 }
 722
 723 static unsigned radeon_family_from_device(unsigned device)
 724 {
 725         switch (device) {
 726 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
 727 #include "pci_ids/r600_pci_ids.h"
 728 #undef CHIPSET
 729         default:
 730                 return CHIP_UNKNOWN;
 731         }
 732 }
 733
 734 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 735 {
 736         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 737         if (rscreen == NULL) {
 738                 return NULL;
 739         }
 740
 741         rscreen->ws = ws;
 742         ws->query_info(ws, &rscreen->info);
 743
 744         rscreen->family = radeon_family_from_device(rscreen->info.pci_id);
 745         if (rscreen->family == CHIP_UNKNOWN) {
 746                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
 747                 FREE(rscreen);
 748                 return NULL;
 749         }
 750
 751         /* setup class */
 752         if (rscreen->family == CHIP_CAYMAN) {
 753                 rscreen->chip_class = CAYMAN;
 754         } else if (rscreen->family >= CHIP_CEDAR) {
 755                 rscreen->chip_class = EVERGREEN;
 756         } else if (rscreen->family >= CHIP_RV770) {
 757                 rscreen->chip_class = R700;
 758         } else {
 759                 rscreen->chip_class = R600;
 760         }
 761
 762         if (r600_init_tiling(rscreen)) {
 763                 FREE(rscreen);
 764                 return NULL;
 765         }
 766
 767         rscreen->screen.winsys = (struct pipe_winsys*)ws;
 768         rscreen->screen.destroy = r600_destroy_screen;
 769         rscreen->screen.get_name = r600_get_name;
 770         rscreen->screen.get_vendor = r600_get_vendor;
 771         rscreen->screen.get_param = r600_get_param;
 772         rscreen->screen.get_shader_param = r600_get_shader_param;
 773         rscreen->screen.get_paramf = r600_get_paramf;
 774         rscreen->screen.get_video_param = r600_get_video_param;
 775         if (rscreen->chip_class >= EVERGREEN) {
 776                 rscreen->screen.is_format_supported = evergreen_is_format_supported;
 777         } else {
 778                 rscreen->screen.is_format_supported = r600_is_format_supported;
 779         }
 780         rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
 781         rscreen->screen.context_create = r600_create_context;
 782         rscreen->screen.fence_reference = r600_fence_reference;
 783         rscreen->screen.fence_signalled = r600_fence_signalled;
 784         rscreen->screen.fence_finish = r600_fence_finish;
 785         r600_init_screen_resource_functions(&rscreen->screen);
 786
 787         util_format_s3tc_init();
 788
 789         util_slab_create(&rscreen->pool_buffers,
 790                          sizeof(struct r600_resource), 64,
 791                          UTIL_SLAB_SINGLETHREADED);
 792
 793         pipe_mutex_init(rscreen->mutex_num_contexts);
 794
 795         return &rscreen->screen;
 796 }