Merge branch 'arb_sampler_objects'
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25 #include <pipe/p_defines.h>
26 #include <pipe/p_state.h>
27 #include <pipe/p_context.h>
28 #include <tgsi/tgsi_scan.h>
29 #include <tgsi/tgsi_parse.h>
30 #include <tgsi/tgsi_util.h>
31 #include <util/u_blitter.h>
32 #include <util/u_double_list.h>
33 #include <util/u_format_s3tc.h>
34 #include <util/u_transfer.h>
35 #include <util/u_surface.h>
36 #include <util/u_pack_color.h>
37 #include <util/u_memory.h>
38 #include <util/u_inlines.h>
39 #include "util/u_upload_mgr.h"
40 #include "os/os_time.h"
41 #include <pipebuffer/pb_buffer.h>
42 #include "r600.h"
43 #include "r600d.h"
44 #include "r600_resource.h"
45 #include "r600_shader.h"
46 #include "r600_pipe.h"
47 #include "r600_state_inlines.h"
48
49 /*
50 * pipe_context
51 */
52 static struct r600_fence *r600_create_fence(struct r600_pipe_context *ctx)
53 {
54 struct r600_fence *fence = NULL;
55
56 if (!ctx->fences.bo) {
57 /* Create the shared buffer object */
58 ctx->fences.bo = r600_bo(ctx->radeon, 4096, 0, 0, 0);
59 if (!ctx->fences.bo) {
60 R600_ERR("r600: failed to create bo for fence objects\n");
61 return NULL;
62 }
63 ctx->fences.data = r600_bo_map(ctx->radeon, ctx->fences.bo, PB_USAGE_UNSYNCHRONIZED, NULL);
64 }
65
66 if (!LIST_IS_EMPTY(&ctx->fences.pool)) {
67 struct r600_fence *entry;
68
69 /* Try to find a freed fence that has been signalled */
70 LIST_FOR_EACH_ENTRY(entry, &ctx->fences.pool, head) {
71 if (ctx->fences.data[entry->index] != 0) {
72 LIST_DELINIT(&entry->head);
73 fence = entry;
74 break;
75 }
76 }
77 }
78
79 if (!fence) {
80 /* Allocate a new fence */
81 struct r600_fence_block *block;
82 unsigned index;
83
84 if ((ctx->fences.next_index + 1) >= 1024) {
85 R600_ERR("r600: too many concurrent fences\n");
86 return NULL;
87 }
88
89 index = ctx->fences.next_index++;
90
91 if (!(index % FENCE_BLOCK_SIZE)) {
92 /* Allocate a new block */
93 block = CALLOC_STRUCT(r600_fence_block);
94 if (block == NULL)
95 return NULL;
96
97 LIST_ADD(&block->head, &ctx->fences.blocks);
98 } else {
99 block = LIST_ENTRY(struct r600_fence_block, ctx->fences.blocks.next, head);
100 }
101
102 fence = &block->fences[index % FENCE_BLOCK_SIZE];
103 fence->ctx = ctx;
104 fence->index = index;
105 }
106
107 pipe_reference_init(&fence->reference, 1);
108
109 ctx->fences.data[fence->index] = 0;
110 r600_context_emit_fence(&ctx->ctx, ctx->fences.bo, fence->index, 1);
111 return fence;
112 }
113
114 static void r600_flush(struct pipe_context *ctx,
115 struct pipe_fence_handle **fence)
116 {
117 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
118 struct r600_fence **rfence = (struct r600_fence**)fence;
119
120 #if 0
121 static int dc = 0;
122 char dname[256];
123 #endif
124
125 if (rfence)
126 *rfence = r600_create_fence(rctx);
127
128 if (!rctx->ctx.pm4_cdwords)
129 return;
130
131 #if 0
132 sprintf(dname, "gallium-%08d.bof", dc);
133 if (dc < 20) {
134 r600_context_dump_bof(&rctx->ctx, dname);
135 R600_ERR("dumped %s\n", dname);
136 }
137 dc++;
138 #endif
139 r600_context_flush(&rctx->ctx);
140
141 /* XXX This shouldn't be really necessary, but removing it breaks some tests.
142 * Needless buffer reallocations may significantly increase memory consumption,
143 * so getting rid of this call is important. */
144 u_upload_flush(rctx->vbuf_mgr->uploader);
145 }
146
147 static void r600_update_num_contexts(struct r600_screen *rscreen, int diff)
148 {
149 pipe_mutex_lock(rscreen->mutex_num_contexts);
150 if (diff > 0) {
151 rscreen->num_contexts++;
152
153 if (rscreen->num_contexts > 1)
154 util_slab_set_thread_safety(&rscreen->pool_buffers,
155 UTIL_SLAB_MULTITHREADED);
156 } else {
157 rscreen->num_contexts--;
158
159 if (rscreen->num_contexts <= 1)
160 util_slab_set_thread_safety(&rscreen->pool_buffers,
161 UTIL_SLAB_SINGLETHREADED);
162 }
163 pipe_mutex_unlock(rscreen->mutex_num_contexts);
164 }
165
166 static void r600_destroy_context(struct pipe_context *context)
167 {
168 struct r600_pipe_context *rctx = (struct r600_pipe_context *)context;
169
170 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
171 util_unreference_framebuffer_state(&rctx->framebuffer);
172
173 r600_context_fini(&rctx->ctx);
174
175 util_blitter_destroy(rctx->blitter);
176
177 for (int i = 0; i < R600_PIPE_NSTATES; i++) {
178 free(rctx->states[i]);
179 }
180
181 u_vbuf_mgr_destroy(rctx->vbuf_mgr);
182 util_slab_destroy(&rctx->pool_transfers);
183
184 if (rctx->fences.bo) {
185 struct r600_fence_block *entry, *tmp;
186
187 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rctx->fences.blocks, head) {
188 LIST_DEL(&entry->head);
189 FREE(entry);
190 }
191
192 r600_bo_unmap(rctx->radeon, rctx->fences.bo);
193 r600_bo_reference(rctx->radeon, &rctx->fences.bo, NULL);
194 }
195
196 r600_update_num_contexts(rctx->screen, -1);
197
198 FREE(rctx);
199 }
200
201 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
202 {
203 struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context);
204 struct r600_screen* rscreen = (struct r600_screen *)screen;
205 enum chip_class class;
206
207 if (rctx == NULL)
208 return NULL;
209
210 r600_update_num_contexts(rscreen, 1);
211
212 rctx->context.winsys = rscreen->screen.winsys;
213 rctx->context.screen = screen;
214 rctx->context.priv = priv;
215 rctx->context.destroy = r600_destroy_context;
216 rctx->context.flush = r600_flush;
217
218 /* Easy accessing of screen/winsys. */
219 rctx->screen = rscreen;
220 rctx->radeon = rscreen->radeon;
221 rctx->family = r600_get_family(rctx->radeon);
222
223 rctx->fences.bo = NULL;
224 rctx->fences.data = NULL;
225 rctx->fences.next_index = 0;
226 LIST_INITHEAD(&rctx->fences.pool);
227 LIST_INITHEAD(&rctx->fences.blocks);
228
229 r600_init_blit_functions(rctx);
230 r600_init_query_functions(rctx);
231 r600_init_context_resource_functions(rctx);
232 r600_init_surface_functions(rctx);
233 rctx->context.draw_vbo = r600_draw_vbo;
234
235 switch (r600_get_family(rctx->radeon)) {
236 case CHIP_R600:
237 case CHIP_RV610:
238 case CHIP_RV630:
239 case CHIP_RV670:
240 case CHIP_RV620:
241 case CHIP_RV635:
242 case CHIP_RS780:
243 case CHIP_RS880:
244 case CHIP_RV770:
245 case CHIP_RV730:
246 case CHIP_RV710:
247 case CHIP_RV740:
248 r600_init_state_functions(rctx);
249 if (r600_context_init(&rctx->ctx, rctx->radeon)) {
250 r600_destroy_context(&rctx->context);
251 return NULL;
252 }
253 r600_init_config(rctx);
254 break;
255 case CHIP_CEDAR:
256 case CHIP_REDWOOD:
257 case CHIP_JUNIPER:
258 case CHIP_CYPRESS:
259 case CHIP_HEMLOCK:
260 case CHIP_PALM:
261 case CHIP_BARTS:
262 case CHIP_TURKS:
263 case CHIP_CAICOS:
264 evergreen_init_state_functions(rctx);
265 if (evergreen_context_init(&rctx->ctx, rctx->radeon)) {
266 r600_destroy_context(&rctx->context);
267 return NULL;
268 }
269 evergreen_init_config(rctx);
270 break;
271 default:
272 R600_ERR("unsupported family %d\n", r600_get_family(rctx->radeon));
273 r600_destroy_context(&rctx->context);
274 return NULL;
275 }
276
277 util_slab_create(&rctx->pool_transfers,
278 sizeof(struct pipe_transfer), 64,
279 UTIL_SLAB_SINGLETHREADED);
280
281 rctx->vbuf_mgr = u_vbuf_mgr_create(&rctx->context, 1024 * 1024, 256,
282 PIPE_BIND_VERTEX_BUFFER |
283 PIPE_BIND_INDEX_BUFFER |
284 PIPE_BIND_CONSTANT_BUFFER,
285 U_VERTEX_FETCH_DWORD_ALIGNED);
286 if (!rctx->vbuf_mgr) {
287 r600_destroy_context(&rctx->context);
288 return NULL;
289 }
290
291 rctx->blitter = util_blitter_create(&rctx->context);
292 if (rctx->blitter == NULL) {
293 r600_destroy_context(&rctx->context);
294 return NULL;
295 }
296
297 class = r600_get_family_class(rctx->radeon);
298 if (class == R600 || class == R700)
299 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
300 else
301 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
302
303 return &rctx->context;
304 }
305
306 /*
307 * pipe_screen
308 */
309 static const char* r600_get_vendor(struct pipe_screen* pscreen)
310 {
311 return "X.Org";
312 }
313
314 static const char *r600_get_family_name(enum radeon_family family)
315 {
316 switch(family) {
317 case CHIP_R600: return "AMD R600";
318 case CHIP_RV610: return "AMD RV610";
319 case CHIP_RV630: return "AMD RV630";
320 case CHIP_RV670: return "AMD RV670";
321 case CHIP_RV620: return "AMD RV620";
322 case CHIP_RV635: return "AMD RV635";
323 case CHIP_RS780: return "AMD RS780";
324 case CHIP_RS880: return "AMD RS880";
325 case CHIP_RV770: return "AMD RV770";
326 case CHIP_RV730: return "AMD RV730";
327 case CHIP_RV710: return "AMD RV710";
328 case CHIP_RV740: return "AMD RV740";
329 case CHIP_CEDAR: return "AMD CEDAR";
330 case CHIP_REDWOOD: return "AMD REDWOOD";
331 case CHIP_JUNIPER: return "AMD JUNIPER";
332 case CHIP_CYPRESS: return "AMD CYPRESS";
333 case CHIP_HEMLOCK: return "AMD HEMLOCK";
334 case CHIP_PALM: return "AMD PALM";
335 case CHIP_BARTS: return "AMD BARTS";
336 case CHIP_TURKS: return "AMD TURKS";
337 case CHIP_CAICOS: return "AMD CAICOS";
338 default: return "AMD unknown";
339 }
340 }
341
342 static const char* r600_get_name(struct pipe_screen* pscreen)
343 {
344 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
345 enum radeon_family family = r600_get_family(rscreen->radeon);
346
347 return r600_get_family_name(family);
348 }
349
350 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
351 {
352 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
353 enum radeon_family family = r600_get_family(rscreen->radeon);
354
355 switch (param) {
356 /* Supported features (boolean caps). */
357 case PIPE_CAP_NPOT_TEXTURES:
358 case PIPE_CAP_TWO_SIDED_STENCIL:
359 case PIPE_CAP_GLSL:
360 case PIPE_CAP_DUAL_SOURCE_BLEND:
361 case PIPE_CAP_ANISOTROPIC_FILTER:
362 case PIPE_CAP_POINT_SPRITE:
363 case PIPE_CAP_OCCLUSION_QUERY:
364 case PIPE_CAP_TEXTURE_SHADOW_MAP:
365 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
366 case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
367 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
368 case PIPE_CAP_SM3:
369 case PIPE_CAP_TEXTURE_SWIZZLE:
370 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
371 case PIPE_CAP_DEPTH_CLAMP:
372 case PIPE_CAP_SHADER_STENCIL_EXPORT:
373 case PIPE_CAP_TGSI_INSTANCEID:
374 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
375 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
376 return 1;
377 case PIPE_CAP_INDEP_BLEND_ENABLE:
378 /* R600 doesn't support per-MRT blends */
379 if (family == CHIP_R600)
380 return 0;
381 else
382 return 1;
383
384 /* Unsupported features (boolean caps). */
385 case PIPE_CAP_STREAM_OUTPUT:
386 case PIPE_CAP_PRIMITIVE_RESTART:
387 case PIPE_CAP_INDEP_BLEND_FUNC: /* FIXME allow this */
388 case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
389 /* R600 doesn't support per-MRT blends */
390 if (family == CHIP_R600)
391 return 0;
392 else
393 return 0;
394
395 case PIPE_CAP_ARRAY_TEXTURES:
396 /* fix once the CS checker upstream is fixed */
397 return debug_get_bool_option("R600_ARRAY_TEXTURE", FALSE);
398
399 /* Texturing. */
400 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
401 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
402 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
403 if (family >= CHIP_CEDAR)
404 return 15;
405 else
406 return 14;
407 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
408 /* FIXME allow this once infrastructure is there */
409 return 16;
410 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
411 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
412 return 16;
413
414 /* Render targets. */
415 case PIPE_CAP_MAX_RENDER_TARGETS:
416 /* FIXME some r6xx are buggy and can only do 4 */
417 return 8;
418
419 /* Fragment coordinate conventions. */
420 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
421 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
422 return 1;
423 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
424 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
425 return 0;
426
427 /* Timer queries, present when the clock frequency is non zero. */
428 case PIPE_CAP_TIMER_QUERY:
429 return r600_get_clock_crystal_freq(rscreen->radeon) != 0;
430
431 default:
432 R600_ERR("r600: unknown param %d\n", param);
433 return 0;
434 }
435 }
436
437 static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
438 {
439 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
440 enum radeon_family family = r600_get_family(rscreen->radeon);
441
442 switch (param) {
443 case PIPE_CAP_MAX_LINE_WIDTH:
444 case PIPE_CAP_MAX_LINE_WIDTH_AA:
445 case PIPE_CAP_MAX_POINT_WIDTH:
446 case PIPE_CAP_MAX_POINT_WIDTH_AA:
447 if (family >= CHIP_CEDAR)
448 return 16384.0f;
449 else
450 return 8192.0f;
451 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
452 return 16.0f;
453 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
454 return 16.0f;
455 default:
456 R600_ERR("r600: unsupported paramf %d\n", param);
457 return 0.0f;
458 }
459 }
460
461 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
462 {
463 switch(shader)
464 {
465 case PIPE_SHADER_FRAGMENT:
466 case PIPE_SHADER_VERTEX:
467 break;
468 case PIPE_SHADER_GEOMETRY:
469 /* TODO: support and enable geometry programs */
470 return 0;
471 default:
472 /* TODO: support tessellation on Evergreen */
473 return 0;
474 }
475
476 /* TODO: all these should be fixed, since r600 surely supports much more! */
477 switch (param) {
478 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
479 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
480 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
481 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
482 return 16384;
483 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
484 return 8; /* FIXME */
485 case PIPE_SHADER_CAP_MAX_INPUTS:
486 if(shader == PIPE_SHADER_FRAGMENT)
487 return 10;
488 else
489 return 16;
490 case PIPE_SHADER_CAP_MAX_TEMPS:
491 return 256; //max native temporaries
492 case PIPE_SHADER_CAP_MAX_ADDRS:
493 return 1; //max native address registers/* FIXME Isn't this equal to TEMPS? */
494 case PIPE_SHADER_CAP_MAX_CONSTS:
495 return R600_MAX_CONST_BUFFER_SIZE;
496 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
497 return R600_MAX_CONST_BUFFERS;
498 case PIPE_SHADER_CAP_MAX_PREDS:
499 return 0; /* FIXME */
500 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
501 return 1;
502 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
503 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
504 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
505 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
506 return 1;
507 case PIPE_SHADER_CAP_SUBROUTINES:
508 return 0;
509 default:
510 return 0;
511 }
512 }
513
514 static boolean r600_is_format_supported(struct pipe_screen* screen,
515 enum pipe_format format,
516 enum pipe_texture_target target,
517 unsigned sample_count,
518 unsigned usage)
519 {
520 unsigned retval = 0;
521 if (target >= PIPE_MAX_TEXTURE_TYPES) {
522 R600_ERR("r600: unsupported texture type %d\n", target);
523 return FALSE;
524 }
525
526 /* Multisample */
527 if (sample_count > 1)
528 return FALSE;
529
530 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
531 r600_is_sampler_format_supported(screen, format)) {
532 retval |= PIPE_BIND_SAMPLER_VIEW;
533 }
534
535 if ((usage & (PIPE_BIND_RENDER_TARGET |
536 PIPE_BIND_DISPLAY_TARGET |
537 PIPE_BIND_SCANOUT |
538 PIPE_BIND_SHARED)) &&
539 r600_is_colorbuffer_format_supported(format)) {
540 retval |= usage &
541 (PIPE_BIND_RENDER_TARGET |
542 PIPE_BIND_DISPLAY_TARGET |
543 PIPE_BIND_SCANOUT |
544 PIPE_BIND_SHARED);
545 }
546
547 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
548 r600_is_zs_format_supported(format)) {
549 retval |= PIPE_BIND_DEPTH_STENCIL;
550 }
551
552 if (usage & PIPE_BIND_VERTEX_BUFFER) {
553 struct r600_screen *rscreen = (struct r600_screen *)screen;
554 enum radeon_family family = r600_get_family(rscreen->radeon);
555
556 if (r600_is_vertex_format_supported(format, family)) {
557 retval |= PIPE_BIND_VERTEX_BUFFER;
558 }
559 }
560
561 if (usage & PIPE_BIND_TRANSFER_READ)
562 retval |= PIPE_BIND_TRANSFER_READ;
563 if (usage & PIPE_BIND_TRANSFER_WRITE)
564 retval |= PIPE_BIND_TRANSFER_WRITE;
565
566 return retval == usage;
567 }
568
569 static void r600_destroy_screen(struct pipe_screen* pscreen)
570 {
571 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
572
573 if (rscreen == NULL)
574 return;
575
576 radeon_decref(rscreen->radeon);
577
578 util_slab_destroy(&rscreen->pool_buffers);
579 pipe_mutex_destroy(rscreen->mutex_num_contexts);
580 FREE(rscreen);
581 }
582
583 static void r600_fence_reference(struct pipe_screen *pscreen,
584 struct pipe_fence_handle **ptr,
585 struct pipe_fence_handle *fence)
586 {
587 struct r600_fence **oldf = (struct r600_fence**)ptr;
588 struct r600_fence *newf = (struct r600_fence*)fence;
589
590 if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
591 struct r600_pipe_context *ctx = (*oldf)->ctx;
592 LIST_ADDTAIL(&(*oldf)->head, &ctx->fences.pool);
593 }
594
595 *ptr = fence;
596 }
597
598 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
599 struct pipe_fence_handle *fence)
600 {
601 struct r600_fence *rfence = (struct r600_fence*)fence;
602 struct r600_pipe_context *ctx = rfence->ctx;
603
604 return ctx->fences.data[rfence->index];
605 }
606
607 static boolean r600_fence_finish(struct pipe_screen *pscreen,
608 struct pipe_fence_handle *fence,
609 uint64_t timeout)
610 {
611 struct r600_fence *rfence = (struct r600_fence*)fence;
612 struct r600_pipe_context *ctx = rfence->ctx;
613 int64_t start_time = 0;
614 unsigned spins = 0;
615
616 if (timeout != PIPE_TIMEOUT_INFINITE) {
617 start_time = os_time_get();
618
619 /* Convert to microseconds. */
620 timeout /= 1000;
621 }
622
623 while (ctx->fences.data[rfence->index] == 0) {
624 if (++spins % 256)
625 continue;
626 #ifdef PIPE_OS_UNIX
627 sched_yield();
628 #else
629 os_time_sleep(10);
630 #endif
631 if (timeout != PIPE_TIMEOUT_INFINITE &&
632 os_time_get() - start_time >= timeout) {
633 return FALSE;
634 }
635 }
636
637 return TRUE;
638 }
639
640 struct pipe_screen *r600_screen_create(struct radeon *radeon)
641 {
642 struct r600_screen *rscreen;
643
644 rscreen = CALLOC_STRUCT(r600_screen);
645 if (rscreen == NULL) {
646 return NULL;
647 }
648
649 rscreen->radeon = radeon;
650 rscreen->screen.winsys = (struct pipe_winsys*)radeon;
651 rscreen->screen.destroy = r600_destroy_screen;
652 rscreen->screen.get_name = r600_get_name;
653 rscreen->screen.get_vendor = r600_get_vendor;
654 rscreen->screen.get_param = r600_get_param;
655 rscreen->screen.get_shader_param = r600_get_shader_param;
656 rscreen->screen.get_paramf = r600_get_paramf;
657 rscreen->screen.is_format_supported = r600_is_format_supported;
658 rscreen->screen.context_create = r600_create_context;
659 rscreen->screen.fence_reference = r600_fence_reference;
660 rscreen->screen.fence_signalled = r600_fence_signalled;
661 rscreen->screen.fence_finish = r600_fence_finish;
662 r600_init_screen_resource_functions(&rscreen->screen);
663
664 rscreen->tiling_info = r600_get_tiling_info(radeon);
665 util_format_s3tc_init();
666
667 util_slab_create(&rscreen->pool_buffers,
668 sizeof(struct r600_resource_buffer), 64,
669 UTIL_SLAB_SINGLETHREADED);
670
671 pipe_mutex_init(rscreen->mutex_num_contexts);
672
673 return &rscreen->screen;
674 }