src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25 #include "r600_isa.h"
  26 #include "evergreen_compute.h"
  27 #include "r600d.h"
  28
  29 #include "sb/sb_public.h"
  30
  31 #include <errno.h>
  32 #include "pipe/p_shader_tokens.h"
  33 #include "util/u_debug.h"
  34 #include "util/u_memory.h"
  35 #include "util/u_simple_shaders.h"
  36 #include "util/u_upload_mgr.h"
  37 #include "util/u_math.h"
  38 #include "vl/vl_decoder.h"
  39 #include "vl/vl_video_buffer.h"
  40 #include "radeon/radeon_video.h"
  41 #include "radeon/radeon_uvd.h"
  42 #include "os/os_time.h"
  43
  44 static const struct debug_named_value r600_debug_options[] = {
  45         /* features */
  46 #if defined(R600_USE_LLVM)
  47         { "llvm", DBG_LLVM, "Enable the LLVM shader compiler" },
  48 #endif
  49         { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
  50
  51         /* shader backend */
  52         { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
  53         { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
  54         { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
  55         { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
  56         { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
  57         { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
  58         { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
  59         { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
  60
  61         DEBUG_NAMED_VALUE_END /* must be last */
  62 };
  63
  64 /*
  65  * pipe_context
  66  */
  67
  68 static void r600_destroy_context(struct pipe_context *context)
  69 {
  70         struct r600_context *rctx = (struct r600_context *)context;
  71
  72         r600_isa_destroy(rctx->isa);
  73
  74         r600_sb_context_destroy(rctx->sb_context);
  75
  76         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
  77         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
  78
  79         if (rctx->dummy_pixel_shader) {
  80                 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
  81         }
  82         if (rctx->custom_dsa_flush) {
  83                 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
  84         }
  85         if (rctx->custom_blend_resolve) {
  86                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
  87         }
  88         if (rctx->custom_blend_decompress) {
  89                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
  90         }
  91         if (rctx->custom_blend_fastclear) {
  92                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
  93         }
  94         util_unreference_framebuffer_state(&rctx->framebuffer.state);
  95
  96         if (rctx->blitter) {
  97                 util_blitter_destroy(rctx->blitter);
  98         }
  99         if (rctx->allocator_fetch_shader) {
 100                 u_suballocator_destroy(rctx->allocator_fetch_shader);
 101         }
 102
 103         r600_release_command_buffer(&rctx->start_cs_cmd);
 104
 105         FREE(rctx->start_compute_cs_cmd.buf);
 106
 107         r600_common_context_cleanup(&rctx->b);
 108         FREE(rctx);
 109 }
 110
 111 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 112 {
 113         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 114         struct r600_screen* rscreen = (struct r600_screen *)screen;
 115         struct radeon_winsys *ws = rscreen->b.ws;
 116
 117         if (rctx == NULL)
 118                 return NULL;
 119
 120         rctx->b.b.screen = screen;
 121         rctx->b.b.priv = priv;
 122         rctx->b.b.destroy = r600_destroy_context;
 123         rctx->b.set_atom_dirty = (void *)r600_set_atom_dirty;
 124
 125         if (!r600_common_context_init(&rctx->b, &rscreen->b))
 126                 goto fail;
 127
 128         rctx->screen = rscreen;
 129         rctx->keep_tiling_flags = rscreen->b.info.drm_minor >= 12;
 130
 131         r600_init_blit_functions(rctx);
 132
 133         if (rscreen->b.info.has_uvd) {
 134                 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
 135                 rctx->b.b.create_video_buffer = r600_video_buffer_create;
 136         } else {
 137                 rctx->b.b.create_video_codec = vl_create_decoder;
 138                 rctx->b.b.create_video_buffer = vl_video_buffer_create;
 139         }
 140
 141         r600_init_common_state_functions(rctx);
 142
 143         switch (rctx->b.chip_class) {
 144         case R600:
 145         case R700:
 146                 r600_init_state_functions(rctx);
 147                 r600_init_atom_start_cs(rctx);
 148                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 149                 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
 150                                                                       : r600_create_resolve_blend(rctx);
 151                 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
 152                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
 153                                            rctx->b.family == CHIP_RV620 ||
 154                                            rctx->b.family == CHIP_RS780 ||
 155                                            rctx->b.family == CHIP_RS880 ||
 156                                            rctx->b.family == CHIP_RV710);
 157                 break;
 158         case EVERGREEN:
 159         case CAYMAN:
 160                 evergreen_init_state_functions(rctx);
 161                 evergreen_init_atom_start_cs(rctx);
 162                 evergreen_init_atom_start_compute_cs(rctx);
 163                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 164                 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
 165                 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
 166                 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
 167                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
 168                                            rctx->b.family == CHIP_PALM ||
 169                                            rctx->b.family == CHIP_SUMO ||
 170                                            rctx->b.family == CHIP_SUMO2 ||
 171                                            rctx->b.family == CHIP_CAICOS ||
 172                                            rctx->b.family == CHIP_CAYMAN ||
 173                                            rctx->b.family == CHIP_ARUBA);
 174                 break;
 175         default:
 176                 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
 177                 goto fail;
 178         }
 179
 180         rctx->b.rings.gfx.cs = ws->cs_create(rctx->b.ctx, RING_GFX,
 181                                              r600_context_gfx_flush, rctx,
 182                                              rscreen->b.trace_bo ?
 183                                                      rscreen->b.trace_bo->cs_buf : NULL);
 184         rctx->b.rings.gfx.flush = r600_context_gfx_flush;
 185
 186         rctx->allocator_fetch_shader = u_suballocator_create(&rctx->b.b, 64 * 1024, 256,
 187                                                              0, PIPE_USAGE_DEFAULT, FALSE);
 188         if (!rctx->allocator_fetch_shader)
 189                 goto fail;
 190
 191         rctx->isa = calloc(1, sizeof(struct r600_isa));
 192         if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
 193                 goto fail;
 194
 195         if (rscreen->b.debug_flags & DBG_FORCE_DMA)
 196                 rctx->b.b.resource_copy_region = rctx->b.dma_copy;
 197
 198         rctx->blitter = util_blitter_create(&rctx->b.b);
 199         if (rctx->blitter == NULL)
 200                 goto fail;
 201         util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
 202         rctx->blitter->draw_rectangle = r600_draw_rectangle;
 203
 204         r600_begin_new_cs(rctx);
 205         r600_query_init_backend_mask(&rctx->b); /* this emits commands and must be last */
 206
 207         rctx->dummy_pixel_shader =
 208                 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
 209                                                      TGSI_SEMANTIC_GENERIC,
 210                                                      TGSI_INTERPOLATE_CONSTANT);
 211         rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 212
 213         return &rctx->b.b;
 214
 215 fail:
 216         r600_destroy_context(&rctx->b.b);
 217         return NULL;
 218 }
 219
 220 /*
 221  * pipe_screen
 222  */
 223
 224 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 225 {
 226         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 227         enum radeon_family family = rscreen->b.family;
 228
 229         switch (param) {
 230         /* Supported features (boolean caps). */
 231         case PIPE_CAP_NPOT_TEXTURES:
 232         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 233         case PIPE_CAP_TWO_SIDED_STENCIL:
 234         case PIPE_CAP_ANISOTROPIC_FILTER:
 235         case PIPE_CAP_POINT_SPRITE:
 236         case PIPE_CAP_OCCLUSION_QUERY:
 237         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 238         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 239         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 240         case PIPE_CAP_TEXTURE_SWIZZLE:
 241         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 242         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 243         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 244         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 245         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 246         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 247         case PIPE_CAP_SM3:
 248         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 249         case PIPE_CAP_PRIMITIVE_RESTART:
 250         case PIPE_CAP_CONDITIONAL_RENDER:
 251         case PIPE_CAP_TEXTURE_BARRIER:
 252         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 253         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 254         case PIPE_CAP_TGSI_INSTANCEID:
 255         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 256         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 257         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 258         case PIPE_CAP_USER_INDEX_BUFFERS:
 259         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 260         case PIPE_CAP_START_INSTANCE:
 261         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 262         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 263         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 264         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 265         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 266         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 267         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 268         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 269         case PIPE_CAP_SAMPLE_SHADING:
 270         case PIPE_CAP_CLIP_HALFZ:
 271         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 272         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 273         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 274         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 275                 return 1;
 276
 277         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 278                 return rscreen->b.info.drm_major == 2 && rscreen->b.info.drm_minor >= 43;
 279
 280         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 281                 return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;
 282
 283         case PIPE_CAP_COMPUTE:
 284                 return rscreen->b.chip_class > R700;
 285
 286         case PIPE_CAP_TGSI_TEXCOORD:
 287                 return 0;
 288
 289         case PIPE_CAP_FAKE_SW_MSAA:
 290                 return 0;
 291
 292         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 293                 return MIN2(rscreen->b.info.vram_size, 0xFFFFFFFF);
 294
 295         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 296                 return R600_MAP_BUFFER_ALIGNMENT;
 297
 298         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 299                 return 256;
 300
 301         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 302                 return 1;
 303
 304         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 305                 if (family >= CHIP_CEDAR)
 306                    return 330;
 307                 /* pre-evergreen geom shaders need newer kernel */
 308                 if (rscreen->b.info.drm_minor >= 37)
 309                    return 330;
 310                 return 140;
 311
 312         /* Supported except the original R600. */
 313         case PIPE_CAP_INDEP_BLEND_ENABLE:
 314         case PIPE_CAP_INDEP_BLEND_FUNC:
 315                 /* R600 doesn't support per-MRT blends */
 316                 return family == CHIP_R600 ? 0 : 1;
 317
 318         /* Supported on Evergreen. */
 319         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 320         case PIPE_CAP_CUBE_MAP_ARRAY:
 321         case PIPE_CAP_TEXTURE_GATHER_SM5:
 322         case PIPE_CAP_TEXTURE_QUERY_LOD:
 323         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 324                 return family >= CHIP_CEDAR ? 1 : 0;
 325         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 326                 return family >= CHIP_CEDAR ? 4 : 0;
 327         case PIPE_CAP_DRAW_INDIRECT:
 328                 /* kernel command checker support is also required */
 329                 return family >= CHIP_CEDAR && rscreen->b.info.drm_minor >= 41;
 330
 331         /* Unsupported features. */
 332         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 333         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 334         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 335         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 336         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 337         case PIPE_CAP_USER_VERTEX_BUFFERS:
 338         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 339         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 340         case PIPE_CAP_VERTEXID_NOBASE:
 341         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 342                 return 0;
 343
 344         /* Stream output. */
 345         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 346                 return rscreen->b.has_streamout ? 4 : 0;
 347         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 348                 return rscreen->b.has_streamout ? 1 : 0;
 349         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 350         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 351                 return 32*4;
 352
 353         /* Geometry shader output. */
 354         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 355                 return 1024;
 356         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 357                 return 16384;
 358         case PIPE_CAP_MAX_VERTEX_STREAMS:
 359                 return 1;
 360
 361         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 362                 return 2047;
 363
 364         /* Texturing. */
 365         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 366         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 367                 if (family >= CHIP_CEDAR)
 368                         return 15;
 369                 else
 370                         return 14;
 371         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 372                 /* textures support 8192, but layered rendering supports 2048 */
 373                 return 12;
 374         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 375                 /* textures support 8192, but layered rendering supports 2048 */
 376                 return rscreen->b.info.drm_minor >= 9 ? 2048 : 0;
 377
 378         /* Render targets. */
 379         case PIPE_CAP_MAX_RENDER_TARGETS:
 380                 /* XXX some r6xx are buggy and can only do 4 */
 381                 return 8;
 382
 383         case PIPE_CAP_MAX_VIEWPORTS:
 384                 return R600_MAX_VIEWPORTS;
 385
 386         /* Timer queries, present when the clock frequency is non zero. */
 387         case PIPE_CAP_QUERY_TIME_ELAPSED:
 388                 return rscreen->b.info.r600_clock_crystal_freq != 0;
 389         case PIPE_CAP_QUERY_TIMESTAMP:
 390                 return rscreen->b.info.drm_minor >= 20 &&
 391                        rscreen->b.info.r600_clock_crystal_freq != 0;
 392
 393         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 394         case PIPE_CAP_MIN_TEXEL_OFFSET:
 395                 return -8;
 396
 397         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 398         case PIPE_CAP_MAX_TEXEL_OFFSET:
 399                 return 7;
 400
 401         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 402                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 403         case PIPE_CAP_ENDIANNESS:
 404                 return PIPE_ENDIAN_LITTLE;
 405
 406         case PIPE_CAP_VENDOR_ID:
 407                 return 0x1002;
 408         case PIPE_CAP_DEVICE_ID:
 409                 return rscreen->b.info.pci_id;
 410         case PIPE_CAP_ACCELERATED:
 411                 return 1;
 412         case PIPE_CAP_VIDEO_MEMORY:
 413                 return rscreen->b.info.vram_size >> 20;
 414         case PIPE_CAP_UMA:
 415                 return 0;
 416         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 417                 return rscreen->b.chip_class >= R700;
 418         }
 419         return 0;
 420 }
 421
 422 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 423 {
 424         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 425
 426         switch(shader)
 427         {
 428         case PIPE_SHADER_FRAGMENT:
 429         case PIPE_SHADER_VERTEX:
 430         case PIPE_SHADER_COMPUTE:
 431                 break;
 432         case PIPE_SHADER_GEOMETRY:
 433                 if (rscreen->b.family >= CHIP_CEDAR)
 434                         break;
 435                 /* pre-evergreen geom shaders need newer kernel */
 436                 if (rscreen->b.info.drm_minor >= 37)
 437                         break;
 438                 return 0;
 439         default:
 440                 /* XXX: support tessellation on Evergreen */
 441                 return 0;
 442         }
 443
 444         switch (param) {
 445         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 446         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 447         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 448         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 449                 return 16384;
 450         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 451                 return 32;
 452         case PIPE_SHADER_CAP_MAX_INPUTS:
 453                 return shader == PIPE_SHADER_VERTEX ? 16 : 32;
 454         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 455                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 456         case PIPE_SHADER_CAP_MAX_TEMPS:
 457                 return 256; /* Max native temporaries. */
 458         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 459                 if (shader == PIPE_SHADER_COMPUTE) {
 460                         uint64_t max_const_buffer_size;
 461                         pscreen->get_compute_param(pscreen,
 462                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 463                                 &max_const_buffer_size);
 464                         return max_const_buffer_size;
 465
 466                 } else {
 467                         return R600_MAX_CONST_BUFFER_SIZE;
 468                 }
 469         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 470                 return R600_MAX_USER_CONST_BUFFERS;
 471         case PIPE_SHADER_CAP_MAX_PREDS:
 472                 return 0; /* nothing uses this */
 473         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 474                 return 1;
 475         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 476                 return 1;
 477         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 478         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 479         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 480         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 481                 return 1;
 482         case PIPE_SHADER_CAP_SUBROUTINES:
 483                 return 0;
 484         case PIPE_SHADER_CAP_INTEGERS:
 485         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 486                 return 1;
 487         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 488         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 489                 return 16;
 490         case PIPE_SHADER_CAP_PREFERRED_IR:
 491                 if (shader == PIPE_SHADER_COMPUTE) {
 492 #if HAVE_LLVM < 0x0306
 493                         return PIPE_SHADER_IR_LLVM;
 494 #else
 495                         return PIPE_SHADER_IR_NATIVE;
 496 #endif
 497                 } else {
 498                         return PIPE_SHADER_IR_TGSI;
 499                 }
 500         case PIPE_SHADER_CAP_DOUBLES:
 501                 return 0;
 502         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 503         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 504         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 505                 return 0;
 506         }
 507         return 0;
 508 }
 509
 510 static void r600_destroy_screen(struct pipe_screen* pscreen)
 511 {
 512         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 513
 514         if (rscreen == NULL)
 515                 return;
 516
 517         if (!rscreen->b.ws->unref(rscreen->b.ws))
 518                 return;
 519
 520         if (rscreen->global_pool) {
 521                 compute_memory_pool_delete(rscreen->global_pool);
 522         }
 523
 524         r600_destroy_common_screen(&rscreen->b);
 525 }
 526
 527 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
 528                                                   const struct pipe_resource *templ)
 529 {
 530         if (templ->target == PIPE_BUFFER &&
 531             (templ->bind & PIPE_BIND_GLOBAL))
 532                 return r600_compute_global_buffer_create(screen, templ);
 533
 534         return r600_resource_create_common(screen, templ);
 535 }
 536
 537 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 538 {
 539         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 540
 541         if (rscreen == NULL) {
 542                 return NULL;
 543         }
 544
 545         /* Set functions first. */
 546         rscreen->b.b.context_create = r600_create_context;
 547         rscreen->b.b.destroy = r600_destroy_screen;
 548         rscreen->b.b.get_param = r600_get_param;
 549         rscreen->b.b.get_shader_param = r600_get_shader_param;
 550         rscreen->b.b.resource_create = r600_resource_create;
 551
 552         if (!r600_common_screen_init(&rscreen->b, ws)) {
 553                 FREE(rscreen);
 554                 return NULL;
 555         }
 556
 557         if (rscreen->b.info.chip_class >= EVERGREEN) {
 558                 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
 559         } else {
 560                 rscreen->b.b.is_format_supported = r600_is_format_supported;
 561         }
 562
 563         rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
 564         if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
 565                 rscreen->b.debug_flags |= DBG_COMPUTE;
 566         if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
 567                 rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 568         if (!debug_get_bool_option("R600_HYPERZ", TRUE))
 569                 rscreen->b.debug_flags |= DBG_NO_HYPERZ;
 570         if (debug_get_bool_option("R600_LLVM", FALSE))
 571                 rscreen->b.debug_flags |= DBG_LLVM;
 572
 573         if (rscreen->b.family == CHIP_UNKNOWN) {
 574                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
 575                 FREE(rscreen);
 576                 return NULL;
 577         }
 578
 579         /* Figure out streamout kernel support. */
 580         switch (rscreen->b.chip_class) {
 581         case R600:
 582                 if (rscreen->b.family < CHIP_RS780) {
 583                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 584                 } else {
 585                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
 586                 }
 587                 break;
 588         case R700:
 589                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
 590                 break;
 591         case EVERGREEN:
 592         case CAYMAN:
 593                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 594                 break;
 595         default:
 596                 rscreen->b.has_streamout = FALSE;
 597                 break;
 598         }
 599
 600         /* MSAA support. */
 601         switch (rscreen->b.chip_class) {
 602         case R600:
 603         case R700:
 604                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
 605                 rscreen->has_compressed_msaa_texturing = false;
 606                 break;
 607         case EVERGREEN:
 608                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 609                 rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
 610                 break;
 611         case CAYMAN:
 612                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 613                 rscreen->has_compressed_msaa_texturing = true;
 614                 break;
 615         default:
 616                 rscreen->has_msaa = FALSE;
 617                 rscreen->has_compressed_msaa_texturing = false;
 618         }
 619
 620         rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
 621                               !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
 622
 623         rscreen->global_pool = compute_memory_pool_new(rscreen);
 624
 625         /* Create the auxiliary context. This must be done last. */
 626         rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL);
 627
 628 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
 629         struct pipe_resource templ = {};
 630
 631         templ.width0 = 4;
 632         templ.height0 = 2048;
 633         templ.depth0 = 1;
 634         templ.array_size = 1;
 635         templ.target = PIPE_TEXTURE_2D;
 636         templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
 637         templ.usage = PIPE_USAGE_DEFAULT;
 638
 639         struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
 640         unsigned char *map = ws->buffer_map(res->cs_buf, NULL, PIPE_TRANSFER_WRITE);
 641
 642         memset(map, 0, 256);
 643
 644         r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
 645         r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
 646         r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
 647         r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
 648         r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
 649
 650         ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
 651
 652         int i;
 653         for (i = 0; i < 256; i++) {
 654                 printf("%02X", map[i]);
 655                 if (i % 16 == 15)
 656                         printf("\n");
 657         }
 658 #endif
 659
 660         return &rscreen->b.b;
 661 }