src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25 #include "r600_isa.h"
  26 #include "evergreen_compute.h"
  27 #include "r600d.h"
  28
  29 #include "sb/sb_public.h"
  30
  31 #include <errno.h>
  32 #include "pipe/p_shader_tokens.h"
  33 #include "util/u_debug.h"
  34 #include "util/u_memory.h"
  35 #include "util/u_simple_shaders.h"
  36 #include "util/u_upload_mgr.h"
  37 #include "util/u_math.h"
  38 #include "vl/vl_decoder.h"
  39 #include "vl/vl_video_buffer.h"
  40 #include "radeon_video.h"
  41 #include "radeon_uvd.h"
  42 #include "util/os_time.h"
  43
  44 static const struct debug_named_value r600_debug_options[] = {
  45         /* features */
  46         { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
  47
  48         /* shader backend */
  49         { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
  50         { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
  51         { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
  52         { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
  53         { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
  54         { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
  55         { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
  56         { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
  57
  58         DEBUG_NAMED_VALUE_END /* must be last */
  59 };
  60
  61 /*
  62  * pipe_context
  63  */
  64
  65 static void r600_destroy_context(struct pipe_context *context)
  66 {
  67         struct r600_context *rctx = (struct r600_context *)context;
  68         unsigned sh;
  69
  70         r600_isa_destroy(rctx->isa);
  71
  72         r600_sb_context_destroy(rctx->sb_context);
  73
  74         r600_resource_reference(&rctx->dummy_cmask, NULL);
  75         r600_resource_reference(&rctx->dummy_fmask, NULL);
  76
  77         if (rctx->append_fence)
  78                 pipe_resource_reference((struct pipe_resource**)&rctx->append_fence, NULL);
  79         for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
  80                 rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, NULL);
  81                 free(rctx->driver_consts[sh].constants);
  82         }
  83
  84         if (rctx->fixed_func_tcs_shader)
  85                 rctx->b.b.delete_tcs_state(&rctx->b.b, rctx->fixed_func_tcs_shader);
  86
  87         if (rctx->dummy_pixel_shader) {
  88                 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
  89         }
  90         if (rctx->custom_dsa_flush) {
  91                 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
  92         }
  93         if (rctx->custom_blend_resolve) {
  94                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
  95         }
  96         if (rctx->custom_blend_decompress) {
  97                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
  98         }
  99         if (rctx->custom_blend_fastclear) {
 100                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
 101         }
 102         util_unreference_framebuffer_state(&rctx->framebuffer.state);
 103
 104         if (rctx->blitter) {
 105                 util_blitter_destroy(rctx->blitter);
 106         }
 107         if (rctx->allocator_fetch_shader) {
 108                 u_suballocator_destroy(rctx->allocator_fetch_shader);
 109         }
 110
 111         r600_release_command_buffer(&rctx->start_cs_cmd);
 112
 113         FREE(rctx->start_compute_cs_cmd.buf);
 114
 115         r600_common_context_cleanup(&rctx->b);
 116
 117         r600_resource_reference(&rctx->trace_buf, NULL);
 118         r600_resource_reference(&rctx->last_trace_buf, NULL);
 119         radeon_clear_saved_cs(&rctx->last_gfx);
 120
 121         FREE(rctx);
 122 }
 123
 124 static struct pipe_context *r600_create_context(struct pipe_screen *screen,
 125                                                 void *priv, unsigned flags)
 126 {
 127         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 128         struct r600_screen* rscreen = (struct r600_screen *)screen;
 129         struct radeon_winsys *ws = rscreen->b.ws;
 130
 131         if (!rctx)
 132                 return NULL;
 133
 134         rctx->b.b.screen = screen;
 135         assert(!priv);
 136         rctx->b.b.priv = NULL; /* for threaded_context_unwrap_sync */
 137         rctx->b.b.destroy = r600_destroy_context;
 138         rctx->b.set_atom_dirty = (void *)r600_set_atom_dirty;
 139
 140         if (!r600_common_context_init(&rctx->b, &rscreen->b, flags))
 141                 goto fail;
 142
 143         rctx->screen = rscreen;
 144         LIST_INITHEAD(&rctx->texture_buffers);
 145
 146         r600_init_blit_functions(rctx);
 147
 148         if (rscreen->b.info.has_hw_decode) {
 149                 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
 150                 rctx->b.b.create_video_buffer = r600_video_buffer_create;
 151         } else {
 152                 rctx->b.b.create_video_codec = vl_create_decoder;
 153                 rctx->b.b.create_video_buffer = vl_video_buffer_create;
 154         }
 155
 156         if (getenv("R600_TRACE"))
 157                 rctx->is_debug = true;
 158         r600_init_common_state_functions(rctx);
 159
 160         switch (rctx->b.chip_class) {
 161         case R600:
 162         case R700:
 163                 r600_init_state_functions(rctx);
 164                 r600_init_atom_start_cs(rctx);
 165                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 166                 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
 167                                                                       : r600_create_resolve_blend(rctx);
 168                 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
 169                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
 170                                            rctx->b.family == CHIP_RV620 ||
 171                                            rctx->b.family == CHIP_RS780 ||
 172                                            rctx->b.family == CHIP_RS880 ||
 173                                            rctx->b.family == CHIP_RV710);
 174                 break;
 175         case EVERGREEN:
 176         case CAYMAN:
 177                 evergreen_init_state_functions(rctx);
 178                 evergreen_init_atom_start_cs(rctx);
 179                 evergreen_init_atom_start_compute_cs(rctx);
 180                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 181                 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
 182                 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
 183                 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
 184                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
 185                                            rctx->b.family == CHIP_PALM ||
 186                                            rctx->b.family == CHIP_SUMO ||
 187                                            rctx->b.family == CHIP_SUMO2 ||
 188                                            rctx->b.family == CHIP_CAICOS ||
 189                                            rctx->b.family == CHIP_CAYMAN ||
 190                                            rctx->b.family == CHIP_ARUBA);
 191
 192                 rctx->append_fence = pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
 193                                                          PIPE_USAGE_DEFAULT, 32);
 194                 break;
 195         default:
 196                 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
 197                 goto fail;
 198         }
 199
 200         rctx->b.gfx.cs = ws->cs_create(rctx->b.ctx, RING_GFX,
 201                                        r600_context_gfx_flush, rctx);
 202         rctx->b.gfx.flush = r600_context_gfx_flush;
 203
 204         rctx->allocator_fetch_shader =
 205                 u_suballocator_create(&rctx->b.b, 64 * 1024,
 206                                       0, PIPE_USAGE_DEFAULT, 0, FALSE);
 207         if (!rctx->allocator_fetch_shader)
 208                 goto fail;
 209
 210         rctx->isa = calloc(1, sizeof(struct r600_isa));
 211         if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
 212                 goto fail;
 213
 214         if (rscreen->b.debug_flags & DBG_FORCE_DMA)
 215                 rctx->b.b.resource_copy_region = rctx->b.dma_copy;
 216
 217         rctx->blitter = util_blitter_create(&rctx->b.b);
 218         if (rctx->blitter == NULL)
 219                 goto fail;
 220         util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
 221         rctx->blitter->draw_rectangle = r600_draw_rectangle;
 222
 223         r600_begin_new_cs(rctx);
 224
 225         rctx->dummy_pixel_shader =
 226                 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
 227                                                      TGSI_SEMANTIC_GENERIC,
 228                                                      TGSI_INTERPOLATE_CONSTANT);
 229         rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 230
 231         return &rctx->b.b;
 232
 233 fail:
 234         r600_destroy_context(&rctx->b.b);
 235         return NULL;
 236 }
 237
 238 /*
 239  * pipe_screen
 240  */
 241
 242 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 243 {
 244         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 245         enum radeon_family family = rscreen->b.family;
 246
 247         switch (param) {
 248         /* Supported features (boolean caps). */
 249         case PIPE_CAP_NPOT_TEXTURES:
 250         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 251         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 252         case PIPE_CAP_TWO_SIDED_STENCIL:
 253         case PIPE_CAP_ANISOTROPIC_FILTER:
 254         case PIPE_CAP_POINT_SPRITE:
 255         case PIPE_CAP_OCCLUSION_QUERY:
 256         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 257         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 258         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 259         case PIPE_CAP_TEXTURE_SWIZZLE:
 260         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 261         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 262         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 263         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 264         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 265         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 266         case PIPE_CAP_SM3:
 267         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 268         case PIPE_CAP_PRIMITIVE_RESTART:
 269         case PIPE_CAP_CONDITIONAL_RENDER:
 270         case PIPE_CAP_TEXTURE_BARRIER:
 271         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 272         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 273         case PIPE_CAP_TGSI_INSTANCEID:
 274         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 275         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 276         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 277         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 278         case PIPE_CAP_START_INSTANCE:
 279         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 280         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 281         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 282         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 283         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 284         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 285         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 286         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 287         case PIPE_CAP_SAMPLE_SHADING:
 288         case PIPE_CAP_CLIP_HALFZ:
 289         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 290         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 291         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 292         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 293         case PIPE_CAP_TGSI_TXQS:
 294         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 295         case PIPE_CAP_INVALIDATE_BUFFER:
 296         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 297         case PIPE_CAP_QUERY_MEMORY_INFO:
 298         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 299         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 300         case PIPE_CAP_CLEAR_TEXTURE:
 301         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 302         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 303         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 304                 return 1;
 305
 306         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 307                 return rscreen->b.info.drm_major == 2 && rscreen->b.info.drm_minor >= 43;
 308
 309         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 310                 return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;
 311
 312         case PIPE_CAP_COMPUTE:
 313                 return rscreen->b.chip_class > R700;
 314
 315         case PIPE_CAP_TGSI_TEXCOORD:
 316                 return 0;
 317
 318         case PIPE_CAP_FAKE_SW_MSAA:
 319                 return 0;
 320
 321         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 322                 return MIN2(rscreen->b.info.max_alloc_size, INT_MAX);
 323
 324         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 325                 return R600_MAP_BUFFER_ALIGNMENT;
 326
 327         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 328                 return 256;
 329
 330         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 331                 return 1;
 332
 333         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 334                 if (family >= CHIP_CEDAR)
 335                    return 420;
 336                 /* pre-evergreen geom shaders need newer kernel */
 337                 if (rscreen->b.info.drm_minor >= 37)
 338                    return 330;
 339                 return 140;
 340
 341         /* Supported except the original R600. */
 342         case PIPE_CAP_INDEP_BLEND_ENABLE:
 343         case PIPE_CAP_INDEP_BLEND_FUNC:
 344                 /* R600 doesn't support per-MRT blends */
 345                 return family == CHIP_R600 ? 0 : 1;
 346
 347         /* Supported on Evergreen. */
 348         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 349         case PIPE_CAP_CUBE_MAP_ARRAY:
 350         case PIPE_CAP_TEXTURE_GATHER_SM5:
 351         case PIPE_CAP_TEXTURE_QUERY_LOD:
 352         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 353         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 354         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 355                 return family >= CHIP_CEDAR ? 1 : 0;
 356         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 357                 return family >= CHIP_CEDAR ? 4 : 0;
 358         case PIPE_CAP_DRAW_INDIRECT:
 359                 /* kernel command checker support is also required */
 360                 return family >= CHIP_CEDAR && rscreen->b.info.drm_minor >= 41;
 361
 362         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 363                 return family >= CHIP_CEDAR ? 0 : 1;
 364
 365         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 366                 return 8;
 367
 368         /* Unsupported features. */
 369         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 370         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 371         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 372         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 373         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 374         case PIPE_CAP_USER_VERTEX_BUFFERS:
 375         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 376         case PIPE_CAP_VERTEXID_NOBASE:
 377         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 378         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 379         case PIPE_CAP_SHAREABLE_SHADERS:
 380         case PIPE_CAP_DRAW_PARAMETERS:
 381         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 382         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 383         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 384         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 385         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 386         case PIPE_CAP_GENERATE_MIPMAP:
 387         case PIPE_CAP_STRING_MARKER:
 388         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 389         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 390         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 391         case PIPE_CAP_TGSI_VOTE:
 392         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 393         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 394         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 395         case PIPE_CAP_NATIVE_FENCE_FD:
 396         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 397         case PIPE_CAP_TGSI_FS_FBFETCH:
 398         case PIPE_CAP_INT64:
 399         case PIPE_CAP_INT64_DIVMOD:
 400         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 401         case PIPE_CAP_TGSI_CLOCK:
 402         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 403         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 404         case PIPE_CAP_TGSI_BALLOT:
 405         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 406         case PIPE_CAP_POST_DEPTH_COVERAGE:
 407         case PIPE_CAP_BINDLESS_TEXTURE:
 408         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 409         case PIPE_CAP_QUERY_SO_OVERFLOW:
 410         case PIPE_CAP_MEMOBJ:
 411         case PIPE_CAP_LOAD_CONSTBUF:
 412         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 413         case PIPE_CAP_TILE_RASTER_ORDER:
 414         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 415                 return 0;
 416
 417         case PIPE_CAP_DOUBLES:
 418                 if (rscreen->b.family == CHIP_ARUBA ||
 419                     rscreen->b.family == CHIP_CAYMAN ||
 420                     rscreen->b.family == CHIP_CYPRESS ||
 421                     rscreen->b.family == CHIP_HEMLOCK)
 422                         return 1;
 423                 return 0;
 424         case PIPE_CAP_CULL_DISTANCE:
 425                 return 1;
 426
 427         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 428                 if (family >= CHIP_CEDAR)
 429                         return 30;
 430                 else
 431                         return 0;
 432         /* Stream output. */
 433         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 434                 return rscreen->b.has_streamout ? 4 : 0;
 435         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 436         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 437                 return rscreen->b.has_streamout ? 1 : 0;
 438         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 439         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 440                 return 32*4;
 441
 442         /* Geometry shader output. */
 443         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 444                 return 1024;
 445         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 446                 return 16384;
 447         case PIPE_CAP_MAX_VERTEX_STREAMS:
 448                 return family >= CHIP_CEDAR ? 4 : 1;
 449
 450         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 451                 return 2047;
 452
 453         /* Texturing. */
 454         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 455         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 456                 if (family >= CHIP_CEDAR)
 457                         return 15;
 458                 else
 459                         return 14;
 460         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 461                 /* textures support 8192, but layered rendering supports 2048 */
 462                 return 12;
 463         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 464                 /* textures support 8192, but layered rendering supports 2048 */
 465                 return 2048;
 466
 467         /* Render targets. */
 468         case PIPE_CAP_MAX_RENDER_TARGETS:
 469                 /* XXX some r6xx are buggy and can only do 4 */
 470                 return 8;
 471
 472         case PIPE_CAP_MAX_VIEWPORTS:
 473                 return R600_MAX_VIEWPORTS;
 474         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 475                 return 8;
 476
 477         /* Timer queries, present when the clock frequency is non zero. */
 478         case PIPE_CAP_QUERY_TIME_ELAPSED:
 479                 return rscreen->b.info.clock_crystal_freq != 0;
 480         case PIPE_CAP_QUERY_TIMESTAMP:
 481                 return rscreen->b.info.drm_minor >= 20 &&
 482                        rscreen->b.info.clock_crystal_freq != 0;
 483
 484         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 485         case PIPE_CAP_MIN_TEXEL_OFFSET:
 486                 return -8;
 487
 488         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 489         case PIPE_CAP_MAX_TEXEL_OFFSET:
 490                 return 7;
 491
 492         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 493                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 494         case PIPE_CAP_ENDIANNESS:
 495                 return PIPE_ENDIAN_LITTLE;
 496
 497         case PIPE_CAP_VENDOR_ID:
 498                 return ATI_VENDOR_ID;
 499         case PIPE_CAP_DEVICE_ID:
 500                 return rscreen->b.info.pci_id;
 501         case PIPE_CAP_ACCELERATED:
 502                 return 1;
 503         case PIPE_CAP_VIDEO_MEMORY:
 504                 return rscreen->b.info.vram_size >> 20;
 505         case PIPE_CAP_UMA:
 506                 return 0;
 507         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 508                 return rscreen->b.chip_class >= R700;
 509         case PIPE_CAP_PCI_GROUP:
 510                 return rscreen->b.info.pci_domain;
 511         case PIPE_CAP_PCI_BUS:
 512                 return rscreen->b.info.pci_bus;
 513         case PIPE_CAP_PCI_DEVICE:
 514                 return rscreen->b.info.pci_dev;
 515         case PIPE_CAP_PCI_FUNCTION:
 516                 return rscreen->b.info.pci_func;
 517         }
 518         return 0;
 519 }
 520
 521 static int r600_get_shader_param(struct pipe_screen* pscreen,
 522                                  enum pipe_shader_type shader,
 523                                  enum pipe_shader_cap param)
 524 {
 525         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 526
 527         switch(shader)
 528         {
 529         case PIPE_SHADER_FRAGMENT:
 530         case PIPE_SHADER_VERTEX:
 531         case PIPE_SHADER_COMPUTE:
 532                 break;
 533         case PIPE_SHADER_GEOMETRY:
 534                 if (rscreen->b.family >= CHIP_CEDAR)
 535                         break;
 536                 /* pre-evergreen geom shaders need newer kernel */
 537                 if (rscreen->b.info.drm_minor >= 37)
 538                         break;
 539                 return 0;
 540         case PIPE_SHADER_TESS_CTRL:
 541         case PIPE_SHADER_TESS_EVAL:
 542                 if (rscreen->b.family >= CHIP_CEDAR)
 543                         break;
 544         default:
 545                 return 0;
 546         }
 547
 548         switch (param) {
 549         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 550         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 551         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 552         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 553                 return 16384;
 554         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 555                 return 32;
 556         case PIPE_SHADER_CAP_MAX_INPUTS:
 557                 return shader == PIPE_SHADER_VERTEX ? 16 : 32;
 558         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 559                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 560         case PIPE_SHADER_CAP_MAX_TEMPS:
 561                 return 256; /* Max native temporaries. */
 562         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 563                 if (shader == PIPE_SHADER_COMPUTE) {
 564                         uint64_t max_const_buffer_size;
 565                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 566                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 567                                 &max_const_buffer_size);
 568                         return MIN2(max_const_buffer_size, INT_MAX);
 569
 570                 } else {
 571                         return R600_MAX_CONST_BUFFER_SIZE;
 572                 }
 573         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 574                 return R600_MAX_USER_CONST_BUFFERS;
 575         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 576                 return 1;
 577         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 578                 return 1;
 579         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 580         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 581         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 582         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 583                 return 1;
 584         case PIPE_SHADER_CAP_SUBROUTINES:
 585         case PIPE_SHADER_CAP_INT64_ATOMICS:
 586         case PIPE_SHADER_CAP_FP16:
 587                 return 0;
 588         case PIPE_SHADER_CAP_INTEGERS:
 589         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 590                 return 1;
 591         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 592         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 593                 return 16;
 594         case PIPE_SHADER_CAP_PREFERRED_IR:
 595                 if (shader == PIPE_SHADER_COMPUTE) {
 596                         return PIPE_SHADER_IR_NATIVE;
 597                 } else {
 598                         return PIPE_SHADER_IR_TGSI;
 599                 }
 600         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 601                 return 0;
 602         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 603                 if (rscreen->b.family == CHIP_ARUBA ||
 604                     rscreen->b.family == CHIP_CAYMAN ||
 605                     rscreen->b.family == CHIP_CYPRESS ||
 606                     rscreen->b.family == CHIP_HEMLOCK)
 607                         return 1;
 608                 return 0;
 609         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 610         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 611         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 612         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 613         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 614         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 615                 return 0;
 616         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 617                 if (rscreen->b.family >= CHIP_CEDAR &&
 618                     (shader == PIPE_SHADER_FRAGMENT))
 619                     return 8;
 620                 return 0;
 621         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 622                 if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
 623                         return 8;
 624                 return 0;
 625         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 626                 /* having to allocate the atomics out amongst shaders stages is messy,
 627                    so give compute 8 buffers and all the others one */
 628                 if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics) {
 629                         return EG_MAX_ATOMIC_BUFFERS;
 630                 }
 631                 return 0;
 632         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 633                 /* due to a bug in the shader compiler, some loops hang
 634                  * if they are not unrolled, see:
 635                  *    https://bugs.freedesktop.org/show_bug.cgi?id=86720
 636                  */
 637                 return 255;
 638         }
 639         return 0;
 640 }
 641
 642 static void r600_destroy_screen(struct pipe_screen* pscreen)
 643 {
 644         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 645
 646         if (!rscreen)
 647                 return;
 648
 649         if (!rscreen->b.ws->unref(rscreen->b.ws))
 650                 return;
 651
 652         if (rscreen->global_pool) {
 653                 compute_memory_pool_delete(rscreen->global_pool);
 654         }
 655
 656         r600_destroy_common_screen(&rscreen->b);
 657 }
 658
 659 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
 660                                                   const struct pipe_resource *templ)
 661 {
 662         if (templ->target == PIPE_BUFFER &&
 663             (templ->bind & PIPE_BIND_GLOBAL))
 664                 return r600_compute_global_buffer_create(screen, templ);
 665
 666         return r600_resource_create_common(screen, templ);
 667 }
 668
 669 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws,
 670                                        const struct pipe_screen_config *config)
 671 {
 672         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 673
 674         if (!rscreen) {
 675                 return NULL;
 676         }
 677
 678         /* Set functions first. */
 679         rscreen->b.b.context_create = r600_create_context;
 680         rscreen->b.b.destroy = r600_destroy_screen;
 681         rscreen->b.b.get_param = r600_get_param;
 682         rscreen->b.b.get_shader_param = r600_get_shader_param;
 683         rscreen->b.b.resource_create = r600_resource_create;
 684
 685         if (!r600_common_screen_init(&rscreen->b, ws)) {
 686                 FREE(rscreen);
 687                 return NULL;
 688         }
 689
 690         if (rscreen->b.info.chip_class >= EVERGREEN) {
 691                 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
 692         } else {
 693                 rscreen->b.b.is_format_supported = r600_is_format_supported;
 694         }
 695
 696         rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
 697         if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
 698                 rscreen->b.debug_flags |= DBG_COMPUTE;
 699         if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
 700                 rscreen->b.debug_flags |= DBG_ALL_SHADERS | DBG_FS;
 701         if (!debug_get_bool_option("R600_HYPERZ", TRUE))
 702                 rscreen->b.debug_flags |= DBG_NO_HYPERZ;
 703
 704         if (rscreen->b.family == CHIP_UNKNOWN) {
 705                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
 706                 FREE(rscreen);
 707                 return NULL;
 708         }
 709
 710         /* Figure out streamout kernel support. */
 711         switch (rscreen->b.chip_class) {
 712         case R600:
 713                 if (rscreen->b.family < CHIP_RS780) {
 714                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 715                 } else {
 716                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
 717                 }
 718                 break;
 719         case R700:
 720                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
 721                 break;
 722         case EVERGREEN:
 723         case CAYMAN:
 724                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 725                 break;
 726         default:
 727                 rscreen->b.has_streamout = FALSE;
 728                 break;
 729         }
 730
 731         /* MSAA support. */
 732         switch (rscreen->b.chip_class) {
 733         case R600:
 734         case R700:
 735                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
 736                 rscreen->has_compressed_msaa_texturing = false;
 737                 break;
 738         case EVERGREEN:
 739                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 740                 rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
 741                 break;
 742         case CAYMAN:
 743                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 744                 rscreen->has_compressed_msaa_texturing = true;
 745                 break;
 746         default:
 747                 rscreen->has_msaa = FALSE;
 748                 rscreen->has_compressed_msaa_texturing = false;
 749         }
 750
 751         rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
 752                               !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
 753
 754         rscreen->b.barrier_flags.cp_to_L2 =
 755                 R600_CONTEXT_INV_VERTEX_CACHE |
 756                 R600_CONTEXT_INV_TEX_CACHE |
 757                 R600_CONTEXT_INV_CONST_CACHE;
 758         rscreen->b.barrier_flags.compute_to_L2 = R600_CONTEXT_PS_PARTIAL_FLUSH;
 759
 760         rscreen->global_pool = compute_memory_pool_new(rscreen);
 761
 762         /* Create the auxiliary context. This must be done last. */
 763         rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL, 0);
 764
 765         rscreen->has_atomics = rscreen->b.info.drm_minor >= 44;
 766 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
 767         struct pipe_resource templ = {};
 768
 769         templ.width0 = 4;
 770         templ.height0 = 2048;
 771         templ.depth0 = 1;
 772         templ.array_size = 1;
 773         templ.target = PIPE_TEXTURE_2D;
 774         templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
 775         templ.usage = PIPE_USAGE_DEFAULT;
 776
 777         struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
 778         unsigned char *map = ws->buffer_map(res->buf, NULL, PIPE_TRANSFER_WRITE);
 779
 780         memset(map, 0, 256);
 781
 782         r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
 783         r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
 784         r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
 785         r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
 786         r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
 787
 788         ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
 789
 790         int i;
 791         for (i = 0; i < 256; i++) {
 792                 printf("%02X", map[i]);
 793                 if (i % 16 == 15)
 794                         printf("\n");
 795         }
 796 #endif
 797
 798         if (rscreen->b.debug_flags & DBG_TEST_DMA)
 799                 r600_test_dma(&rscreen->b);
 800
 801         r600_query_fix_enabled_rb_mask(&rscreen->b);
 802         return &rscreen->b.b;
 803 }