src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25 #include "r600_isa.h"
  26 #include "evergreen_compute.h"
  27 #include "r600d.h"
  28
  29 #include "sb/sb_public.h"
  30
  31 #include <errno.h>
  32 #include "pipe/p_shader_tokens.h"
  33 #include "util/u_blitter.h"
  34 #include "util/u_debug.h"
  35 #include "util/u_memory.h"
  36 #include "util/u_simple_shaders.h"
  37 #include "util/u_upload_mgr.h"
  38 #include "util/u_math.h"
  39 #include "vl/vl_decoder.h"
  40 #include "vl/vl_video_buffer.h"
  41 #include "radeon/radeon_uvd.h"
  42 #include "os/os_time.h"
  43
  44 static const struct debug_named_value r600_debug_options[] = {
  45         /* features */
  46 #if defined(R600_USE_LLVM)
  47         { "nollvm", DBG_NO_LLVM, "Disable the LLVM shader compiler" },
  48 #endif
  49         { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
  50         { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
  51
  52         /* shader backend */
  53         { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
  54         { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
  55         { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
  56         { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
  57         { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
  58         { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
  59         { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
  60         { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
  61
  62         DEBUG_NAMED_VALUE_END /* must be last */
  63 };
  64
  65 /*
  66  * pipe_context
  67  */
  68
  69 static void r600_flush(struct pipe_context *ctx, unsigned flags)
  70 {
  71         struct r600_context *rctx = (struct r600_context *)ctx;
  72         struct pipe_query *render_cond = NULL;
  73         unsigned render_cond_mode = 0;
  74         boolean render_cond_cond = FALSE;
  75
  76         if (rctx->b.rings.gfx.cs->cdw == rctx->initial_gfx_cs_size)
  77                 return;
  78
  79         rctx->b.rings.gfx.flushing = true;
  80         /* Disable render condition. */
  81         if (rctx->b.current_render_cond) {
  82                 render_cond = rctx->b.current_render_cond;
  83                 render_cond_cond = rctx->b.current_render_cond_cond;
  84                 render_cond_mode = rctx->b.current_render_cond_mode;
  85                 ctx->render_condition(ctx, NULL, FALSE, 0);
  86         }
  87
  88         r600_context_flush(rctx, flags);
  89         rctx->b.rings.gfx.flushing = false;
  90         r600_begin_new_cs(rctx);
  91
  92         /* Re-enable render condition. */
  93         if (render_cond) {
  94                 ctx->render_condition(ctx, render_cond, render_cond_cond, render_cond_mode);
  95         }
  96
  97         rctx->initial_gfx_cs_size = rctx->b.rings.gfx.cs->cdw;
  98 }
  99
 100 static void r600_flush_from_st(struct pipe_context *ctx,
 101                                struct pipe_fence_handle **fence,
 102                                unsigned flags)
 103 {
 104         struct r600_context *rctx = (struct r600_context *)ctx;
 105         unsigned fflags;
 106
 107         fflags = flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0;
 108         if (fence) {
 109                 *fence = rctx->b.ws->cs_create_fence(rctx->b.rings.gfx.cs);
 110         }
 111         /* flush gfx & dma ring, order does not matter as only one can be live */
 112         if (rctx->b.rings.dma.cs) {
 113                 rctx->b.rings.dma.flush(rctx, fflags);
 114         }
 115         rctx->b.rings.gfx.flush(rctx, fflags);
 116 }
 117
 118 static void r600_flush_gfx_ring(void *ctx, unsigned flags)
 119 {
 120         r600_flush((struct pipe_context*)ctx, flags);
 121 }
 122
 123 static void r600_flush_dma_ring(void *ctx, unsigned flags)
 124 {
 125         struct r600_context *rctx = (struct r600_context *)ctx;
 126         struct radeon_winsys_cs *cs = rctx->b.rings.dma.cs;
 127
 128         if (!cs->cdw) {
 129                 return;
 130         }
 131
 132         rctx->b.rings.dma.flushing = true;
 133         rctx->b.ws->cs_flush(cs, flags, 0);
 134         rctx->b.rings.dma.flushing = false;
 135 }
 136
 137 static void r600_flush_from_winsys(void *ctx, unsigned flags)
 138 {
 139         struct r600_context *rctx = (struct r600_context *)ctx;
 140
 141         rctx->b.rings.gfx.flush(rctx, flags);
 142 }
 143
 144 static void r600_flush_dma_from_winsys(void *ctx, unsigned flags)
 145 {
 146         struct r600_context *rctx = (struct r600_context *)ctx;
 147
 148         rctx->b.rings.dma.flush(rctx, flags);
 149 }
 150
 151 static void r600_destroy_context(struct pipe_context *context)
 152 {
 153         struct r600_context *rctx = (struct r600_context *)context;
 154
 155         r600_isa_destroy(rctx->isa);
 156
 157         r600_sb_context_destroy(rctx->sb_context);
 158
 159         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
 160         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
 161
 162         if (rctx->dummy_pixel_shader) {
 163                 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 164         }
 165         if (rctx->custom_dsa_flush) {
 166                 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
 167         }
 168         if (rctx->custom_blend_resolve) {
 169                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
 170         }
 171         if (rctx->custom_blend_decompress) {
 172                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
 173         }
 174         if (rctx->custom_blend_fastclear) {
 175                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
 176         }
 177         util_unreference_framebuffer_state(&rctx->framebuffer.state);
 178
 179         if (rctx->blitter) {
 180                 util_blitter_destroy(rctx->blitter);
 181         }
 182         if (rctx->allocator_fetch_shader) {
 183                 u_suballocator_destroy(rctx->allocator_fetch_shader);
 184         }
 185
 186         r600_release_command_buffer(&rctx->start_cs_cmd);
 187
 188         FREE(rctx->start_compute_cs_cmd.buf);
 189
 190         r600_common_context_cleanup(&rctx->b);
 191         FREE(rctx);
 192 }
 193
 194 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 195 {
 196         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 197         struct r600_screen* rscreen = (struct r600_screen *)screen;
 198
 199         if (rctx == NULL)
 200                 return NULL;
 201
 202         rctx->b.b.screen = screen;
 203         rctx->b.b.priv = priv;
 204         rctx->b.b.destroy = r600_destroy_context;
 205         rctx->b.b.flush = r600_flush_from_st;
 206
 207         if (!r600_common_context_init(&rctx->b, &rscreen->b))
 208                 goto fail;
 209
 210         rctx->screen = rscreen;
 211         rctx->keep_tiling_flags = rscreen->b.info.drm_minor >= 12;
 212
 213         r600_init_blit_functions(rctx);
 214         r600_init_context_resource_functions(rctx);
 215
 216         if (rscreen->b.info.has_uvd) {
 217                 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
 218                 rctx->b.b.create_video_buffer = r600_video_buffer_create;
 219         } else {
 220                 rctx->b.b.create_video_codec = vl_create_decoder;
 221                 rctx->b.b.create_video_buffer = vl_video_buffer_create;
 222         }
 223
 224         r600_init_common_state_functions(rctx);
 225
 226         switch (rctx->b.chip_class) {
 227         case R600:
 228         case R700:
 229                 r600_init_state_functions(rctx);
 230                 r600_init_atom_start_cs(rctx);
 231                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 232                 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
 233                                                                       : r600_create_resolve_blend(rctx);
 234                 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
 235                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
 236                                            rctx->b.family == CHIP_RV620 ||
 237                                            rctx->b.family == CHIP_RS780 ||
 238                                            rctx->b.family == CHIP_RS880 ||
 239                                            rctx->b.family == CHIP_RV710);
 240                 break;
 241         case EVERGREEN:
 242         case CAYMAN:
 243                 evergreen_init_state_functions(rctx);
 244                 evergreen_init_atom_start_cs(rctx);
 245                 evergreen_init_atom_start_compute_cs(rctx);
 246                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 247                 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
 248                 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
 249                 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
 250                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
 251                                            rctx->b.family == CHIP_PALM ||
 252                                            rctx->b.family == CHIP_SUMO ||
 253                                            rctx->b.family == CHIP_SUMO2 ||
 254                                            rctx->b.family == CHIP_CAICOS ||
 255                                            rctx->b.family == CHIP_CAYMAN ||
 256                                            rctx->b.family == CHIP_ARUBA);
 257                 break;
 258         default:
 259                 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
 260                 goto fail;
 261         }
 262
 263         if (rscreen->trace_bo) {
 264                 rctx->b.rings.gfx.cs = rctx->b.ws->cs_create(rctx->b.ws, RING_GFX, rscreen->trace_bo->cs_buf);
 265         } else {
 266                 rctx->b.rings.gfx.cs = rctx->b.ws->cs_create(rctx->b.ws, RING_GFX, NULL);
 267         }
 268         rctx->b.rings.gfx.flush = r600_flush_gfx_ring;
 269         rctx->b.ws->cs_set_flush_callback(rctx->b.rings.gfx.cs, r600_flush_from_winsys, rctx);
 270         rctx->b.rings.gfx.flushing = false;
 271
 272         rctx->b.rings.dma.cs = NULL;
 273         if (rscreen->b.info.r600_has_dma && !(rscreen->b.debug_flags & DBG_NO_ASYNC_DMA)) {
 274                 rctx->b.rings.dma.cs = rctx->b.ws->cs_create(rctx->b.ws, RING_DMA, NULL);
 275                 rctx->b.rings.dma.flush = r600_flush_dma_ring;
 276                 rctx->b.ws->cs_set_flush_callback(rctx->b.rings.dma.cs, r600_flush_dma_from_winsys, rctx);
 277                 rctx->b.rings.dma.flushing = false;
 278         }
 279
 280         rctx->allocator_fetch_shader = u_suballocator_create(&rctx->b.b, 64 * 1024, 256,
 281                                                              0, PIPE_USAGE_STATIC, FALSE);
 282         if (!rctx->allocator_fetch_shader)
 283                 goto fail;
 284
 285         rctx->isa = calloc(1, sizeof(struct r600_isa));
 286         if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
 287                 goto fail;
 288
 289         rctx->blitter = util_blitter_create(&rctx->b.b);
 290         if (rctx->blitter == NULL)
 291                 goto fail;
 292         util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
 293         rctx->blitter->draw_rectangle = r600_draw_rectangle;
 294
 295         r600_begin_new_cs(rctx);
 296         r600_query_init_backend_mask(&rctx->b); /* this emits commands and must be last */
 297
 298         rctx->dummy_pixel_shader =
 299                 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
 300                                                      TGSI_SEMANTIC_GENERIC,
 301                                                      TGSI_INTERPOLATE_CONSTANT);
 302         rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 303
 304         return &rctx->b.b;
 305
 306 fail:
 307         r600_destroy_context(&rctx->b.b);
 308         return NULL;
 309 }
 310
 311 /*
 312  * pipe_screen
 313  */
 314 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 315 {
 316         return "X.Org";
 317 }
 318
 319 static const char *r600_get_family_name(enum radeon_family family)
 320 {
 321         switch(family) {
 322         case CHIP_R600: return "AMD R600";
 323         case CHIP_RV610: return "AMD RV610";
 324         case CHIP_RV630: return "AMD RV630";
 325         case CHIP_RV670: return "AMD RV670";
 326         case CHIP_RV620: return "AMD RV620";
 327         case CHIP_RV635: return "AMD RV635";
 328         case CHIP_RS780: return "AMD RS780";
 329         case CHIP_RS880: return "AMD RS880";
 330         case CHIP_RV770: return "AMD RV770";
 331         case CHIP_RV730: return "AMD RV730";
 332         case CHIP_RV710: return "AMD RV710";
 333         case CHIP_RV740: return "AMD RV740";
 334         case CHIP_CEDAR: return "AMD CEDAR";
 335         case CHIP_REDWOOD: return "AMD REDWOOD";
 336         case CHIP_JUNIPER: return "AMD JUNIPER";
 337         case CHIP_CYPRESS: return "AMD CYPRESS";
 338         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 339         case CHIP_PALM: return "AMD PALM";
 340         case CHIP_SUMO: return "AMD SUMO";
 341         case CHIP_SUMO2: return "AMD SUMO2";
 342         case CHIP_BARTS: return "AMD BARTS";
 343         case CHIP_TURKS: return "AMD TURKS";
 344         case CHIP_CAICOS: return "AMD CAICOS";
 345         case CHIP_CAYMAN: return "AMD CAYMAN";
 346         case CHIP_ARUBA: return "AMD ARUBA";
 347         default: return "AMD unknown";
 348         }
 349 }
 350
 351 static const char* r600_get_name(struct pipe_screen* pscreen)
 352 {
 353         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 354
 355         return r600_get_family_name(rscreen->b.family);
 356 }
 357
 358 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 359 {
 360         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 361         enum radeon_family family = rscreen->b.family;
 362
 363         switch (param) {
 364         /* Supported features (boolean caps). */
 365         case PIPE_CAP_NPOT_TEXTURES:
 366         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 367         case PIPE_CAP_TWO_SIDED_STENCIL:
 368         case PIPE_CAP_ANISOTROPIC_FILTER:
 369         case PIPE_CAP_POINT_SPRITE:
 370         case PIPE_CAP_OCCLUSION_QUERY:
 371         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 372         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 373         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 374         case PIPE_CAP_TEXTURE_SWIZZLE:
 375         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 376         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 377         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 378         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 379         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 380         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 381         case PIPE_CAP_SM3:
 382         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 383         case PIPE_CAP_PRIMITIVE_RESTART:
 384         case PIPE_CAP_CONDITIONAL_RENDER:
 385         case PIPE_CAP_TEXTURE_BARRIER:
 386         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 387         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 388         case PIPE_CAP_TGSI_INSTANCEID:
 389         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 390         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 391         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 392         case PIPE_CAP_USER_INDEX_BUFFERS:
 393         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 394         case PIPE_CAP_COMPUTE:
 395         case PIPE_CAP_START_INSTANCE:
 396         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 397         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 398         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 399         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 400         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 401                 return 1;
 402
 403         case PIPE_CAP_TGSI_TEXCOORD:
 404                 return 0;
 405
 406         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 407                 return MIN2(rscreen->b.info.vram_size, 0xFFFFFFFF);
 408
 409         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 410                 return R600_MAP_BUFFER_ALIGNMENT;
 411
 412         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 413                 return 256;
 414
 415         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 416                 return 1;
 417
 418         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 419                 return 140;
 420
 421         /* Supported except the original R600. */
 422         case PIPE_CAP_INDEP_BLEND_ENABLE:
 423         case PIPE_CAP_INDEP_BLEND_FUNC:
 424                 /* R600 doesn't support per-MRT blends */
 425                 return family == CHIP_R600 ? 0 : 1;
 426
 427         /* Supported on Evergreen. */
 428         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 429         case PIPE_CAP_CUBE_MAP_ARRAY:
 430                 return family >= CHIP_CEDAR ? 1 : 0;
 431
 432         /* Unsupported features. */
 433         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 434         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 435         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 436         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 437         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 438         case PIPE_CAP_USER_VERTEX_BUFFERS:
 439         case PIPE_CAP_TGSI_VS_LAYER:
 440                 return 0;
 441
 442         /* Stream output. */
 443         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 444                 return rscreen->b.has_streamout ? 4 : 0;
 445         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 446                 return rscreen->b.has_streamout ? 1 : 0;
 447         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 448         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 449                 return 32*4;
 450
 451         /* Texturing. */
 452         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 453         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 454         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 455                 if (family >= CHIP_CEDAR)
 456                         return 15;
 457                 else
 458                         return 14;
 459         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 460                 return rscreen->b.info.drm_minor >= 9 ?
 461                         (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
 462         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 463                 return 32;
 464
 465         /* Render targets. */
 466         case PIPE_CAP_MAX_RENDER_TARGETS:
 467                 /* XXX some r6xx are buggy and can only do 4 */
 468                 return 8;
 469
 470         case PIPE_CAP_MAX_VIEWPORTS:
 471                 return 1;
 472
 473         /* Timer queries, present when the clock frequency is non zero. */
 474         case PIPE_CAP_QUERY_TIME_ELAPSED:
 475                 return rscreen->b.info.r600_clock_crystal_freq != 0;
 476         case PIPE_CAP_QUERY_TIMESTAMP:
 477                 return rscreen->b.info.drm_minor >= 20 &&
 478                        rscreen->b.info.r600_clock_crystal_freq != 0;
 479
 480         case PIPE_CAP_MIN_TEXEL_OFFSET:
 481                 return -8;
 482
 483         case PIPE_CAP_MAX_TEXEL_OFFSET:
 484                 return 7;
 485
 486         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 487                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 488         case PIPE_CAP_ENDIANNESS:
 489                 return PIPE_ENDIAN_LITTLE;
 490         }
 491         return 0;
 492 }
 493
 494 static float r600_get_paramf(struct pipe_screen* pscreen,
 495                              enum pipe_capf param)
 496 {
 497         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 498         enum radeon_family family = rscreen->b.family;
 499
 500         switch (param) {
 501         case PIPE_CAPF_MAX_LINE_WIDTH:
 502         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 503         case PIPE_CAPF_MAX_POINT_WIDTH:
 504         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 505                 if (family >= CHIP_CEDAR)
 506                         return 16384.0f;
 507                 else
 508                         return 8192.0f;
 509         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 510                 return 16.0f;
 511         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 512                 return 16.0f;
 513         case PIPE_CAPF_GUARD_BAND_LEFT:
 514         case PIPE_CAPF_GUARD_BAND_TOP:
 515         case PIPE_CAPF_GUARD_BAND_RIGHT:
 516         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 517                 return 0.0f;
 518         }
 519         return 0.0f;
 520 }
 521
 522 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 523 {
 524         switch(shader)
 525         {
 526         case PIPE_SHADER_FRAGMENT:
 527         case PIPE_SHADER_VERTEX:
 528         case PIPE_SHADER_COMPUTE:
 529                 break;
 530         case PIPE_SHADER_GEOMETRY:
 531                 /* XXX: support and enable geometry programs */
 532                 return 0;
 533         default:
 534                 /* XXX: support tessellation on Evergreen */
 535                 return 0;
 536         }
 537
 538         switch (param) {
 539         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 540         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 541         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 542         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 543                 return 16384;
 544         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 545                 return 32;
 546         case PIPE_SHADER_CAP_MAX_INPUTS:
 547                 return 32;
 548         case PIPE_SHADER_CAP_MAX_TEMPS:
 549                 return 256; /* Max native temporaries. */
 550         case PIPE_SHADER_CAP_MAX_ADDRS:
 551                 /* XXX Isn't this equal to TEMPS? */
 552                 return 1; /* Max native address registers */
 553         case PIPE_SHADER_CAP_MAX_CONSTS:
 554                 return R600_MAX_CONST_BUFFER_SIZE;
 555         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 556                 return R600_MAX_USER_CONST_BUFFERS;
 557         case PIPE_SHADER_CAP_MAX_PREDS:
 558                 return 0; /* nothing uses this */
 559         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 560                 return 1;
 561         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 562                 return 0;
 563         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 564         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 565         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 566         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 567                 return 1;
 568         case PIPE_SHADER_CAP_SUBROUTINES:
 569                 return 0;
 570         case PIPE_SHADER_CAP_INTEGERS:
 571                 return 1;
 572         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 573         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 574                 return 16;
 575         case PIPE_SHADER_CAP_PREFERRED_IR:
 576                 if (shader == PIPE_SHADER_COMPUTE) {
 577                         return PIPE_SHADER_IR_LLVM;
 578                 } else {
 579                         return PIPE_SHADER_IR_TGSI;
 580                 }
 581         }
 582         return 0;
 583 }
 584
 585 static int r600_get_video_param(struct pipe_screen *screen,
 586                                 enum pipe_video_profile profile,
 587                                 enum pipe_video_entrypoint entrypoint,
 588                                 enum pipe_video_cap param)
 589 {
 590         switch (param) {
 591         case PIPE_VIDEO_CAP_SUPPORTED:
 592                 return vl_profile_supported(screen, profile, entrypoint);
 593         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 594                 return 1;
 595         case PIPE_VIDEO_CAP_MAX_WIDTH:
 596         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 597                 return vl_video_buffer_max_size(screen);
 598         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 599                 return PIPE_FORMAT_NV12;
 600         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 601                 return false;
 602         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 603                 return false;
 604         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 605                 return true;
 606         case PIPE_VIDEO_CAP_MAX_LEVEL:
 607                 return vl_level_supported(screen, profile);
 608         default:
 609                 return 0;
 610         }
 611 }
 612
 613 const char * r600_llvm_gpu_string(enum radeon_family family)
 614 {
 615         const char * gpu_family;
 616
 617         switch (family) {
 618         case CHIP_R600:
 619         case CHIP_RV630:
 620         case CHIP_RV635:
 621         case CHIP_RV670:
 622                 gpu_family = "r600";
 623                 break;
 624         case CHIP_RV610:
 625         case CHIP_RV620:
 626         case CHIP_RS780:
 627         case CHIP_RS880:
 628                 gpu_family = "rs880";
 629                 break;
 630         case CHIP_RV710:
 631                 gpu_family = "rv710";
 632                 break;
 633         case CHIP_RV730:
 634                 gpu_family = "rv730";
 635                 break;
 636         case CHIP_RV740:
 637         case CHIP_RV770:
 638                 gpu_family = "rv770";
 639                 break;
 640         case CHIP_PALM:
 641         case CHIP_CEDAR:
 642                 gpu_family = "cedar";
 643                 break;
 644         case CHIP_SUMO:
 645         case CHIP_SUMO2:
 646                 gpu_family = "sumo";
 647                 break;
 648         case CHIP_REDWOOD:
 649                 gpu_family = "redwood";
 650                 break;
 651         case CHIP_JUNIPER:
 652                 gpu_family = "juniper";
 653                 break;
 654         case CHIP_HEMLOCK:
 655         case CHIP_CYPRESS:
 656                 gpu_family = "cypress";
 657                 break;
 658         case CHIP_BARTS:
 659                 gpu_family = "barts";
 660                 break;
 661         case CHIP_TURKS:
 662                 gpu_family = "turks";
 663                 break;
 664         case CHIP_CAICOS:
 665                 gpu_family = "caicos";
 666                 break;
 667         case CHIP_CAYMAN:
 668         case CHIP_ARUBA:
 669                 gpu_family = "cayman";
 670                 break;
 671         default:
 672                 gpu_family = "";
 673                 fprintf(stderr, "Chip not supported by r600 llvm "
 674                         "backend, please file a bug at " PACKAGE_BUGREPORT "\n");
 675                 break;
 676         }
 677         return gpu_family;
 678 }
 679
 680
 681 static int r600_get_compute_param(struct pipe_screen *screen,
 682         enum pipe_compute_cap param,
 683         void *ret)
 684 {
 685         struct r600_screen *rscreen = (struct r600_screen *)screen;
 686         //TODO: select these params by asic
 687         switch (param) {
 688         case PIPE_COMPUTE_CAP_IR_TARGET: {
 689                 const char *gpu = r600_llvm_gpu_string(rscreen->b.family);
 690                 if (ret) {
 691                         sprintf(ret, "%s-r600--", gpu);
 692                 }
 693                 return (8 + strlen(gpu)) * sizeof(char);
 694         }
 695         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 696                 if (ret) {
 697                         uint64_t * grid_dimension = ret;
 698                         grid_dimension[0] = 3;
 699                 }
 700                 return 1 * sizeof(uint64_t);
 701
 702         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 703                 if (ret) {
 704                         uint64_t * grid_size = ret;
 705                         grid_size[0] = 65535;
 706                         grid_size[1] = 65535;
 707                         grid_size[2] = 1;
 708                 }
 709                 return 3 * sizeof(uint64_t) ;
 710
 711         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 712                 if (ret) {
 713                         uint64_t * block_size = ret;
 714                         block_size[0] = 256;
 715                         block_size[1] = 256;
 716                         block_size[2] = 256;
 717                 }
 718                 return 3 * sizeof(uint64_t);
 719
 720         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 721                 if (ret) {
 722                         uint64_t * max_threads_per_block = ret;
 723                         *max_threads_per_block = 256;
 724                 }
 725                 return sizeof(uint64_t);
 726
 727         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 728                 if (ret) {
 729                         uint64_t * max_global_size = ret;
 730                         /* XXX: This is what the proprietary driver reports, we
 731                          * may want to use a different value. */
 732                         *max_global_size = 201326592;
 733                 }
 734                 return sizeof(uint64_t);
 735
 736         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 737                 if (ret) {
 738                         uint64_t * max_input_size = ret;
 739                         *max_input_size = 1024;
 740                 }
 741                 return sizeof(uint64_t);
 742
 743         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 744                 if (ret) {
 745                         uint64_t * max_local_size = ret;
 746                         /* XXX: This is what the proprietary driver reports, we
 747                          * may want to use a different value. */
 748                         *max_local_size = 32768;
 749                 }
 750                 return sizeof(uint64_t);
 751
 752         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 753                 if (ret) {
 754                         uint64_t max_global_size;
 755                         uint64_t * max_mem_alloc_size = ret;
 756                         r600_get_compute_param(screen,
 757                                         PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE,
 758                                         &max_global_size);
 759                         /* OpenCL requres this value be at least
 760                          * max(MAX_GLOBAL_SIZE / 4, 128 * 1024 *1024)
 761                          * I'm really not sure what value to report here, but
 762                          * MAX_GLOBAL_SIZE / 4 seems resonable.
 763                          */
 764                         *max_mem_alloc_size = max_global_size / 4;
 765                 }
 766                 return sizeof(uint64_t);
 767
 768         default:
 769                 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
 770                 return 0;
 771         }
 772 }
 773
 774 static void r600_destroy_screen(struct pipe_screen* pscreen)
 775 {
 776         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 777
 778         if (rscreen == NULL)
 779                 return;
 780
 781         if (!radeon_winsys_unref(rscreen->b.ws))
 782                 return;
 783
 784         r600_common_screen_cleanup(&rscreen->b);
 785
 786         if (rscreen->global_pool) {
 787                 compute_memory_pool_delete(rscreen->global_pool);
 788         }
 789
 790         if (rscreen->trace_bo) {
 791                 rscreen->b.ws->buffer_unmap(rscreen->trace_bo->cs_buf);
 792                 pipe_resource_reference((struct pipe_resource**)&rscreen->trace_bo, NULL);
 793         }
 794
 795         rscreen->b.ws->destroy(rscreen->b.ws);
 796         FREE(rscreen);
 797 }
 798
 799 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
 800 {
 801         struct r600_screen *rscreen = (struct r600_screen*)screen;
 802
 803         return 1000000 * rscreen->b.ws->query_value(rscreen->b.ws, RADEON_TIMESTAMP) /
 804                         rscreen->b.info.r600_clock_crystal_freq;
 805 }
 806
 807 static int r600_get_driver_query_info(struct pipe_screen *screen,
 808                                       unsigned index,
 809                                       struct pipe_driver_query_info *info)
 810 {
 811         struct r600_screen *rscreen = (struct r600_screen*)screen;
 812         struct pipe_driver_query_info list[] = {
 813                 {"draw-calls", R600_QUERY_DRAW_CALLS, 0},
 814                 {"requested-VRAM", R600_QUERY_REQUESTED_VRAM, rscreen->b.info.vram_size, TRUE},
 815                 {"requested-GTT", R600_QUERY_REQUESTED_GTT, rscreen->b.info.gart_size, TRUE},
 816                 {"buffer-wait-time", R600_QUERY_BUFFER_WAIT_TIME, 0, FALSE}
 817         };
 818
 819         if (!info)
 820                 return Elements(list);
 821
 822         if (index >= Elements(list))
 823                 return 0;
 824
 825         *info = list[index];
 826         return 1;
 827 }
 828
 829 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 830 {
 831         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 832
 833         if (rscreen == NULL) {
 834                 return NULL;
 835         }
 836
 837         ws->query_info(ws, &rscreen->b.info);
 838
 839         /* Set functions first. */
 840         rscreen->b.b.context_create = r600_create_context;
 841         rscreen->b.b.destroy = r600_destroy_screen;
 842         rscreen->b.b.get_name = r600_get_name;
 843         rscreen->b.b.get_vendor = r600_get_vendor;
 844         rscreen->b.b.get_param = r600_get_param;
 845         rscreen->b.b.get_shader_param = r600_get_shader_param;
 846         rscreen->b.b.get_paramf = r600_get_paramf;
 847         rscreen->b.b.get_compute_param = r600_get_compute_param;
 848         rscreen->b.b.get_timestamp = r600_get_timestamp;
 849         if (rscreen->b.info.chip_class >= EVERGREEN) {
 850                 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
 851         } else {
 852                 rscreen->b.b.is_format_supported = r600_is_format_supported;
 853         }
 854         rscreen->b.b.get_driver_query_info = r600_get_driver_query_info;
 855         if (rscreen->b.info.has_uvd) {
 856                 rscreen->b.b.get_video_param = ruvd_get_video_param;
 857                 rscreen->b.b.is_video_format_supported = ruvd_is_format_supported;
 858         } else {
 859                 rscreen->b.b.get_video_param = r600_get_video_param;
 860                 rscreen->b.b.is_video_format_supported = vl_video_buffer_is_format_supported;
 861         }
 862         r600_init_screen_resource_functions(&rscreen->b.b);
 863
 864         if (!r600_common_screen_init(&rscreen->b, ws)) {
 865                 FREE(rscreen);
 866                 return NULL;
 867         }
 868
 869         rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
 870         if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
 871                 rscreen->b.debug_flags |= DBG_COMPUTE;
 872         if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
 873                 rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 874         if (!debug_get_bool_option("R600_HYPERZ", TRUE))
 875                 rscreen->b.debug_flags |= DBG_NO_HYPERZ;
 876         if (!debug_get_bool_option("R600_LLVM", TRUE))
 877                 rscreen->b.debug_flags |= DBG_NO_LLVM;
 878
 879         if (rscreen->b.family == CHIP_UNKNOWN) {
 880                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
 881                 FREE(rscreen);
 882                 return NULL;
 883         }
 884
 885         /* Figure out streamout kernel support. */
 886         switch (rscreen->b.chip_class) {
 887         case R600:
 888                 if (rscreen->b.family < CHIP_RS780) {
 889                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 890                 } else {
 891                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
 892                 }
 893                 break;
 894         case R700:
 895                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
 896                 break;
 897         case EVERGREEN:
 898         case CAYMAN:
 899                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 900                 break;
 901         default:
 902                 rscreen->b.has_streamout = FALSE;
 903                 break;
 904         }
 905
 906         /* MSAA support. */
 907         switch (rscreen->b.chip_class) {
 908         case R600:
 909         case R700:
 910                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
 911                 rscreen->has_compressed_msaa_texturing = false;
 912                 break;
 913         case EVERGREEN:
 914                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 915                 rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
 916                 break;
 917         case CAYMAN:
 918                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 919                 rscreen->has_compressed_msaa_texturing = true;
 920                 break;
 921         default:
 922                 rscreen->has_msaa = FALSE;
 923                 rscreen->has_compressed_msaa_texturing = false;
 924         }
 925
 926         rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
 927                               !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
 928
 929         rscreen->global_pool = compute_memory_pool_new(rscreen);
 930
 931         rscreen->cs_count = 0;
 932         if (rscreen->b.info.drm_minor >= 28 && (rscreen->b.debug_flags & DBG_TRACE_CS)) {
 933                 rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b.b,
 934                                                                                 PIPE_BIND_CUSTOM,
 935                                                                                 PIPE_USAGE_STAGING,
 936                                                                                 4096);
 937                 if (rscreen->trace_bo) {
 938                         rscreen->trace_ptr = rscreen->b.ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
 939                                                                         PIPE_TRANSFER_UNSYNCHRONIZED);
 940                 }
 941         }
 942
 943         /* Create the auxiliary context. This must be done last. */
 944         rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL);
 945
 946 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
 947         struct pipe_resource templ = {};
 948
 949         templ.width0 = 4;
 950         templ.height0 = 2048;
 951         templ.depth0 = 1;
 952         templ.array_size = 1;
 953         templ.target = PIPE_TEXTURE_2D;
 954         templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
 955         templ.usage = PIPE_USAGE_STATIC;
 956
 957         struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
 958         unsigned char *map = ws->buffer_map(res->cs_buf, NULL, PIPE_TRANSFER_WRITE);
 959
 960         memset(map, 0, 256);
 961
 962         r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
 963         r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
 964         r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
 965         r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
 966         r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
 967
 968         ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
 969
 970         int i;
 971         for (i = 0; i < 256; i++) {
 972                 printf("%02X", map[i]);
 973                 if (i % 16 == 15)
 974                         printf("\n");
 975         }
 976 #endif
 977
 978         return &rscreen->b.b;
 979 }