[g3dvl] move video buffer creation out of video context
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25 #include <pipe/p_defines.h>
26 #include <pipe/p_state.h>
27 #include <pipe/p_context.h>
28 #include <tgsi/tgsi_scan.h>
29 #include <tgsi/tgsi_parse.h>
30 #include <tgsi/tgsi_util.h>
31 #include <util/u_blitter.h>
32 #include <util/u_double_list.h>
33 #include "util/u_format.h"
34 #include <util/u_format_s3tc.h>
35 #include <util/u_transfer.h>
36 #include <util/u_surface.h>
37 #include <util/u_pack_color.h>
38 #include <util/u_memory.h>
39 #include <util/u_inlines.h>
40 #include "util/u_upload_mgr.h"
41 #include <vl/vl_context.h>
42 #include <vl/vl_video_buffer.h>
43 #include "os/os_time.h"
44 #include <pipebuffer/pb_buffer.h>
45 #include "r600.h"
46 #include "r600d.h"
47 #include "r600_resource.h"
48 #include "r600_shader.h"
49 #include "r600_pipe.h"
50 #include "r600_state_inlines.h"
51
52 /*
53 * pipe_context
54 */
55 static struct r600_fence *r600_create_fence(struct r600_pipe_context *ctx)
56 {
57 struct r600_fence *fence = NULL;
58
59 if (!ctx->fences.bo) {
60 /* Create the shared buffer object */
61 ctx->fences.bo = r600_bo(ctx->radeon, 4096, 0, 0, 0);
62 if (!ctx->fences.bo) {
63 R600_ERR("r600: failed to create bo for fence objects\n");
64 return NULL;
65 }
66 ctx->fences.data = r600_bo_map(ctx->radeon, ctx->fences.bo, PB_USAGE_UNSYNCHRONIZED, NULL);
67 }
68
69 if (!LIST_IS_EMPTY(&ctx->fences.pool)) {
70 struct r600_fence *entry;
71
72 /* Try to find a freed fence that has been signalled */
73 LIST_FOR_EACH_ENTRY(entry, &ctx->fences.pool, head) {
74 if (ctx->fences.data[entry->index] != 0) {
75 LIST_DELINIT(&entry->head);
76 fence = entry;
77 break;
78 }
79 }
80 }
81
82 if (!fence) {
83 /* Allocate a new fence */
84 struct r600_fence_block *block;
85 unsigned index;
86
87 if ((ctx->fences.next_index + 1) >= 1024) {
88 R600_ERR("r600: too many concurrent fences\n");
89 return NULL;
90 }
91
92 index = ctx->fences.next_index++;
93
94 if (!(index % FENCE_BLOCK_SIZE)) {
95 /* Allocate a new block */
96 block = CALLOC_STRUCT(r600_fence_block);
97 if (block == NULL)
98 return NULL;
99
100 LIST_ADD(&block->head, &ctx->fences.blocks);
101 } else {
102 block = LIST_ENTRY(struct r600_fence_block, ctx->fences.blocks.next, head);
103 }
104
105 fence = &block->fences[index % FENCE_BLOCK_SIZE];
106 fence->ctx = ctx;
107 fence->index = index;
108 }
109
110 pipe_reference_init(&fence->reference, 1);
111
112 ctx->fences.data[fence->index] = 0;
113 r600_context_emit_fence(&ctx->ctx, ctx->fences.bo, fence->index, 1);
114 return fence;
115 }
116
117 static void r600_flush(struct pipe_context *ctx,
118 struct pipe_fence_handle **fence)
119 {
120 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
121 struct r600_fence **rfence = (struct r600_fence**)fence;
122
123 #if 0
124 static int dc = 0;
125 char dname[256];
126 #endif
127
128 if (rfence)
129 *rfence = r600_create_fence(rctx);
130
131 #if 0
132 sprintf(dname, "gallium-%08d.bof", dc);
133 if (dc < 20) {
134 r600_context_dump_bof(&rctx->ctx, dname);
135 R600_ERR("dumped %s\n", dname);
136 }
137 dc++;
138 #endif
139 r600_context_flush(&rctx->ctx);
140 }
141
142 static void r600_update_num_contexts(struct r600_screen *rscreen, int diff)
143 {
144 pipe_mutex_lock(rscreen->mutex_num_contexts);
145 if (diff > 0) {
146 rscreen->num_contexts++;
147
148 if (rscreen->num_contexts > 1)
149 util_slab_set_thread_safety(&rscreen->pool_buffers,
150 UTIL_SLAB_MULTITHREADED);
151 } else {
152 rscreen->num_contexts--;
153
154 if (rscreen->num_contexts <= 1)
155 util_slab_set_thread_safety(&rscreen->pool_buffers,
156 UTIL_SLAB_SINGLETHREADED);
157 }
158 pipe_mutex_unlock(rscreen->mutex_num_contexts);
159 }
160
161 static void r600_destroy_context(struct pipe_context *context)
162 {
163 struct r600_pipe_context *rctx = (struct r600_pipe_context *)context;
164
165 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
166 util_unreference_framebuffer_state(&rctx->framebuffer);
167
168 r600_context_fini(&rctx->ctx);
169
170 util_blitter_destroy(rctx->blitter);
171
172 for (int i = 0; i < R600_PIPE_NSTATES; i++) {
173 free(rctx->states[i]);
174 }
175
176 u_vbuf_mgr_destroy(rctx->vbuf_mgr);
177 util_slab_destroy(&rctx->pool_transfers);
178
179 if (rctx->fences.bo) {
180 struct r600_fence_block *entry, *tmp;
181
182 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rctx->fences.blocks, head) {
183 LIST_DEL(&entry->head);
184 FREE(entry);
185 }
186
187 r600_bo_unmap(rctx->radeon, rctx->fences.bo);
188 r600_bo_reference(rctx->radeon, &rctx->fences.bo, NULL);
189 }
190
191 r600_update_num_contexts(rctx->screen, -1);
192
193 FREE(rctx);
194 }
195
196 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
197 {
198 struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context);
199 struct r600_screen* rscreen = (struct r600_screen *)screen;
200 enum chip_class class;
201
202 if (rctx == NULL)
203 return NULL;
204
205 r600_update_num_contexts(rscreen, 1);
206
207 rctx->context.winsys = rscreen->screen.winsys;
208 rctx->context.screen = screen;
209 rctx->context.priv = priv;
210 rctx->context.destroy = r600_destroy_context;
211 rctx->context.flush = r600_flush;
212
213 /* Easy accessing of screen/winsys. */
214 rctx->screen = rscreen;
215 rctx->radeon = rscreen->radeon;
216 rctx->family = r600_get_family(rctx->radeon);
217
218 rctx->fences.bo = NULL;
219 rctx->fences.data = NULL;
220 rctx->fences.next_index = 0;
221 LIST_INITHEAD(&rctx->fences.pool);
222 LIST_INITHEAD(&rctx->fences.blocks);
223
224 r600_init_blit_functions(rctx);
225 r600_init_query_functions(rctx);
226 r600_init_context_resource_functions(rctx);
227 r600_init_surface_functions(rctx);
228 rctx->context.draw_vbo = r600_draw_vbo;
229 rctx->context.create_video_buffer = vl_video_buffer_create;
230
231 switch (r600_get_family(rctx->radeon)) {
232 case CHIP_R600:
233 case CHIP_RV610:
234 case CHIP_RV630:
235 case CHIP_RV670:
236 case CHIP_RV620:
237 case CHIP_RV635:
238 case CHIP_RS780:
239 case CHIP_RS880:
240 case CHIP_RV770:
241 case CHIP_RV730:
242 case CHIP_RV710:
243 case CHIP_RV740:
244 r600_init_state_functions(rctx);
245 if (r600_context_init(&rctx->ctx, rctx->radeon)) {
246 r600_destroy_context(&rctx->context);
247 return NULL;
248 }
249 r600_init_config(rctx);
250 break;
251 case CHIP_CEDAR:
252 case CHIP_REDWOOD:
253 case CHIP_JUNIPER:
254 case CHIP_CYPRESS:
255 case CHIP_HEMLOCK:
256 case CHIP_PALM:
257 case CHIP_SUMO:
258 case CHIP_SUMO2:
259 case CHIP_BARTS:
260 case CHIP_TURKS:
261 case CHIP_CAICOS:
262 case CHIP_CAYMAN:
263 evergreen_init_state_functions(rctx);
264 if (evergreen_context_init(&rctx->ctx, rctx->radeon)) {
265 r600_destroy_context(&rctx->context);
266 return NULL;
267 }
268 evergreen_init_config(rctx);
269 break;
270 default:
271 R600_ERR("unsupported family %d\n", r600_get_family(rctx->radeon));
272 r600_destroy_context(&rctx->context);
273 return NULL;
274 }
275
276 util_slab_create(&rctx->pool_transfers,
277 sizeof(struct pipe_transfer), 64,
278 UTIL_SLAB_SINGLETHREADED);
279
280 rctx->vbuf_mgr = u_vbuf_mgr_create(&rctx->context, 1024 * 1024, 256,
281 PIPE_BIND_VERTEX_BUFFER |
282 PIPE_BIND_INDEX_BUFFER |
283 PIPE_BIND_CONSTANT_BUFFER,
284 U_VERTEX_FETCH_DWORD_ALIGNED);
285 if (!rctx->vbuf_mgr) {
286 r600_destroy_context(&rctx->context);
287 return NULL;
288 }
289
290 rctx->blitter = util_blitter_create(&rctx->context);
291 if (rctx->blitter == NULL) {
292 r600_destroy_context(&rctx->context);
293 return NULL;
294 }
295
296 class = r600_get_family_class(rctx->radeon);
297 if (class == R600 || class == R700)
298 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
299 else
300 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
301
302 return &rctx->context;
303 }
304
305 static struct pipe_video_context *
306 r600_video_create(struct pipe_screen *screen, struct pipe_context *pipe)
307 {
308 assert(screen && pipe);
309
310 return vl_create_context(pipe);
311 }
312
313 /*
314 * pipe_screen
315 */
316 static const char* r600_get_vendor(struct pipe_screen* pscreen)
317 {
318 return "X.Org";
319 }
320
321 static const char *r600_get_family_name(enum radeon_family family)
322 {
323 switch(family) {
324 case CHIP_R600: return "AMD R600";
325 case CHIP_RV610: return "AMD RV610";
326 case CHIP_RV630: return "AMD RV630";
327 case CHIP_RV670: return "AMD RV670";
328 case CHIP_RV620: return "AMD RV620";
329 case CHIP_RV635: return "AMD RV635";
330 case CHIP_RS780: return "AMD RS780";
331 case CHIP_RS880: return "AMD RS880";
332 case CHIP_RV770: return "AMD RV770";
333 case CHIP_RV730: return "AMD RV730";
334 case CHIP_RV710: return "AMD RV710";
335 case CHIP_RV740: return "AMD RV740";
336 case CHIP_CEDAR: return "AMD CEDAR";
337 case CHIP_REDWOOD: return "AMD REDWOOD";
338 case CHIP_JUNIPER: return "AMD JUNIPER";
339 case CHIP_CYPRESS: return "AMD CYPRESS";
340 case CHIP_HEMLOCK: return "AMD HEMLOCK";
341 case CHIP_PALM: return "AMD PALM";
342 case CHIP_SUMO: return "AMD SUMO";
343 case CHIP_SUMO2: return "AMD SUMO2";
344 case CHIP_BARTS: return "AMD BARTS";
345 case CHIP_TURKS: return "AMD TURKS";
346 case CHIP_CAICOS: return "AMD CAICOS";
347 case CHIP_CAYMAN: return "AMD CAYMAN";
348 default: return "AMD unknown";
349 }
350 }
351
352 static const char* r600_get_name(struct pipe_screen* pscreen)
353 {
354 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
355 enum radeon_family family = r600_get_family(rscreen->radeon);
356
357 return r600_get_family_name(family);
358 }
359
360 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
361 {
362 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
363 enum radeon_family family = r600_get_family(rscreen->radeon);
364
365 switch (param) {
366 /* Supported features (boolean caps). */
367 case PIPE_CAP_NPOT_TEXTURES:
368 case PIPE_CAP_TWO_SIDED_STENCIL:
369 case PIPE_CAP_GLSL:
370 case PIPE_CAP_DUAL_SOURCE_BLEND:
371 case PIPE_CAP_ANISOTROPIC_FILTER:
372 case PIPE_CAP_POINT_SPRITE:
373 case PIPE_CAP_OCCLUSION_QUERY:
374 case PIPE_CAP_TEXTURE_SHADOW_MAP:
375 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
376 case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
377 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
378 case PIPE_CAP_TEXTURE_SWIZZLE:
379 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
380 case PIPE_CAP_DEPTH_CLAMP:
381 case PIPE_CAP_SHADER_STENCIL_EXPORT:
382 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
383 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
384 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
385 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
386 case PIPE_CAP_SM3:
387 case PIPE_CAP_SEAMLESS_CUBE_MAP:
388 case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
389 return 1;
390
391 /* Supported except the original R600. */
392 case PIPE_CAP_INDEP_BLEND_ENABLE:
393 case PIPE_CAP_INDEP_BLEND_FUNC:
394 /* R600 doesn't support per-MRT blends */
395 return family == CHIP_R600 ? 0 : 1;
396
397 /* Supported on Evergreen. */
398 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
399 return family >= CHIP_CEDAR ? 1 : 0;
400
401 /* Unsupported features. */
402 case PIPE_CAP_STREAM_OUTPUT:
403 case PIPE_CAP_PRIMITIVE_RESTART:
404 case PIPE_CAP_TGSI_INSTANCEID:
405 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
406 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
407 return 0;
408
409 case PIPE_CAP_ARRAY_TEXTURES:
410 /* fix once the CS checker upstream is fixed */
411 return debug_get_bool_option("R600_ARRAY_TEXTURE", FALSE);
412
413 /* Texturing. */
414 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
415 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
416 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
417 if (family >= CHIP_CEDAR)
418 return 15;
419 else
420 return 14;
421 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
422 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
423 return 16;
424 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
425 return 32;
426
427 /* Render targets. */
428 case PIPE_CAP_MAX_RENDER_TARGETS:
429 /* FIXME some r6xx are buggy and can only do 4 */
430 return 8;
431
432 /* Timer queries, present when the clock frequency is non zero. */
433 case PIPE_CAP_TIMER_QUERY:
434 return r600_get_clock_crystal_freq(rscreen->radeon) != 0;
435
436 default:
437 R600_ERR("r600: unknown param %d\n", param);
438 return 0;
439 }
440 }
441
442 static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
443 {
444 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
445 enum radeon_family family = r600_get_family(rscreen->radeon);
446
447 switch (param) {
448 case PIPE_CAP_MAX_LINE_WIDTH:
449 case PIPE_CAP_MAX_LINE_WIDTH_AA:
450 case PIPE_CAP_MAX_POINT_WIDTH:
451 case PIPE_CAP_MAX_POINT_WIDTH_AA:
452 if (family >= CHIP_CEDAR)
453 return 16384.0f;
454 else
455 return 8192.0f;
456 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
457 return 16.0f;
458 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
459 return 16.0f;
460 default:
461 R600_ERR("r600: unsupported paramf %d\n", param);
462 return 0.0f;
463 }
464 }
465
466 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
467 {
468 switch(shader)
469 {
470 case PIPE_SHADER_FRAGMENT:
471 case PIPE_SHADER_VERTEX:
472 break;
473 case PIPE_SHADER_GEOMETRY:
474 /* TODO: support and enable geometry programs */
475 return 0;
476 default:
477 /* TODO: support tessellation on Evergreen */
478 return 0;
479 }
480
481 /* TODO: all these should be fixed, since r600 surely supports much more! */
482 switch (param) {
483 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
484 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
485 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
486 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
487 return 16384;
488 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
489 return 8; /* FIXME */
490 case PIPE_SHADER_CAP_MAX_INPUTS:
491 if(shader == PIPE_SHADER_FRAGMENT)
492 return 34;
493 else
494 return 32;
495 case PIPE_SHADER_CAP_MAX_TEMPS:
496 return 256; /* Max native temporaries. */
497 case PIPE_SHADER_CAP_MAX_ADDRS:
498 /* FIXME Isn't this equal to TEMPS? */
499 return 1; /* Max native address registers */
500 case PIPE_SHADER_CAP_MAX_CONSTS:
501 return R600_MAX_CONST_BUFFER_SIZE;
502 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
503 return R600_MAX_CONST_BUFFERS;
504 case PIPE_SHADER_CAP_MAX_PREDS:
505 return 0; /* FIXME */
506 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
507 return 1;
508 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
509 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
510 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
511 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
512 return 1;
513 case PIPE_SHADER_CAP_SUBROUTINES:
514 return 0;
515 default:
516 return 0;
517 }
518 }
519
520 static int r600_get_video_param(struct pipe_screen *screen,
521 enum pipe_video_profile profile,
522 enum pipe_video_cap param)
523 {
524 switch (param) {
525 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
526 return 1;
527 default:
528 return 0;
529 }
530 }
531
532 static boolean r600_is_format_supported(struct pipe_screen* screen,
533 enum pipe_format format,
534 enum pipe_texture_target target,
535 unsigned sample_count,
536 unsigned usage)
537 {
538 unsigned retval = 0;
539 if (target >= PIPE_MAX_TEXTURE_TYPES) {
540 R600_ERR("r600: unsupported texture type %d\n", target);
541 return FALSE;
542 }
543
544 if (!util_format_is_supported(format, usage))
545 return FALSE;
546
547 /* Multisample */
548 if (sample_count > 1)
549 return FALSE;
550
551 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
552 r600_is_sampler_format_supported(screen, format)) {
553 retval |= PIPE_BIND_SAMPLER_VIEW;
554 }
555
556 if ((usage & (PIPE_BIND_RENDER_TARGET |
557 PIPE_BIND_DISPLAY_TARGET |
558 PIPE_BIND_SCANOUT |
559 PIPE_BIND_SHARED)) &&
560 r600_is_colorbuffer_format_supported(format)) {
561 retval |= usage &
562 (PIPE_BIND_RENDER_TARGET |
563 PIPE_BIND_DISPLAY_TARGET |
564 PIPE_BIND_SCANOUT |
565 PIPE_BIND_SHARED);
566 }
567
568 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
569 r600_is_zs_format_supported(format)) {
570 retval |= PIPE_BIND_DEPTH_STENCIL;
571 }
572
573 if (usage & PIPE_BIND_VERTEX_BUFFER) {
574 struct r600_screen *rscreen = (struct r600_screen *)screen;
575 enum radeon_family family = r600_get_family(rscreen->radeon);
576
577 if (r600_is_vertex_format_supported(format, family)) {
578 retval |= PIPE_BIND_VERTEX_BUFFER;
579 }
580 }
581
582 if (usage & PIPE_BIND_TRANSFER_READ)
583 retval |= PIPE_BIND_TRANSFER_READ;
584 if (usage & PIPE_BIND_TRANSFER_WRITE)
585 retval |= PIPE_BIND_TRANSFER_WRITE;
586
587 return retval == usage;
588 }
589
590 static void r600_destroy_screen(struct pipe_screen* pscreen)
591 {
592 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
593
594 if (rscreen == NULL)
595 return;
596
597 radeon_decref(rscreen->radeon);
598
599 util_slab_destroy(&rscreen->pool_buffers);
600 pipe_mutex_destroy(rscreen->mutex_num_contexts);
601 FREE(rscreen);
602 }
603
604 static void r600_fence_reference(struct pipe_screen *pscreen,
605 struct pipe_fence_handle **ptr,
606 struct pipe_fence_handle *fence)
607 {
608 struct r600_fence **oldf = (struct r600_fence**)ptr;
609 struct r600_fence *newf = (struct r600_fence*)fence;
610
611 if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
612 struct r600_pipe_context *ctx = (*oldf)->ctx;
613 LIST_ADDTAIL(&(*oldf)->head, &ctx->fences.pool);
614 }
615
616 *ptr = fence;
617 }
618
619 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
620 struct pipe_fence_handle *fence)
621 {
622 struct r600_fence *rfence = (struct r600_fence*)fence;
623 struct r600_pipe_context *ctx = rfence->ctx;
624
625 return ctx->fences.data[rfence->index];
626 }
627
628 static boolean r600_fence_finish(struct pipe_screen *pscreen,
629 struct pipe_fence_handle *fence,
630 uint64_t timeout)
631 {
632 struct r600_fence *rfence = (struct r600_fence*)fence;
633 struct r600_pipe_context *ctx = rfence->ctx;
634 int64_t start_time = 0;
635 unsigned spins = 0;
636
637 if (timeout != PIPE_TIMEOUT_INFINITE) {
638 start_time = os_time_get();
639
640 /* Convert to microseconds. */
641 timeout /= 1000;
642 }
643
644 while (ctx->fences.data[rfence->index] == 0) {
645 if (++spins % 256)
646 continue;
647 #ifdef PIPE_OS_UNIX
648 sched_yield();
649 #else
650 os_time_sleep(10);
651 #endif
652 if (timeout != PIPE_TIMEOUT_INFINITE &&
653 os_time_get() - start_time >= timeout) {
654 return FALSE;
655 }
656 }
657
658 return TRUE;
659 }
660
661 struct pipe_screen *r600_screen_create(struct radeon *radeon)
662 {
663 struct r600_screen *rscreen;
664
665 rscreen = CALLOC_STRUCT(r600_screen);
666 if (rscreen == NULL) {
667 return NULL;
668 }
669
670 rscreen->radeon = radeon;
671 rscreen->screen.winsys = (struct pipe_winsys*)radeon;
672 rscreen->screen.destroy = r600_destroy_screen;
673 rscreen->screen.get_name = r600_get_name;
674 rscreen->screen.get_vendor = r600_get_vendor;
675 rscreen->screen.get_param = r600_get_param;
676 rscreen->screen.get_shader_param = r600_get_shader_param;
677 rscreen->screen.get_paramf = r600_get_paramf;
678 rscreen->screen.get_video_param = r600_get_video_param;
679 rscreen->screen.is_format_supported = r600_is_format_supported;
680 rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
681 rscreen->screen.context_create = r600_create_context;
682 rscreen->screen.video_context_create = r600_video_create;
683 rscreen->screen.fence_reference = r600_fence_reference;
684 rscreen->screen.fence_signalled = r600_fence_signalled;
685 rscreen->screen.fence_finish = r600_fence_finish;
686 r600_init_screen_resource_functions(&rscreen->screen);
687
688 rscreen->tiling_info = r600_get_tiling_info(radeon);
689 util_format_s3tc_init();
690
691 util_slab_create(&rscreen->pool_buffers,
692 sizeof(struct r600_resource_buffer), 64,
693 UTIL_SLAB_SINGLETHREADED);
694
695 pipe_mutex_init(rscreen->mutex_num_contexts);
696
697 return &rscreen->screen;
698 }