src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "pipe/p_context.h"
  28 #include "tgsi/tgsi_scan.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "tgsi/tgsi_util.h"
  31 #include "util/u_blitter.h"
  32 #include "util/u_double_list.h"
  33 #include "util/u_format.h"
  34 #include "util/u_format_s3tc.h"
  35 #include "util/u_transfer.h"
  36 #include "util/u_surface.h"
  37 #include "util/u_pack_color.h"
  38 #include "util/u_memory.h"
  39 #include "util/u_inlines.h"
  40 #include "util/u_upload_mgr.h"
  41 #include "vl/vl_decoder.h"
  42 #include "vl/vl_video_buffer.h"
  43 #include "os/os_time.h"
  44 #include "pipebuffer/pb_buffer.h"
  45 #include "r600.h"
  46 #include "r600d.h"
  47 #include "r600_resource.h"
  48 #include "r600_shader.h"
  49 #include "r600_pipe.h"
  50
  51 /*
  52  * pipe_context
  53  */
  54 static struct r600_fence *r600_create_fence(struct r600_pipe_context *ctx)
  55 {
  56         struct r600_fence *fence = NULL;
  57
  58         if (!ctx->fences.bo) {
  59                 /* Create the shared buffer object */
  60                 ctx->fences.bo = (struct r600_resource*)
  61                         pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM,
  62                                            PIPE_USAGE_STAGING, 4096);
  63                 if (!ctx->fences.bo) {
  64                         R600_ERR("r600: failed to create bo for fence objects\n");
  65                         return NULL;
  66                 }
  67                 ctx->fences.data = ctx->ws->buffer_map(ctx->fences.bo->buf, ctx->ctx.cs,
  68                                                        PIPE_TRANSFER_WRITE);
  69         }
  70
  71         if (!LIST_IS_EMPTY(&ctx->fences.pool)) {
  72                 struct r600_fence *entry;
  73
  74                 /* Try to find a freed fence that has been signalled */
  75                 LIST_FOR_EACH_ENTRY(entry, &ctx->fences.pool, head) {
  76                         if (ctx->fences.data[entry->index] != 0) {
  77                                 LIST_DELINIT(&entry->head);
  78                                 fence = entry;
  79                                 break;
  80                         }
  81                 }
  82         }
  83
  84         if (!fence) {
  85                 /* Allocate a new fence */
  86                 struct r600_fence_block *block;
  87                 unsigned index;
  88
  89                 if ((ctx->fences.next_index + 1) >= 1024) {
  90                         R600_ERR("r600: too many concurrent fences\n");
  91                         return NULL;
  92                 }
  93
  94                 index = ctx->fences.next_index++;
  95
  96                 if (!(index % FENCE_BLOCK_SIZE)) {
  97                         /* Allocate a new block */
  98                         block = CALLOC_STRUCT(r600_fence_block);
  99                         if (block == NULL)
 100                                 return NULL;
 101
 102                         LIST_ADD(&block->head, &ctx->fences.blocks);
 103                 } else {
 104                         block = LIST_ENTRY(struct r600_fence_block, ctx->fences.blocks.next, head);
 105                 }
 106
 107                 fence = &block->fences[index % FENCE_BLOCK_SIZE];
 108                 fence->ctx = ctx;
 109                 fence->index = index;
 110         }
 111
 112         pipe_reference_init(&fence->reference, 1);
 113
 114         ctx->fences.data[fence->index] = 0;
 115         r600_context_emit_fence(&ctx->ctx, ctx->fences.bo, fence->index, 1);
 116         return fence;
 117 }
 118
 119
 120 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 121                 unsigned flags)
 122 {
 123         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 124         struct r600_fence **rfence = (struct r600_fence**)fence;
 125
 126         if (rfence)
 127                 *rfence = r600_create_fence(rctx);
 128
 129         r600_context_flush(&rctx->ctx, flags);
 130 }
 131
 132 static void r600_flush_from_st(struct pipe_context *ctx,
 133                                struct pipe_fence_handle **fence)
 134 {
 135         r600_flush(ctx, fence, 0);
 136 }
 137
 138 static void r600_flush_from_winsys(void *ctx, unsigned flags)
 139 {
 140         r600_flush((struct pipe_context*)ctx, NULL, flags);
 141 }
 142
 143 static void r600_update_num_contexts(struct r600_screen *rscreen, int diff)
 144 {
 145         pipe_mutex_lock(rscreen->mutex_num_contexts);
 146         if (diff > 0) {
 147                 rscreen->num_contexts++;
 148
 149                 if (rscreen->num_contexts > 1)
 150                         util_slab_set_thread_safety(&rscreen->pool_buffers,
 151                                                     UTIL_SLAB_MULTITHREADED);
 152         } else {
 153                 rscreen->num_contexts--;
 154
 155                 if (rscreen->num_contexts <= 1)
 156                         util_slab_set_thread_safety(&rscreen->pool_buffers,
 157                                                     UTIL_SLAB_SINGLETHREADED);
 158         }
 159         pipe_mutex_unlock(rscreen->mutex_num_contexts);
 160 }
 161
 162 static void r600_destroy_context(struct pipe_context *context)
 163 {
 164         struct r600_pipe_context *rctx = (struct r600_pipe_context *)context;
 165
 166         rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
 167         util_unreference_framebuffer_state(&rctx->framebuffer);
 168
 169         r600_context_fini(&rctx->ctx);
 170
 171         util_blitter_destroy(rctx->blitter);
 172
 173         for (int i = 0; i < R600_PIPE_NSTATES; i++) {
 174                 free(rctx->states[i]);
 175         }
 176
 177         u_vbuf_destroy(rctx->vbuf_mgr);
 178         util_slab_destroy(&rctx->pool_transfers);
 179
 180         if (rctx->fences.bo) {
 181                 struct r600_fence_block *entry, *tmp;
 182
 183                 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rctx->fences.blocks, head) {
 184                         LIST_DEL(&entry->head);
 185                         FREE(entry);
 186                 }
 187
 188                 rctx->ws->buffer_unmap(rctx->fences.bo->buf);
 189                 pipe_resource_reference((struct pipe_resource**)&rctx->fences.bo, NULL);
 190         }
 191
 192         r600_update_num_contexts(rctx->screen, -1);
 193
 194         FREE(rctx);
 195 }
 196
 197 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 198 {
 199         struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context);
 200         struct r600_screen* rscreen = (struct r600_screen *)screen;
 201
 202         if (rctx == NULL)
 203                 return NULL;
 204
 205         r600_update_num_contexts(rscreen, 1);
 206
 207         rctx->context.winsys = rscreen->screen.winsys;
 208         rctx->context.screen = screen;
 209         rctx->context.priv = priv;
 210         rctx->context.destroy = r600_destroy_context;
 211         rctx->context.flush = r600_flush_from_st;
 212
 213         /* Easy accessing of screen/winsys. */
 214         rctx->screen = rscreen;
 215         rctx->ws = rscreen->ws;
 216         rctx->radeon = rscreen->radeon;
 217         rctx->family = r600_get_family(rctx->radeon);
 218         rctx->chip_class = r600_get_family_class(rctx->radeon);
 219
 220         rctx->fences.bo = NULL;
 221         rctx->fences.data = NULL;
 222         rctx->fences.next_index = 0;
 223         LIST_INITHEAD(&rctx->fences.pool);
 224         LIST_INITHEAD(&rctx->fences.blocks);
 225
 226         r600_init_blit_functions(rctx);
 227         r600_init_query_functions(rctx);
 228         r600_init_context_resource_functions(rctx);
 229         r600_init_surface_functions(rctx);
 230         rctx->context.draw_vbo = r600_draw_vbo;
 231
 232         rctx->context.create_video_decoder = vl_create_decoder;
 233         rctx->context.create_video_buffer = vl_video_buffer_create;
 234
 235         switch (rctx->chip_class) {
 236         case R600:
 237         case R700:
 238                 r600_init_state_functions(rctx);
 239                 if (r600_context_init(&rctx->ctx, rctx->screen, rctx->radeon)) {
 240                         r600_destroy_context(&rctx->context);
 241                         return NULL;
 242                 }
 243                 r600_init_config(rctx);
 244                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 245                 break;
 246         case EVERGREEN:
 247         case CAYMAN:
 248                 evergreen_init_state_functions(rctx);
 249                 if (evergreen_context_init(&rctx->ctx, rctx->screen, rctx->radeon)) {
 250                         r600_destroy_context(&rctx->context);
 251                         return NULL;
 252                 }
 253                 evergreen_init_config(rctx);
 254                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 255                 break;
 256         default:
 257                 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
 258                 r600_destroy_context(&rctx->context);
 259                 return NULL;
 260         }
 261
 262         rctx->screen->ws->cs_set_flush_callback(rctx->ctx.cs, r600_flush_from_winsys, rctx);
 263
 264         util_slab_create(&rctx->pool_transfers,
 265                          sizeof(struct pipe_transfer), 64,
 266                          UTIL_SLAB_SINGLETHREADED);
 267
 268         rctx->vbuf_mgr = u_vbuf_create(&rctx->context, 1024 * 1024, 256,
 269                                            PIPE_BIND_VERTEX_BUFFER |
 270                                            PIPE_BIND_INDEX_BUFFER |
 271                                            PIPE_BIND_CONSTANT_BUFFER,
 272                                            U_VERTEX_FETCH_DWORD_ALIGNED);
 273         if (!rctx->vbuf_mgr) {
 274                 r600_destroy_context(&rctx->context);
 275                 return NULL;
 276         }
 277         rctx->vbuf_mgr->caps.format_fixed32 = 0;
 278
 279         rctx->blitter = util_blitter_create(&rctx->context);
 280         if (rctx->blitter == NULL) {
 281                 r600_destroy_context(&rctx->context);
 282                 return NULL;
 283         }
 284
 285         return &rctx->context;
 286 }
 287
 288 /*
 289  * pipe_screen
 290  */
 291 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 292 {
 293         return "X.Org";
 294 }
 295
 296 static const char *r600_get_family_name(enum radeon_family family)
 297 {
 298         switch(family) {
 299         case CHIP_R600: return "AMD R600";
 300         case CHIP_RV610: return "AMD RV610";
 301         case CHIP_RV630: return "AMD RV630";
 302         case CHIP_RV670: return "AMD RV670";
 303         case CHIP_RV620: return "AMD RV620";
 304         case CHIP_RV635: return "AMD RV635";
 305         case CHIP_RS780: return "AMD RS780";
 306         case CHIP_RS880: return "AMD RS880";
 307         case CHIP_RV770: return "AMD RV770";
 308         case CHIP_RV730: return "AMD RV730";
 309         case CHIP_RV710: return "AMD RV710";
 310         case CHIP_RV740: return "AMD RV740";
 311         case CHIP_CEDAR: return "AMD CEDAR";
 312         case CHIP_REDWOOD: return "AMD REDWOOD";
 313         case CHIP_JUNIPER: return "AMD JUNIPER";
 314         case CHIP_CYPRESS: return "AMD CYPRESS";
 315         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 316         case CHIP_PALM: return "AMD PALM";
 317         case CHIP_SUMO: return "AMD SUMO";
 318         case CHIP_SUMO2: return "AMD SUMO2";
 319         case CHIP_BARTS: return "AMD BARTS";
 320         case CHIP_TURKS: return "AMD TURKS";
 321         case CHIP_CAICOS: return "AMD CAICOS";
 322         case CHIP_CAYMAN: return "AMD CAYMAN";
 323         default: return "AMD unknown";
 324         }
 325 }
 326
 327 static const char* r600_get_name(struct pipe_screen* pscreen)
 328 {
 329         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 330         enum radeon_family family = r600_get_family(rscreen->radeon);
 331
 332         return r600_get_family_name(family);
 333 }
 334
 335 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 336 {
 337         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 338         enum radeon_family family = r600_get_family(rscreen->radeon);
 339
 340         switch (param) {
 341         /* Supported features (boolean caps). */
 342         case PIPE_CAP_NPOT_TEXTURES:
 343         case PIPE_CAP_TWO_SIDED_STENCIL:
 344         case PIPE_CAP_GLSL:
 345         case PIPE_CAP_DUAL_SOURCE_BLEND:
 346         case PIPE_CAP_ANISOTROPIC_FILTER:
 347         case PIPE_CAP_POINT_SPRITE:
 348         case PIPE_CAP_OCCLUSION_QUERY:
 349         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 350         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 351         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 352         case PIPE_CAP_TEXTURE_SWIZZLE:
 353         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 354         case PIPE_CAP_DEPTH_CLAMP:
 355         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 356         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 357         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 358         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 359         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 360         case PIPE_CAP_SM3:
 361         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 362         case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
 363         case PIPE_CAP_PRIMITIVE_RESTART:
 364         case PIPE_CAP_CONDITIONAL_RENDER:
 365         case PIPE_CAP_TEXTURE_BARRIER:
 366                 return 1;
 367
 368         /* Supported except the original R600. */
 369         case PIPE_CAP_INDEP_BLEND_ENABLE:
 370         case PIPE_CAP_INDEP_BLEND_FUNC:
 371                 /* R600 doesn't support per-MRT blends */
 372                 return family == CHIP_R600 ? 0 : 1;
 373
 374         /* Supported on Evergreen. */
 375         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 376                 return family >= CHIP_CEDAR ? 1 : 0;
 377
 378         /* Unsupported features. */
 379         case PIPE_CAP_STREAM_OUTPUT:
 380         case PIPE_CAP_TGSI_INSTANCEID:
 381         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 382         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 383                 return 0;
 384
 385         /* Texturing. */
 386         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 387         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 388         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 389                 if (family >= CHIP_CEDAR)
 390                         return 15;
 391                 else
 392                         return 14;
 393         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 394                 return rscreen->info.drm_minor >= 9 ?
 395                         (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
 396         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 397                 return 32;
 398
 399         /* Render targets. */
 400         case PIPE_CAP_MAX_RENDER_TARGETS:
 401                 /* FIXME some r6xx are buggy and can only do 4 */
 402                 return 8;
 403
 404         /* Timer queries, present when the clock frequency is non zero. */
 405         case PIPE_CAP_TIMER_QUERY:
 406                 return rscreen->info.r600_clock_crystal_freq != 0;
 407
 408         case PIPE_CAP_MIN_TEXEL_OFFSET:
 409                 return -8;
 410
 411         case PIPE_CAP_MAX_TEXEL_OFFSET:
 412                 return 7;
 413
 414         default:
 415                 R600_ERR("r600: unknown param %d\n", param);
 416                 return 0;
 417         }
 418 }
 419
 420 static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
 421 {
 422         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 423         enum radeon_family family = r600_get_family(rscreen->radeon);
 424
 425         switch (param) {
 426         case PIPE_CAP_MAX_LINE_WIDTH:
 427         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 428         case PIPE_CAP_MAX_POINT_WIDTH:
 429         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 430                 if (family >= CHIP_CEDAR)
 431                         return 16384.0f;
 432                 else
 433                         return 8192.0f;
 434         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 435                 return 16.0f;
 436         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 437                 return 16.0f;
 438         default:
 439                 R600_ERR("r600: unsupported paramf %d\n", param);
 440                 return 0.0f;
 441         }
 442 }
 443
 444 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 445 {
 446         switch(shader)
 447         {
 448         case PIPE_SHADER_FRAGMENT:
 449         case PIPE_SHADER_VERTEX:
 450                 break;
 451         case PIPE_SHADER_GEOMETRY:
 452                 /* TODO: support and enable geometry programs */
 453                 return 0;
 454         default:
 455                 /* TODO: support tessellation on Evergreen */
 456                 return 0;
 457         }
 458
 459         /* TODO: all these should be fixed, since r600 surely supports much more! */
 460         switch (param) {
 461         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 462         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 463         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 464         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 465                 return 16384;
 466         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 467                 return 8; /* FIXME */
 468         case PIPE_SHADER_CAP_MAX_INPUTS:
 469                 if(shader == PIPE_SHADER_FRAGMENT)
 470                         return 34;
 471                 else
 472                         return 32;
 473         case PIPE_SHADER_CAP_MAX_TEMPS:
 474                 return 256; /* Max native temporaries. */
 475         case PIPE_SHADER_CAP_MAX_ADDRS:
 476                 /* FIXME Isn't this equal to TEMPS? */
 477                 return 1; /* Max native address registers */
 478         case PIPE_SHADER_CAP_MAX_CONSTS:
 479                 return R600_MAX_CONST_BUFFER_SIZE;
 480         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 481                 return R600_MAX_CONST_BUFFERS;
 482         case PIPE_SHADER_CAP_MAX_PREDS:
 483                 return 0; /* FIXME */
 484         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 485                 return 1;
 486         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 487         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 488         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 489         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 490                 return 1;
 491         case PIPE_SHADER_CAP_SUBROUTINES:
 492                 return 0;
 493         case PIPE_SHADER_CAP_INTEGERS:
 494                 return 0;
 495         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 496                 return 16;
 497         default:
 498                 return 0;
 499         }
 500 }
 501
 502 static int r600_get_video_param(struct pipe_screen *screen,
 503                                 enum pipe_video_profile profile,
 504                                 enum pipe_video_cap param)
 505 {
 506         switch (param) {
 507         case PIPE_VIDEO_CAP_SUPPORTED:
 508                 return vl_profile_supported(screen, profile);
 509         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 510                 return 1;
 511         case PIPE_VIDEO_CAP_MAX_WIDTH:
 512         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 513                 return vl_video_buffer_max_size(screen);
 514         case PIPE_VIDEO_CAP_NUM_BUFFERS_DESIRED:
 515                 return vl_num_buffers_desired(screen, profile);
 516         default:
 517                 return 0;
 518         }
 519 }
 520
 521 static void r600_destroy_screen(struct pipe_screen* pscreen)
 522 {
 523         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 524
 525         if (rscreen == NULL)
 526                 return;
 527
 528         radeon_destroy(rscreen->radeon);
 529         rscreen->ws->destroy(rscreen->ws);
 530
 531         util_slab_destroy(&rscreen->pool_buffers);
 532         pipe_mutex_destroy(rscreen->mutex_num_contexts);
 533         FREE(rscreen);
 534 }
 535
 536 static void r600_fence_reference(struct pipe_screen *pscreen,
 537                                  struct pipe_fence_handle **ptr,
 538                                  struct pipe_fence_handle *fence)
 539 {
 540         struct r600_fence **oldf = (struct r600_fence**)ptr;
 541         struct r600_fence *newf = (struct r600_fence*)fence;
 542
 543         if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
 544                 struct r600_pipe_context *ctx = (*oldf)->ctx;
 545                 LIST_ADDTAIL(&(*oldf)->head, &ctx->fences.pool);
 546         }
 547
 548         *ptr = fence;
 549 }
 550
 551 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
 552                                     struct pipe_fence_handle *fence)
 553 {
 554         struct r600_fence *rfence = (struct r600_fence*)fence;
 555         struct r600_pipe_context *ctx = rfence->ctx;
 556
 557         return ctx->fences.data[rfence->index];
 558 }
 559
 560 static boolean r600_fence_finish(struct pipe_screen *pscreen,
 561                                  struct pipe_fence_handle *fence,
 562                                  uint64_t timeout)
 563 {
 564         struct r600_fence *rfence = (struct r600_fence*)fence;
 565         struct r600_pipe_context *ctx = rfence->ctx;
 566         int64_t start_time = 0;
 567         unsigned spins = 0;
 568
 569         if (timeout != PIPE_TIMEOUT_INFINITE) {
 570                 start_time = os_time_get();
 571
 572                 /* Convert to microseconds. */
 573                 timeout /= 1000;
 574         }
 575
 576         while (ctx->fences.data[rfence->index] == 0) {
 577                 if (++spins % 256)
 578                         continue;
 579 #ifdef PIPE_OS_UNIX
 580                 sched_yield();
 581 #else
 582                 os_time_sleep(10);
 583 #endif
 584                 if (timeout != PIPE_TIMEOUT_INFINITE &&
 585                     os_time_get() - start_time >= timeout) {
 586                         return FALSE;
 587                 }
 588         }
 589
 590         return TRUE;
 591 }
 592
 593 static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 594 {
 595         switch ((tiling_config & 0xe) >> 1) {
 596         case 0:
 597                 rscreen->tiling_info.num_channels = 1;
 598                 break;
 599         case 1:
 600                 rscreen->tiling_info.num_channels = 2;
 601                 break;
 602         case 2:
 603                 rscreen->tiling_info.num_channels = 4;
 604                 break;
 605         case 3:
 606                 rscreen->tiling_info.num_channels = 8;
 607                 break;
 608         default:
 609                 return -EINVAL;
 610         }
 611
 612         switch ((tiling_config & 0x30) >> 4) {
 613         case 0:
 614                 rscreen->tiling_info.num_banks = 4;
 615                 break;
 616         case 1:
 617                 rscreen->tiling_info.num_banks = 8;
 618                 break;
 619         default:
 620                 return -EINVAL;
 621
 622         }
 623         switch ((tiling_config & 0xc0) >> 6) {
 624         case 0:
 625                 rscreen->tiling_info.group_bytes = 256;
 626                 break;
 627         case 1:
 628                 rscreen->tiling_info.group_bytes = 512;
 629                 break;
 630         default:
 631                 return -EINVAL;
 632         }
 633         return 0;
 634 }
 635
 636 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 637 {
 638         switch (tiling_config & 0xf) {
 639         case 0:
 640                 rscreen->tiling_info.num_channels = 1;
 641                 break;
 642         case 1:
 643                 rscreen->tiling_info.num_channels = 2;
 644                 break;
 645         case 2:
 646                 rscreen->tiling_info.num_channels = 4;
 647                 break;
 648         case 3:
 649                 rscreen->tiling_info.num_channels = 8;
 650                 break;
 651         default:
 652                 return -EINVAL;
 653         }
 654
 655         switch ((tiling_config & 0xf0) >> 4) {
 656         case 0:
 657                 rscreen->tiling_info.num_banks = 4;
 658                 break;
 659         case 1:
 660                 rscreen->tiling_info.num_banks = 8;
 661                 break;
 662         case 2:
 663                 rscreen->tiling_info.num_banks = 16;
 664                 break;
 665         default:
 666                 return -EINVAL;
 667         }
 668
 669         switch ((tiling_config & 0xf00) >> 8) {
 670         case 0:
 671                 rscreen->tiling_info.group_bytes = 256;
 672                 break;
 673         case 1:
 674                 rscreen->tiling_info.group_bytes = 512;
 675                 break;
 676         default:
 677                 return -EINVAL;
 678         }
 679         return 0;
 680 }
 681
 682 static int r600_init_tiling(struct r600_screen *rscreen)
 683 {
 684         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 685
 686         /* set default group bytes, overridden by tiling info ioctl */
 687         if (r600_get_family_class(rscreen->radeon) <= R700) {
 688                 rscreen->tiling_info.group_bytes = 256;
 689         } else {
 690                 rscreen->tiling_info.group_bytes = 512;
 691         }
 692
 693         if (!tiling_config)
 694                 return 0;
 695
 696         if (r600_get_family_class(rscreen->radeon) <= R700) {
 697                 return r600_interpret_tiling(rscreen, tiling_config);
 698         } else {
 699                 return evergreen_interpret_tiling(rscreen, tiling_config);
 700         }
 701 }
 702
 703 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 704 {
 705         struct r600_screen *rscreen;
 706         struct radeon *radeon = radeon_create(ws);
 707         if (!radeon) {
 708                 return NULL;
 709         }
 710
 711         rscreen = CALLOC_STRUCT(r600_screen);
 712         if (rscreen == NULL) {
 713                 radeon_destroy(radeon);
 714                 return NULL;
 715         }
 716
 717         rscreen->ws = ws;
 718         rscreen->radeon = radeon;
 719         ws->query_info(ws, &rscreen->info);
 720
 721         if (r600_init_tiling(rscreen)) {
 722                 radeon_destroy(radeon);
 723                 FREE(rscreen);
 724                 return NULL;
 725         }
 726
 727         rscreen->screen.winsys = (struct pipe_winsys*)ws;
 728         rscreen->screen.destroy = r600_destroy_screen;
 729         rscreen->screen.get_name = r600_get_name;
 730         rscreen->screen.get_vendor = r600_get_vendor;
 731         rscreen->screen.get_param = r600_get_param;
 732         rscreen->screen.get_shader_param = r600_get_shader_param;
 733         rscreen->screen.get_paramf = r600_get_paramf;
 734         rscreen->screen.get_video_param = r600_get_video_param;
 735         if (r600_get_family_class(radeon) >= EVERGREEN) {
 736                 rscreen->screen.is_format_supported = evergreen_is_format_supported;
 737         } else {
 738                 rscreen->screen.is_format_supported = r600_is_format_supported;
 739         }
 740         rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
 741         rscreen->screen.context_create = r600_create_context;
 742         rscreen->screen.fence_reference = r600_fence_reference;
 743         rscreen->screen.fence_signalled = r600_fence_signalled;
 744         rscreen->screen.fence_finish = r600_fence_finish;
 745         r600_init_screen_resource_functions(&rscreen->screen);
 746
 747         util_format_s3tc_init();
 748
 749         util_slab_create(&rscreen->pool_buffers,
 750                          sizeof(struct r600_resource), 64,
 751                          UTIL_SLAB_SINGLETHREADED);
 752
 753         pipe_mutex_init(rscreen->mutex_num_contexts);
 754
 755         return &rscreen->screen;
 756 }