src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25 #include "r600_isa.h"
  26 #include "evergreen_compute.h"
  27 #include "r600d.h"
  28
  29 #include "sb/sb_public.h"
  30
  31 #include <errno.h>
  32 #include "pipe/p_shader_tokens.h"
  33 #include "util/u_debug.h"
  34 #include "util/u_memory.h"
  35 #include "util/u_simple_shaders.h"
  36 #include "util/u_upload_mgr.h"
  37 #include "util/u_math.h"
  38 #include "vl/vl_decoder.h"
  39 #include "vl/vl_video_buffer.h"
  40 #include "radeon/radeon_video.h"
  41 #include "radeon/radeon_uvd.h"
  42 #include "os/os_time.h"
  43
  44 static const struct debug_named_value r600_debug_options[] = {
  45         /* features */
  46         { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
  47
  48         /* shader backend */
  49         { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
  50         { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
  51         { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
  52         { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
  53         { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
  54         { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
  55         { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
  56         { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
  57
  58         DEBUG_NAMED_VALUE_END /* must be last */
  59 };
  60
  61 /*
  62  * pipe_context
  63  */
  64
  65 static void r600_destroy_context(struct pipe_context *context)
  66 {
  67         struct r600_context *rctx = (struct r600_context *)context;
  68         unsigned sh;
  69
  70         r600_isa_destroy(rctx->isa);
  71
  72         r600_sb_context_destroy(rctx->sb_context);
  73
  74         r600_resource_reference(&rctx->dummy_cmask, NULL);
  75         r600_resource_reference(&rctx->dummy_fmask, NULL);
  76
  77         for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
  78                 rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, NULL);
  79                 free(rctx->driver_consts[sh].constants);
  80         }
  81
  82         if (rctx->fixed_func_tcs_shader)
  83                 rctx->b.b.delete_tcs_state(&rctx->b.b, rctx->fixed_func_tcs_shader);
  84
  85         if (rctx->custom_dsa_flush) {
  86                 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
  87         }
  88         if (rctx->custom_blend_resolve) {
  89                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
  90         }
  91         if (rctx->custom_blend_decompress) {
  92                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
  93         }
  94         if (rctx->custom_blend_fastclear) {
  95                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
  96         }
  97         util_unreference_framebuffer_state(&rctx->framebuffer.state);
  98
  99         if (rctx->blitter) {
 100                 util_blitter_destroy(rctx->blitter);
 101         }
 102         if (rctx->allocator_fetch_shader) {
 103                 u_suballocator_destroy(rctx->allocator_fetch_shader);
 104         }
 105
 106         r600_release_command_buffer(&rctx->start_cs_cmd);
 107
 108         FREE(rctx->start_compute_cs_cmd.buf);
 109
 110         r600_common_context_cleanup(&rctx->b);
 111         FREE(rctx);
 112 }
 113
 114 static struct pipe_context *r600_create_context(struct pipe_screen *screen,
 115                                                 void *priv, unsigned flags)
 116 {
 117         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 118         struct r600_screen* rscreen = (struct r600_screen *)screen;
 119         struct radeon_winsys *ws = rscreen->b.ws;
 120
 121         if (!rctx)
 122                 return NULL;
 123
 124         rctx->b.b.screen = screen;
 125         rctx->b.b.priv = priv;
 126         rctx->b.b.destroy = r600_destroy_context;
 127         rctx->b.set_atom_dirty = (void *)r600_set_atom_dirty;
 128
 129         if (!r600_common_context_init(&rctx->b, &rscreen->b, flags))
 130                 goto fail;
 131
 132         rctx->screen = rscreen;
 133         LIST_INITHEAD(&rctx->texture_buffers);
 134
 135         r600_init_blit_functions(rctx);
 136
 137         if (rscreen->b.info.has_uvd) {
 138                 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
 139                 rctx->b.b.create_video_buffer = r600_video_buffer_create;
 140         } else {
 141                 rctx->b.b.create_video_codec = vl_create_decoder;
 142                 rctx->b.b.create_video_buffer = vl_video_buffer_create;
 143         }
 144
 145         r600_init_common_state_functions(rctx);
 146
 147         switch (rctx->b.chip_class) {
 148         case R600:
 149         case R700:
 150                 r600_init_state_functions(rctx);
 151                 r600_init_atom_start_cs(rctx);
 152                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 153                 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
 154                                                                       : r600_create_resolve_blend(rctx);
 155                 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
 156                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
 157                                            rctx->b.family == CHIP_RV620 ||
 158                                            rctx->b.family == CHIP_RS780 ||
 159                                            rctx->b.family == CHIP_RS880 ||
 160                                            rctx->b.family == CHIP_RV710);
 161                 break;
 162         case EVERGREEN:
 163         case CAYMAN:
 164                 evergreen_init_state_functions(rctx);
 165                 evergreen_init_atom_start_cs(rctx);
 166                 evergreen_init_atom_start_compute_cs(rctx);
 167                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 168                 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
 169                 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
 170                 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
 171                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
 172                                            rctx->b.family == CHIP_PALM ||
 173                                            rctx->b.family == CHIP_SUMO ||
 174                                            rctx->b.family == CHIP_SUMO2 ||
 175                                            rctx->b.family == CHIP_CAICOS ||
 176                                            rctx->b.family == CHIP_CAYMAN ||
 177                                            rctx->b.family == CHIP_ARUBA);
 178                 break;
 179         default:
 180                 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
 181                 goto fail;
 182         }
 183
 184         rctx->b.gfx.cs = ws->cs_create(rctx->b.ctx, RING_GFX,
 185                                        r600_context_gfx_flush, rctx);
 186         rctx->b.gfx.flush = r600_context_gfx_flush;
 187
 188         rctx->allocator_fetch_shader =
 189                 u_suballocator_create(&rctx->b.b, 64 * 1024,
 190                                       0, PIPE_USAGE_DEFAULT, 0, FALSE);
 191         if (!rctx->allocator_fetch_shader)
 192                 goto fail;
 193
 194         rctx->isa = calloc(1, sizeof(struct r600_isa));
 195         if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
 196                 goto fail;
 197
 198         if (rscreen->b.debug_flags & DBG_FORCE_DMA)
 199                 rctx->b.b.resource_copy_region = rctx->b.dma_copy;
 200
 201         rctx->blitter = util_blitter_create(&rctx->b.b);
 202         if (rctx->blitter == NULL)
 203                 goto fail;
 204         util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
 205         rctx->blitter->draw_rectangle = r600_draw_rectangle;
 206
 207         r600_begin_new_cs(rctx);
 208
 209         return &rctx->b.b;
 210
 211 fail:
 212         r600_destroy_context(&rctx->b.b);
 213         return NULL;
 214 }
 215
 216 /*
 217  * pipe_screen
 218  */
 219
 220 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 221 {
 222         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 223         enum radeon_family family = rscreen->b.family;
 224
 225         switch (param) {
 226         /* Supported features (boolean caps). */
 227         case PIPE_CAP_NPOT_TEXTURES:
 228         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 229         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 230         case PIPE_CAP_TWO_SIDED_STENCIL:
 231         case PIPE_CAP_ANISOTROPIC_FILTER:
 232         case PIPE_CAP_POINT_SPRITE:
 233         case PIPE_CAP_OCCLUSION_QUERY:
 234         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 235         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 236         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 237         case PIPE_CAP_TEXTURE_SWIZZLE:
 238         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 239         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 240         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 241         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 242         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 243         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 244         case PIPE_CAP_SM3:
 245         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 246         case PIPE_CAP_PRIMITIVE_RESTART:
 247         case PIPE_CAP_CONDITIONAL_RENDER:
 248         case PIPE_CAP_TEXTURE_BARRIER:
 249         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 250         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 251         case PIPE_CAP_TGSI_INSTANCEID:
 252         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 253         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 254         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 255         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 256         case PIPE_CAP_START_INSTANCE:
 257         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 258         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 259         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 260         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 261         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 262         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 263         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 264         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 265         case PIPE_CAP_SAMPLE_SHADING:
 266         case PIPE_CAP_CLIP_HALFZ:
 267         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 268         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 269         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 270         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 271         case PIPE_CAP_TGSI_TXQS:
 272         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 273         case PIPE_CAP_INVALIDATE_BUFFER:
 274         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 275         case PIPE_CAP_QUERY_MEMORY_INFO:
 276         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 277         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 278         case PIPE_CAP_CLEAR_TEXTURE:
 279         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 280                 return 1;
 281
 282         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 283                 return rscreen->b.info.drm_major == 2 && rscreen->b.info.drm_minor >= 43;
 284
 285         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 286                 return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;
 287
 288         case PIPE_CAP_COMPUTE:
 289                 return rscreen->b.chip_class > R700;
 290
 291         case PIPE_CAP_TGSI_TEXCOORD:
 292                 return 0;
 293
 294         case PIPE_CAP_FAKE_SW_MSAA:
 295                 return 0;
 296
 297         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 298                 return MIN2(rscreen->b.info.max_alloc_size, INT_MAX);
 299
 300         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 301                 return R600_MAP_BUFFER_ALIGNMENT;
 302
 303         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 304                 return 256;
 305
 306         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 307                 return 1;
 308
 309         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 310                 if (family >= CHIP_CEDAR)
 311                    return 410;
 312                 /* pre-evergreen geom shaders need newer kernel */
 313                 if (rscreen->b.info.drm_minor >= 37)
 314                    return 330;
 315                 return 140;
 316
 317         /* Supported except the original R600. */
 318         case PIPE_CAP_INDEP_BLEND_ENABLE:
 319         case PIPE_CAP_INDEP_BLEND_FUNC:
 320                 /* R600 doesn't support per-MRT blends */
 321                 return family == CHIP_R600 ? 0 : 1;
 322
 323         /* Supported on Evergreen. */
 324         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 325         case PIPE_CAP_CUBE_MAP_ARRAY:
 326         case PIPE_CAP_TEXTURE_GATHER_SM5:
 327         case PIPE_CAP_TEXTURE_QUERY_LOD:
 328         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 329         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 330         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 331                 return family >= CHIP_CEDAR ? 1 : 0;
 332         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 333                 return family >= CHIP_CEDAR ? 4 : 0;
 334         case PIPE_CAP_DRAW_INDIRECT:
 335                 /* kernel command checker support is also required */
 336                 return family >= CHIP_CEDAR && rscreen->b.info.drm_minor >= 41;
 337
 338         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 339                 return family >= CHIP_CEDAR ? 0 : 1;
 340
 341         /* Unsupported features. */
 342         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 343         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 344         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 345         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 346         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 347         case PIPE_CAP_USER_VERTEX_BUFFERS:
 348         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 349         case PIPE_CAP_VERTEXID_NOBASE:
 350         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 351         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 352         case PIPE_CAP_SHAREABLE_SHADERS:
 353         case PIPE_CAP_DRAW_PARAMETERS:
 354         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 355         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 356         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 357         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 358         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 359         case PIPE_CAP_GENERATE_MIPMAP:
 360         case PIPE_CAP_STRING_MARKER:
 361         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 362         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 363         case PIPE_CAP_CULL_DISTANCE:
 364         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 365         case PIPE_CAP_TGSI_VOTE:
 366         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 367         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 368         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 369         case PIPE_CAP_NATIVE_FENCE_FD:
 370         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 371         case PIPE_CAP_TGSI_FS_FBFETCH:
 372         case PIPE_CAP_INT64:
 373         case PIPE_CAP_INT64_DIVMOD:
 374         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 375         case PIPE_CAP_TGSI_CLOCK:
 376         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 377         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 378         case PIPE_CAP_TGSI_BALLOT:
 379                 return 0;
 380
 381         case PIPE_CAP_DOUBLES:
 382                 if (rscreen->b.family == CHIP_ARUBA ||
 383                     rscreen->b.family == CHIP_CAYMAN ||
 384                     rscreen->b.family == CHIP_CYPRESS ||
 385                     rscreen->b.family == CHIP_HEMLOCK)
 386                         return 1;
 387                 return 0;
 388
 389         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 390                 if (family >= CHIP_CEDAR)
 391                         return 30;
 392                 else
 393                         return 0;
 394         /* Stream output. */
 395         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 396                 return rscreen->b.has_streamout ? 4 : 0;
 397         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 398         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 399                 return rscreen->b.has_streamout ? 1 : 0;
 400         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 401         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 402                 return 32*4;
 403
 404         /* Geometry shader output. */
 405         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 406                 return 1024;
 407         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 408                 return 16384;
 409         case PIPE_CAP_MAX_VERTEX_STREAMS:
 410                 return family >= CHIP_CEDAR ? 4 : 1;
 411
 412         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 413                 return 2047;
 414
 415         /* Texturing. */
 416         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 417         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 418                 if (family >= CHIP_CEDAR)
 419                         return 15;
 420                 else
 421                         return 14;
 422         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 423                 /* textures support 8192, but layered rendering supports 2048 */
 424                 return 12;
 425         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 426                 /* textures support 8192, but layered rendering supports 2048 */
 427                 return 2048;
 428
 429         /* Render targets. */
 430         case PIPE_CAP_MAX_RENDER_TARGETS:
 431                 /* XXX some r6xx are buggy and can only do 4 */
 432                 return 8;
 433
 434         case PIPE_CAP_MAX_VIEWPORTS:
 435                 return R600_MAX_VIEWPORTS;
 436         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 437                 return 8;
 438
 439         /* Timer queries, present when the clock frequency is non zero. */
 440         case PIPE_CAP_QUERY_TIME_ELAPSED:
 441                 return rscreen->b.info.clock_crystal_freq != 0;
 442         case PIPE_CAP_QUERY_TIMESTAMP:
 443                 return rscreen->b.info.drm_minor >= 20 &&
 444                        rscreen->b.info.clock_crystal_freq != 0;
 445
 446         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 447         case PIPE_CAP_MIN_TEXEL_OFFSET:
 448                 return -8;
 449
 450         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 451         case PIPE_CAP_MAX_TEXEL_OFFSET:
 452                 return 7;
 453
 454         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 455                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 456         case PIPE_CAP_ENDIANNESS:
 457                 return PIPE_ENDIAN_LITTLE;
 458
 459         case PIPE_CAP_VENDOR_ID:
 460                 return ATI_VENDOR_ID;
 461         case PIPE_CAP_DEVICE_ID:
 462                 return rscreen->b.info.pci_id;
 463         case PIPE_CAP_ACCELERATED:
 464                 return 1;
 465         case PIPE_CAP_VIDEO_MEMORY:
 466                 return rscreen->b.info.vram_size >> 20;
 467         case PIPE_CAP_UMA:
 468                 return 0;
 469         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 470                 return rscreen->b.chip_class >= R700;
 471         case PIPE_CAP_PCI_GROUP:
 472                 return rscreen->b.info.pci_domain;
 473         case PIPE_CAP_PCI_BUS:
 474                 return rscreen->b.info.pci_bus;
 475         case PIPE_CAP_PCI_DEVICE:
 476                 return rscreen->b.info.pci_dev;
 477         case PIPE_CAP_PCI_FUNCTION:
 478                 return rscreen->b.info.pci_func;
 479         }
 480         return 0;
 481 }
 482
 483 static int r600_get_shader_param(struct pipe_screen* pscreen,
 484                                  enum pipe_shader_type shader,
 485                                  enum pipe_shader_cap param)
 486 {
 487         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 488
 489         switch(shader)
 490         {
 491         case PIPE_SHADER_FRAGMENT:
 492         case PIPE_SHADER_VERTEX:
 493         case PIPE_SHADER_COMPUTE:
 494                 break;
 495         case PIPE_SHADER_GEOMETRY:
 496                 if (rscreen->b.family >= CHIP_CEDAR)
 497                         break;
 498                 /* pre-evergreen geom shaders need newer kernel */
 499                 if (rscreen->b.info.drm_minor >= 37)
 500                         break;
 501                 return 0;
 502         case PIPE_SHADER_TESS_CTRL:
 503         case PIPE_SHADER_TESS_EVAL:
 504                 if (rscreen->b.family >= CHIP_CEDAR)
 505                         break;
 506         default:
 507                 return 0;
 508         }
 509
 510         switch (param) {
 511         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 512         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 513         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 514         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 515                 return 16384;
 516         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 517                 return 32;
 518         case PIPE_SHADER_CAP_MAX_INPUTS:
 519                 return shader == PIPE_SHADER_VERTEX ? 16 : 32;
 520         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 521                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 522         case PIPE_SHADER_CAP_MAX_TEMPS:
 523                 return 256; /* Max native temporaries. */
 524         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 525                 if (shader == PIPE_SHADER_COMPUTE) {
 526                         uint64_t max_const_buffer_size;
 527                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 528                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 529                                 &max_const_buffer_size);
 530                         return MIN2(max_const_buffer_size, INT_MAX);
 531
 532                 } else {
 533                         return R600_MAX_CONST_BUFFER_SIZE;
 534                 }
 535         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 536                 return R600_MAX_USER_CONST_BUFFERS;
 537         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 538                 return 1;
 539         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 540                 return 1;
 541         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 542         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 543         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 544         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 545                 return 1;
 546         case PIPE_SHADER_CAP_SUBROUTINES:
 547                 return 0;
 548         case PIPE_SHADER_CAP_INTEGERS:
 549         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 550                 return 1;
 551         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 552         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 553                 return 16;
 554         case PIPE_SHADER_CAP_PREFERRED_IR:
 555                 if (shader == PIPE_SHADER_COMPUTE) {
 556                         return PIPE_SHADER_IR_NATIVE;
 557                 } else {
 558                         return PIPE_SHADER_IR_TGSI;
 559                 }
 560         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 561                 return 0;
 562         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 563                 if (rscreen->b.family == CHIP_ARUBA ||
 564                     rscreen->b.family == CHIP_CAYMAN ||
 565                     rscreen->b.family == CHIP_CYPRESS ||
 566                     rscreen->b.family == CHIP_HEMLOCK)
 567                         return 1;
 568                 return 0;
 569         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 570         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 571         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 572         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 573         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 574                 return 0;
 575         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 576                 /* due to a bug in the shader compiler, some loops hang
 577                  * if they are not unrolled, see:
 578                  *    https://bugs.freedesktop.org/show_bug.cgi?id=86720
 579                  */
 580                 return 255;
 581         }
 582         return 0;
 583 }
 584
 585 static void r600_destroy_screen(struct pipe_screen* pscreen)
 586 {
 587         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 588
 589         if (!rscreen)
 590                 return;
 591
 592         if (!rscreen->b.ws->unref(rscreen->b.ws))
 593                 return;
 594
 595         if (rscreen->global_pool) {
 596                 compute_memory_pool_delete(rscreen->global_pool);
 597         }
 598
 599         r600_destroy_common_screen(&rscreen->b);
 600 }
 601
 602 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
 603                                                   const struct pipe_resource *templ)
 604 {
 605         if (templ->target == PIPE_BUFFER &&
 606             (templ->bind & PIPE_BIND_GLOBAL))
 607                 return r600_compute_global_buffer_create(screen, templ);
 608
 609         return r600_resource_create_common(screen, templ);
 610 }
 611
 612 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 613 {
 614         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 615
 616         if (!rscreen) {
 617                 return NULL;
 618         }
 619
 620         /* Set functions first. */
 621         rscreen->b.b.context_create = r600_create_context;
 622         rscreen->b.b.destroy = r600_destroy_screen;
 623         rscreen->b.b.get_param = r600_get_param;
 624         rscreen->b.b.get_shader_param = r600_get_shader_param;
 625         rscreen->b.b.resource_create = r600_resource_create;
 626
 627         if (!r600_common_screen_init(&rscreen->b, ws)) {
 628                 FREE(rscreen);
 629                 return NULL;
 630         }
 631
 632         if (rscreen->b.info.chip_class >= EVERGREEN) {
 633                 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
 634         } else {
 635                 rscreen->b.b.is_format_supported = r600_is_format_supported;
 636         }
 637
 638         rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
 639         if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
 640                 rscreen->b.debug_flags |= DBG_COMPUTE;
 641         if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
 642                 rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS | DBG_TCS | DBG_TES;
 643         if (!debug_get_bool_option("R600_HYPERZ", TRUE))
 644                 rscreen->b.debug_flags |= DBG_NO_HYPERZ;
 645
 646         if (rscreen->b.family == CHIP_UNKNOWN) {
 647                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
 648                 FREE(rscreen);
 649                 return NULL;
 650         }
 651
 652         /* Figure out streamout kernel support. */
 653         switch (rscreen->b.chip_class) {
 654         case R600:
 655                 if (rscreen->b.family < CHIP_RS780) {
 656                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 657                 } else {
 658                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
 659                 }
 660                 break;
 661         case R700:
 662                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
 663                 break;
 664         case EVERGREEN:
 665         case CAYMAN:
 666                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 667                 break;
 668         default:
 669                 rscreen->b.has_streamout = FALSE;
 670                 break;
 671         }
 672
 673         /* MSAA support. */
 674         switch (rscreen->b.chip_class) {
 675         case R600:
 676         case R700:
 677                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
 678                 rscreen->has_compressed_msaa_texturing = false;
 679                 break;
 680         case EVERGREEN:
 681                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 682                 rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
 683                 break;
 684         case CAYMAN:
 685                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 686                 rscreen->has_compressed_msaa_texturing = true;
 687                 break;
 688         default:
 689                 rscreen->has_msaa = FALSE;
 690                 rscreen->has_compressed_msaa_texturing = false;
 691         }
 692
 693         rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
 694                               !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
 695
 696         rscreen->b.barrier_flags.cp_to_L2 =
 697                 R600_CONTEXT_INV_VERTEX_CACHE |
 698                 R600_CONTEXT_INV_TEX_CACHE |
 699                 R600_CONTEXT_INV_CONST_CACHE;
 700         rscreen->b.barrier_flags.compute_to_L2 = R600_CONTEXT_PS_PARTIAL_FLUSH;
 701
 702         rscreen->global_pool = compute_memory_pool_new(rscreen);
 703
 704         /* Create the auxiliary context. This must be done last. */
 705         rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL, 0);
 706
 707 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
 708         struct pipe_resource templ = {};
 709
 710         templ.width0 = 4;
 711         templ.height0 = 2048;
 712         templ.depth0 = 1;
 713         templ.array_size = 1;
 714         templ.target = PIPE_TEXTURE_2D;
 715         templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
 716         templ.usage = PIPE_USAGE_DEFAULT;
 717
 718         struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
 719         unsigned char *map = ws->buffer_map(res->buf, NULL, PIPE_TRANSFER_WRITE);
 720
 721         memset(map, 0, 256);
 722
 723         r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
 724         r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
 725         r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
 726         r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
 727         r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
 728
 729         ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
 730
 731         int i;
 732         for (i = 0; i < 256; i++) {
 733                 printf("%02X", map[i]);
 734                 if (i % 16 == 15)
 735                         printf("\n");
 736         }
 737 #endif
 738
 739         if (rscreen->b.debug_flags & DBG_TEST_DMA)
 740                 r600_test_dma(&rscreen->b);
 741
 742         r600_query_fix_enabled_rb_mask(&rscreen->b);
 743         return &rscreen->b.b;
 744 }