src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "pipe/p_context.h"
  28 #include "tgsi/tgsi_scan.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "tgsi/tgsi_util.h"
  31 #include "util/u_blitter.h"
  32 #include "util/u_double_list.h"
  33 #include "util/u_format.h"
  34 #include "util/u_format_s3tc.h"
  35 #include "util/u_transfer.h"
  36 #include "util/u_surface.h"
  37 #include "util/u_pack_color.h"
  38 #include "util/u_memory.h"
  39 #include "util/u_inlines.h"
  40 #include "util/u_simple_shaders.h"
  41 #include "util/u_upload_mgr.h"
  42 #include "vl/vl_decoder.h"
  43 #include "vl/vl_video_buffer.h"
  44 #include "os/os_time.h"
  45 #include "pipebuffer/pb_buffer.h"
  46 #include "r600.h"
  47 #include "r600d.h"
  48 #include "r600_resource.h"
  49 #include "r600_shader.h"
  50 #include "r600_pipe.h"
  51
  52 /*
  53  * pipe_context
  54  */
  55 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
  56 {
  57         struct r600_screen *rscreen = rctx->screen;
  58         struct r600_fence *fence = NULL;
  59
  60         pipe_mutex_lock(rscreen->fences.mutex);
  61
  62         if (!rscreen->fences.bo) {
  63                 /* Create the shared buffer object */
  64                 rscreen->fences.bo = (struct r600_resource*)
  65                         pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
  66                                            PIPE_USAGE_STAGING, 4096);
  67                 if (!rscreen->fences.bo) {
  68                         R600_ERR("r600: failed to create bo for fence objects\n");
  69                         goto out;
  70                 }
  71                 rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->buf,
  72                                                            rctx->cs,
  73                                                            PIPE_TRANSFER_READ_WRITE);
  74         }
  75
  76         if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
  77                 struct r600_fence *entry;
  78
  79                 /* Try to find a freed fence that has been signalled */
  80                 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
  81                         if (rscreen->fences.data[entry->index] != 0) {
  82                                 LIST_DELINIT(&entry->head);
  83                                 fence = entry;
  84                                 break;
  85                         }
  86                 }
  87         }
  88
  89         if (!fence) {
  90                 /* Allocate a new fence */
  91                 struct r600_fence_block *block;
  92                 unsigned index;
  93
  94                 if ((rscreen->fences.next_index + 1) >= 1024) {
  95                         R600_ERR("r600: too many concurrent fences\n");
  96                         goto out;
  97                 }
  98
  99                 index = rscreen->fences.next_index++;
 100
 101                 if (!(index % FENCE_BLOCK_SIZE)) {
 102                         /* Allocate a new block */
 103                         block = CALLOC_STRUCT(r600_fence_block);
 104                         if (block == NULL)
 105                                 goto out;
 106
 107                         LIST_ADD(&block->head, &rscreen->fences.blocks);
 108                 } else {
 109                         block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
 110                 }
 111
 112                 fence = &block->fences[index % FENCE_BLOCK_SIZE];
 113                 fence->index = index;
 114         }
 115
 116         pipe_reference_init(&fence->reference, 1);
 117
 118         rscreen->fences.data[fence->index] = 0;
 119         r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
 120
 121         /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
 122         fence->sleep_bo = (struct r600_resource*)
 123                         pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM,
 124                                            PIPE_USAGE_STAGING, 1);
 125         /* Add the fence as a dummy relocation. */
 126         r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE);
 127
 128 out:
 129         pipe_mutex_unlock(rscreen->fences.mutex);
 130         return fence;
 131 }
 132
 133
 134 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 135                 unsigned flags)
 136 {
 137         struct r600_context *rctx = (struct r600_context *)ctx;
 138         struct r600_fence **rfence = (struct r600_fence**)fence;
 139         struct pipe_query *render_cond = NULL;
 140         unsigned render_cond_mode = 0;
 141
 142         if (rfence)
 143                 *rfence = r600_create_fence(rctx);
 144
 145         /* Disable render condition. */
 146         if (rctx->current_render_cond) {
 147                 render_cond = rctx->current_render_cond;
 148                 render_cond_mode = rctx->current_render_cond_mode;
 149                 ctx->render_condition(ctx, NULL, 0);
 150         }
 151
 152         r600_context_flush(rctx, flags);
 153
 154         /* Re-enable render condition. */
 155         if (render_cond) {
 156                 ctx->render_condition(ctx, render_cond, render_cond_mode);
 157         }
 158 }
 159
 160 static void r600_flush_from_st(struct pipe_context *ctx,
 161                                struct pipe_fence_handle **fence)
 162 {
 163         r600_flush(ctx, fence, 0);
 164 }
 165
 166 static void r600_flush_from_winsys(void *ctx, unsigned flags)
 167 {
 168         r600_flush((struct pipe_context*)ctx, NULL, flags);
 169 }
 170
 171 static void r600_update_num_contexts(struct r600_screen *rscreen, int diff)
 172 {
 173         pipe_mutex_lock(rscreen->mutex_num_contexts);
 174         if (diff > 0) {
 175                 rscreen->num_contexts++;
 176
 177                 if (rscreen->num_contexts > 1)
 178                         util_slab_set_thread_safety(&rscreen->pool_buffers,
 179                                                     UTIL_SLAB_MULTITHREADED);
 180         } else {
 181                 rscreen->num_contexts--;
 182
 183                 if (rscreen->num_contexts <= 1)
 184                         util_slab_set_thread_safety(&rscreen->pool_buffers,
 185                                                     UTIL_SLAB_SINGLETHREADED);
 186         }
 187         pipe_mutex_unlock(rscreen->mutex_num_contexts);
 188 }
 189
 190 static void r600_destroy_context(struct pipe_context *context)
 191 {
 192         struct r600_context *rctx = (struct r600_context *)context;
 193
 194         if (rctx->dummy_pixel_shader) {
 195                 rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 196         }
 197         if (rctx->custom_dsa_flush) {
 198                 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
 199         }
 200         util_unreference_framebuffer_state(&rctx->framebuffer);
 201
 202         r600_context_fini(rctx);
 203
 204         if (rctx->blitter) {
 205                 util_blitter_destroy(rctx->blitter);
 206         }
 207         for (int i = 0; i < R600_PIPE_NSTATES; i++) {
 208                 free(rctx->states[i]);
 209         }
 210
 211         if (rctx->vbuf_mgr) {
 212                 u_vbuf_destroy(rctx->vbuf_mgr);
 213         }
 214         util_slab_destroy(&rctx->pool_transfers);
 215
 216         r600_update_num_contexts(rctx->screen, -1);
 217
 218         r600_release_command_buffer(&rctx->atom_start_cs);
 219
 220         if (rctx->cs) {
 221                 rctx->ws->cs_destroy(rctx->cs);
 222         }
 223
 224         FREE(rctx->range);
 225         FREE(rctx);
 226 }
 227
 228 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 229 {
 230         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 231         struct r600_screen* rscreen = (struct r600_screen *)screen;
 232
 233         if (rctx == NULL)
 234                 return NULL;
 235
 236         util_slab_create(&rctx->pool_transfers,
 237                          sizeof(struct pipe_transfer), 64,
 238                          UTIL_SLAB_SINGLETHREADED);
 239
 240         r600_update_num_contexts(rscreen, 1);
 241
 242         rctx->context.screen = screen;
 243         rctx->context.priv = priv;
 244         rctx->context.destroy = r600_destroy_context;
 245         rctx->context.flush = r600_flush_from_st;
 246
 247         /* Easy accessing of screen/winsys. */
 248         rctx->screen = rscreen;
 249         rctx->ws = rscreen->ws;
 250         rctx->family = rscreen->family;
 251         rctx->chip_class = rscreen->chip_class;
 252
 253         LIST_INITHEAD(&rctx->dirty_states);
 254         LIST_INITHEAD(&rctx->active_timer_queries);
 255         LIST_INITHEAD(&rctx->active_nontimer_queries);
 256         LIST_INITHEAD(&rctx->dirty);
 257         LIST_INITHEAD(&rctx->resource_dirty);
 258         LIST_INITHEAD(&rctx->enable_list);
 259
 260         rctx->range = CALLOC(NUM_RANGES, sizeof(struct r600_range));
 261         if (!rctx->range)
 262                 goto fail;
 263
 264         r600_init_blit_functions(rctx);
 265         r600_init_query_functions(rctx);
 266         r600_init_context_resource_functions(rctx);
 267         r600_init_surface_functions(rctx);
 268         rctx->context.draw_vbo = r600_draw_vbo;
 269
 270         rctx->context.create_video_decoder = vl_create_decoder;
 271         rctx->context.create_video_buffer = vl_video_buffer_create;
 272
 273         r600_init_common_atoms(rctx);
 274
 275         switch (rctx->chip_class) {
 276         case R600:
 277         case R700:
 278                 r600_init_state_functions(rctx);
 279                 r600_init_atom_start_cs(rctx);
 280                 if (r600_context_init(rctx))
 281                         goto fail;
 282                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 283                 break;
 284         case EVERGREEN:
 285         case CAYMAN:
 286                 evergreen_init_state_functions(rctx);
 287                 evergreen_init_atom_start_cs(rctx);
 288                 if (evergreen_context_init(rctx))
 289                         goto fail;
 290                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 291                 break;
 292         default:
 293                 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
 294                 goto fail;
 295         }
 296
 297         rctx->cs = rctx->ws->cs_create(rctx->ws);
 298         rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx);
 299         r600_emit_atom(rctx, &rctx->atom_start_cs.atom);
 300
 301         rctx->vbuf_mgr = u_vbuf_create(&rctx->context, 1024 * 1024, 256,
 302                                            PIPE_BIND_VERTEX_BUFFER |
 303                                            PIPE_BIND_INDEX_BUFFER |
 304                                            PIPE_BIND_CONSTANT_BUFFER,
 305                                            U_VERTEX_FETCH_DWORD_ALIGNED);
 306         if (!rctx->vbuf_mgr)
 307                 goto fail;
 308         rctx->vbuf_mgr->caps.format_fixed32 = 0;
 309
 310         rctx->blitter = util_blitter_create(&rctx->context);
 311         if (rctx->blitter == NULL)
 312                 goto fail;
 313
 314         r600_get_backend_mask(rctx); /* this emits commands and must be last */
 315
 316         if (rctx->chip_class == R600)
 317                 r600_set_max_scissor(rctx);
 318
 319         rctx->dummy_pixel_shader =
 320                 util_make_fragment_cloneinput_shader(&rctx->context, 0,
 321                                                      TGSI_SEMANTIC_GENERIC,
 322                                                      TGSI_INTERPOLATE_CONSTANT);
 323         rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader);
 324
 325         return &rctx->context;
 326
 327 fail:
 328         r600_destroy_context(&rctx->context);
 329         return NULL;
 330 }
 331
 332 /*
 333  * pipe_screen
 334  */
 335 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 336 {
 337         return "X.Org";
 338 }
 339
 340 static const char *r600_get_family_name(enum radeon_family family)
 341 {
 342         switch(family) {
 343         case CHIP_R600: return "AMD R600";
 344         case CHIP_RV610: return "AMD RV610";
 345         case CHIP_RV630: return "AMD RV630";
 346         case CHIP_RV670: return "AMD RV670";
 347         case CHIP_RV620: return "AMD RV620";
 348         case CHIP_RV635: return "AMD RV635";
 349         case CHIP_RS780: return "AMD RS780";
 350         case CHIP_RS880: return "AMD RS880";
 351         case CHIP_RV770: return "AMD RV770";
 352         case CHIP_RV730: return "AMD RV730";
 353         case CHIP_RV710: return "AMD RV710";
 354         case CHIP_RV740: return "AMD RV740";
 355         case CHIP_CEDAR: return "AMD CEDAR";
 356         case CHIP_REDWOOD: return "AMD REDWOOD";
 357         case CHIP_JUNIPER: return "AMD JUNIPER";
 358         case CHIP_CYPRESS: return "AMD CYPRESS";
 359         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 360         case CHIP_PALM: return "AMD PALM";
 361         case CHIP_SUMO: return "AMD SUMO";
 362         case CHIP_SUMO2: return "AMD SUMO2";
 363         case CHIP_BARTS: return "AMD BARTS";
 364         case CHIP_TURKS: return "AMD TURKS";
 365         case CHIP_CAICOS: return "AMD CAICOS";
 366         case CHIP_CAYMAN: return "AMD CAYMAN";
 367         default: return "AMD unknown";
 368         }
 369 }
 370
 371 static const char* r600_get_name(struct pipe_screen* pscreen)
 372 {
 373         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 374
 375         return r600_get_family_name(rscreen->family);
 376 }
 377
 378 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 379 {
 380         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 381         enum radeon_family family = rscreen->family;
 382
 383         switch (param) {
 384         /* Supported features (boolean caps). */
 385         case PIPE_CAP_NPOT_TEXTURES:
 386         case PIPE_CAP_TWO_SIDED_STENCIL:
 387         case PIPE_CAP_DUAL_SOURCE_BLEND:
 388         case PIPE_CAP_ANISOTROPIC_FILTER:
 389         case PIPE_CAP_POINT_SPRITE:
 390         case PIPE_CAP_OCCLUSION_QUERY:
 391         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 392         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 393         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 394         case PIPE_CAP_TEXTURE_SWIZZLE:
 395         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 396         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 397         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 398         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 399         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 400         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 401         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 402         case PIPE_CAP_SM3:
 403         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 404         case PIPE_CAP_PRIMITIVE_RESTART:
 405         case PIPE_CAP_CONDITIONAL_RENDER:
 406         case PIPE_CAP_TEXTURE_BARRIER:
 407         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 408         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 409                 return 1;
 410
 411         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 412                 return debug_get_bool_option("R600_GLSL130", FALSE) ? 130 : 120;
 413
 414         /* Supported except the original R600. */
 415         case PIPE_CAP_INDEP_BLEND_ENABLE:
 416         case PIPE_CAP_INDEP_BLEND_FUNC:
 417                 /* R600 doesn't support per-MRT blends */
 418                 return family == CHIP_R600 ? 0 : 1;
 419
 420         /* Supported on Evergreen. */
 421         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 422                 return family >= CHIP_CEDAR ? 1 : 0;
 423
 424         /* Unsupported features. */
 425         case PIPE_CAP_TGSI_INSTANCEID:
 426         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 427         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 428         case PIPE_CAP_SCALED_RESOLVE:
 429         case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 430         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 431         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 432         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 433                 return 0;
 434
 435         /* Stream output. */
 436         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 437                 return rscreen->info.r600_has_streamout ? 4 : 0;
 438         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 439                 return rscreen->info.r600_has_streamout ? 1 : 0;
 440         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 441         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 442                 return 16*4;
 443
 444         /* Texturing. */
 445         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 446         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 447         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 448                 if (family >= CHIP_CEDAR)
 449                         return 15;
 450                 else
 451                         return 14;
 452         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 453                 return rscreen->info.drm_minor >= 9 ?
 454                         (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
 455         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 456                 return 32;
 457
 458         /* Render targets. */
 459         case PIPE_CAP_MAX_RENDER_TARGETS:
 460                 /* XXX some r6xx are buggy and can only do 4 */
 461                 return 8;
 462
 463         /* Timer queries, present when the clock frequency is non zero. */
 464         case PIPE_CAP_TIMER_QUERY:
 465                 return rscreen->info.r600_clock_crystal_freq != 0;
 466
 467         case PIPE_CAP_MIN_TEXEL_OFFSET:
 468                 return -8;
 469
 470         case PIPE_CAP_MAX_TEXEL_OFFSET:
 471                 return 7;
 472         }
 473         return 0;
 474 }
 475
 476 static float r600_get_paramf(struct pipe_screen* pscreen,
 477                              enum pipe_capf param)
 478 {
 479         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 480         enum radeon_family family = rscreen->family;
 481
 482         switch (param) {
 483         case PIPE_CAPF_MAX_LINE_WIDTH:
 484         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 485         case PIPE_CAPF_MAX_POINT_WIDTH:
 486         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 487                 if (family >= CHIP_CEDAR)
 488                         return 16384.0f;
 489                 else
 490                         return 8192.0f;
 491         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 492                 return 16.0f;
 493         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 494                 return 16.0f;
 495         case PIPE_CAPF_GUARD_BAND_LEFT:
 496         case PIPE_CAPF_GUARD_BAND_TOP:
 497         case PIPE_CAPF_GUARD_BAND_RIGHT:
 498         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 499                 return 0.0f;
 500         }
 501         return 0.0f;
 502 }
 503
 504 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 505 {
 506         switch(shader)
 507         {
 508         case PIPE_SHADER_FRAGMENT:
 509         case PIPE_SHADER_VERTEX:
 510                 break;
 511         case PIPE_SHADER_GEOMETRY:
 512                 /* XXX: support and enable geometry programs */
 513                 return 0;
 514         default:
 515                 /* XXX: support tessellation on Evergreen */
 516                 return 0;
 517         }
 518
 519         /* XXX: all these should be fixed, since r600 surely supports much more! */
 520         switch (param) {
 521         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 522         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 523         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 524         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 525                 return 16384;
 526         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 527                 return 8; /* XXX */
 528         case PIPE_SHADER_CAP_MAX_INPUTS:
 529                 if(shader == PIPE_SHADER_FRAGMENT)
 530                         return 34;
 531                 else
 532                         return 32;
 533         case PIPE_SHADER_CAP_MAX_TEMPS:
 534                 return 256; /* Max native temporaries. */
 535         case PIPE_SHADER_CAP_MAX_ADDRS:
 536                 /* XXX Isn't this equal to TEMPS? */
 537                 return 1; /* Max native address registers */
 538         case PIPE_SHADER_CAP_MAX_CONSTS:
 539                 return R600_MAX_CONST_BUFFER_SIZE;
 540         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 541                 return R600_MAX_CONST_BUFFERS-1;
 542         case PIPE_SHADER_CAP_MAX_PREDS:
 543                 return 0; /* nothing uses this */
 544         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 545                 return 1;
 546         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 547         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 548         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 549         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 550                 return 1;
 551         case PIPE_SHADER_CAP_SUBROUTINES:
 552                 return 0;
 553         case PIPE_SHADER_CAP_INTEGERS:
 554                 return 0;
 555         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 556                 return 16;
 557         }
 558         return 0;
 559 }
 560
 561 static int r600_get_video_param(struct pipe_screen *screen,
 562                                 enum pipe_video_profile profile,
 563                                 enum pipe_video_cap param)
 564 {
 565         switch (param) {
 566         case PIPE_VIDEO_CAP_SUPPORTED:
 567                 return vl_profile_supported(screen, profile);
 568         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 569                 return 1;
 570         case PIPE_VIDEO_CAP_MAX_WIDTH:
 571         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 572                 return vl_video_buffer_max_size(screen);
 573         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 574                 return PIPE_FORMAT_NV12;
 575         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 576                 return false;
 577         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 578                 return false;
 579         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 580                 return true;
 581         default:
 582                 return 0;
 583         }
 584 }
 585
 586 static void r600_destroy_screen(struct pipe_screen* pscreen)
 587 {
 588         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 589
 590         if (rscreen == NULL)
 591                 return;
 592
 593         if (rscreen->fences.bo) {
 594                 struct r600_fence_block *entry, *tmp;
 595
 596                 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
 597                         LIST_DEL(&entry->head);
 598                         FREE(entry);
 599                 }
 600
 601                 rscreen->ws->buffer_unmap(rscreen->fences.bo->buf);
 602                 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
 603         }
 604         pipe_mutex_destroy(rscreen->fences.mutex);
 605
 606         rscreen->ws->destroy(rscreen->ws);
 607
 608         util_slab_destroy(&rscreen->pool_buffers);
 609         pipe_mutex_destroy(rscreen->mutex_num_contexts);
 610         FREE(rscreen);
 611 }
 612
 613 static void r600_fence_reference(struct pipe_screen *pscreen,
 614                                  struct pipe_fence_handle **ptr,
 615                                  struct pipe_fence_handle *fence)
 616 {
 617         struct r600_fence **oldf = (struct r600_fence**)ptr;
 618         struct r600_fence *newf = (struct r600_fence*)fence;
 619
 620         if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
 621                 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 622                 pipe_mutex_lock(rscreen->fences.mutex);
 623                 pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL);
 624                 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
 625                 pipe_mutex_unlock(rscreen->fences.mutex);
 626         }
 627
 628         *ptr = fence;
 629 }
 630
 631 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
 632                                     struct pipe_fence_handle *fence)
 633 {
 634         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 635         struct r600_fence *rfence = (struct r600_fence*)fence;
 636
 637         return rscreen->fences.data[rfence->index];
 638 }
 639
 640 static boolean r600_fence_finish(struct pipe_screen *pscreen,
 641                                  struct pipe_fence_handle *fence,
 642                                  uint64_t timeout)
 643 {
 644         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 645         struct r600_fence *rfence = (struct r600_fence*)fence;
 646         int64_t start_time = 0;
 647         unsigned spins = 0;
 648
 649         if (timeout != PIPE_TIMEOUT_INFINITE) {
 650                 start_time = os_time_get();
 651
 652                 /* Convert to microseconds. */
 653                 timeout /= 1000;
 654         }
 655
 656         while (rscreen->fences.data[rfence->index] == 0) {
 657                 /* Special-case infinite timeout - wait for the dummy BO to become idle */
 658                 if (timeout == PIPE_TIMEOUT_INFINITE) {
 659                         rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
 660                         break;
 661                 }
 662
 663                 /* The dummy BO will be busy until the CS including the fence has completed, or
 664                  * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
 665                 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
 666                         break;
 667
 668                 if (++spins % 256)
 669                         continue;
 670 #ifdef PIPE_OS_UNIX
 671                 sched_yield();
 672 #else
 673                 os_time_sleep(10);
 674 #endif
 675                 if (timeout != PIPE_TIMEOUT_INFINITE &&
 676                     os_time_get() - start_time >= timeout) {
 677                         break;
 678                 }
 679         }
 680
 681         return rscreen->fences.data[rfence->index] != 0;
 682 }
 683
 684 static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 685 {
 686         switch ((tiling_config & 0xe) >> 1) {
 687         case 0:
 688                 rscreen->tiling_info.num_channels = 1;
 689                 break;
 690         case 1:
 691                 rscreen->tiling_info.num_channels = 2;
 692                 break;
 693         case 2:
 694                 rscreen->tiling_info.num_channels = 4;
 695                 break;
 696         case 3:
 697                 rscreen->tiling_info.num_channels = 8;
 698                 break;
 699         default:
 700                 return -EINVAL;
 701         }
 702
 703         switch ((tiling_config & 0x30) >> 4) {
 704         case 0:
 705                 rscreen->tiling_info.num_banks = 4;
 706                 break;
 707         case 1:
 708                 rscreen->tiling_info.num_banks = 8;
 709                 break;
 710         default:
 711                 return -EINVAL;
 712
 713         }
 714         switch ((tiling_config & 0xc0) >> 6) {
 715         case 0:
 716                 rscreen->tiling_info.group_bytes = 256;
 717                 break;
 718         case 1:
 719                 rscreen->tiling_info.group_bytes = 512;
 720                 break;
 721         default:
 722                 return -EINVAL;
 723         }
 724         return 0;
 725 }
 726
 727 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 728 {
 729         switch (tiling_config & 0xf) {
 730         case 0:
 731                 rscreen->tiling_info.num_channels = 1;
 732                 break;
 733         case 1:
 734                 rscreen->tiling_info.num_channels = 2;
 735                 break;
 736         case 2:
 737                 rscreen->tiling_info.num_channels = 4;
 738                 break;
 739         case 3:
 740                 rscreen->tiling_info.num_channels = 8;
 741                 break;
 742         default:
 743                 return -EINVAL;
 744         }
 745
 746         switch ((tiling_config & 0xf0) >> 4) {
 747         case 0:
 748                 rscreen->tiling_info.num_banks = 4;
 749                 break;
 750         case 1:
 751                 rscreen->tiling_info.num_banks = 8;
 752                 break;
 753         case 2:
 754                 rscreen->tiling_info.num_banks = 16;
 755                 break;
 756         default:
 757                 return -EINVAL;
 758         }
 759
 760         switch ((tiling_config & 0xf00) >> 8) {
 761         case 0:
 762                 rscreen->tiling_info.group_bytes = 256;
 763                 break;
 764         case 1:
 765                 rscreen->tiling_info.group_bytes = 512;
 766                 break;
 767         default:
 768                 return -EINVAL;
 769         }
 770         return 0;
 771 }
 772
 773 static int r600_init_tiling(struct r600_screen *rscreen)
 774 {
 775         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 776
 777         /* set default group bytes, overridden by tiling info ioctl */
 778         if (rscreen->chip_class <= R700) {
 779                 rscreen->tiling_info.group_bytes = 256;
 780         } else {
 781                 rscreen->tiling_info.group_bytes = 512;
 782         }
 783
 784         if (!tiling_config)
 785                 return 0;
 786
 787         if (rscreen->chip_class <= R700) {
 788                 return r600_interpret_tiling(rscreen, tiling_config);
 789         } else {
 790                 return evergreen_interpret_tiling(rscreen, tiling_config);
 791         }
 792 }
 793
 794 static unsigned radeon_family_from_device(unsigned device)
 795 {
 796         switch (device) {
 797 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
 798 #include "pci_ids/r600_pci_ids.h"
 799 #undef CHIPSET
 800         default:
 801                 return CHIP_UNKNOWN;
 802         }
 803 }
 804
 805 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 806 {
 807         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 808         if (rscreen == NULL) {
 809                 return NULL;
 810         }
 811
 812         rscreen->ws = ws;
 813         ws->query_info(ws, &rscreen->info);
 814
 815         rscreen->family = radeon_family_from_device(rscreen->info.pci_id);
 816         if (rscreen->family == CHIP_UNKNOWN) {
 817                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
 818                 FREE(rscreen);
 819                 return NULL;
 820         }
 821
 822         /* setup class */
 823         if (rscreen->family == CHIP_CAYMAN) {
 824                 rscreen->chip_class = CAYMAN;
 825         } else if (rscreen->family >= CHIP_CEDAR) {
 826                 rscreen->chip_class = EVERGREEN;
 827         } else if (rscreen->family >= CHIP_RV770) {
 828                 rscreen->chip_class = R700;
 829         } else {
 830                 rscreen->chip_class = R600;
 831         }
 832
 833         if (r600_init_tiling(rscreen)) {
 834                 FREE(rscreen);
 835                 return NULL;
 836         }
 837
 838         rscreen->screen.destroy = r600_destroy_screen;
 839         rscreen->screen.get_name = r600_get_name;
 840         rscreen->screen.get_vendor = r600_get_vendor;
 841         rscreen->screen.get_param = r600_get_param;
 842         rscreen->screen.get_shader_param = r600_get_shader_param;
 843         rscreen->screen.get_paramf = r600_get_paramf;
 844         rscreen->screen.get_video_param = r600_get_video_param;
 845         if (rscreen->chip_class >= EVERGREEN) {
 846                 rscreen->screen.is_format_supported = evergreen_is_format_supported;
 847         } else {
 848                 rscreen->screen.is_format_supported = r600_is_format_supported;
 849         }
 850         rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
 851         rscreen->screen.context_create = r600_create_context;
 852         rscreen->screen.fence_reference = r600_fence_reference;
 853         rscreen->screen.fence_signalled = r600_fence_signalled;
 854         rscreen->screen.fence_finish = r600_fence_finish;
 855         r600_init_screen_resource_functions(&rscreen->screen);
 856
 857         util_format_s3tc_init();
 858
 859         util_slab_create(&rscreen->pool_buffers,
 860                          sizeof(struct r600_resource), 64,
 861                          UTIL_SLAB_SINGLETHREADED);
 862
 863         pipe_mutex_init(rscreen->mutex_num_contexts);
 864
 865         rscreen->fences.bo = NULL;
 866         rscreen->fences.data = NULL;
 867         rscreen->fences.next_index = 0;
 868         LIST_INITHEAD(&rscreen->fences.pool);
 869         LIST_INITHEAD(&rscreen->fences.blocks);
 870         pipe_mutex_init(rscreen->fences.mutex);
 871
 872         rscreen->use_surface_alloc = debug_get_bool_option("R600_SURF", TRUE);
 873
 874         return &rscreen->screen;
 875 }