src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "pipe/p_context.h"
  28 #include "tgsi/tgsi_scan.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "tgsi/tgsi_util.h"
  31 #include "util/u_blitter.h"
  32 #include "util/u_double_list.h"
  33 #include "util/u_format.h"
  34 #include "util/u_format_s3tc.h"
  35 #include "util/u_transfer.h"
  36 #include "util/u_surface.h"
  37 #include "util/u_pack_color.h"
  38 #include "util/u_memory.h"
  39 #include "util/u_inlines.h"
  40 #include "util/u_upload_mgr.h"
  41 #include "vl/vl_decoder.h"
  42 #include "vl/vl_video_buffer.h"
  43 #include "os/os_time.h"
  44 #include "pipebuffer/pb_buffer.h"
  45 #include "r600.h"
  46 #include "r600d.h"
  47 #include "r600_resource.h"
  48 #include "r600_shader.h"
  49 #include "r600_pipe.h"
  50 #include "r600_hw_context_priv.h"
  51
  52 /*
  53  * pipe_context
  54  */
  55 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
  56 {
  57         struct r600_screen *rscreen = rctx->screen;
  58         struct r600_fence *fence = NULL;
  59
  60         pipe_mutex_lock(rscreen->fences.mutex);
  61
  62         if (!rscreen->fences.bo) {
  63                 /* Create the shared buffer object */
  64                 rscreen->fences.bo = (struct r600_resource*)
  65                         pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
  66                                            PIPE_USAGE_STAGING, 4096);
  67                 if (!rscreen->fences.bo) {
  68                         R600_ERR("r600: failed to create bo for fence objects\n");
  69                         goto out;
  70                 }
  71                 rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->buf,
  72                                                            rctx->cs,
  73                                                            PIPE_TRANSFER_READ_WRITE);
  74         }
  75
  76         if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
  77                 struct r600_fence *entry;
  78
  79                 /* Try to find a freed fence that has been signalled */
  80                 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
  81                         if (rscreen->fences.data[entry->index] != 0) {
  82                                 LIST_DELINIT(&entry->head);
  83                                 fence = entry;
  84                                 break;
  85                         }
  86                 }
  87         }
  88
  89         if (!fence) {
  90                 /* Allocate a new fence */
  91                 struct r600_fence_block *block;
  92                 unsigned index;
  93
  94                 if ((rscreen->fences.next_index + 1) >= 1024) {
  95                         R600_ERR("r600: too many concurrent fences\n");
  96                         goto out;
  97                 }
  98
  99                 index = rscreen->fences.next_index++;
 100
 101                 if (!(index % FENCE_BLOCK_SIZE)) {
 102                         /* Allocate a new block */
 103                         block = CALLOC_STRUCT(r600_fence_block);
 104                         if (block == NULL)
 105                                 goto out;
 106
 107                         LIST_ADD(&block->head, &rscreen->fences.blocks);
 108                 } else {
 109                         block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
 110                 }
 111
 112                 fence = &block->fences[index % FENCE_BLOCK_SIZE];
 113                 fence->index = index;
 114         }
 115
 116         pipe_reference_init(&fence->reference, 1);
 117
 118         rscreen->fences.data[fence->index] = 0;
 119         r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
 120
 121         /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
 122         fence->sleep_bo = (struct r600_resource*)
 123                         pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM,
 124                                            PIPE_USAGE_STAGING, 1);
 125         /* Add the fence as a dummy relocation. */
 126         r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE);
 127
 128 out:
 129         pipe_mutex_unlock(rscreen->fences.mutex);
 130         return fence;
 131 }
 132
 133
 134 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 135                 unsigned flags)
 136 {
 137         struct r600_context *rctx = (struct r600_context *)ctx;
 138         struct r600_fence **rfence = (struct r600_fence**)fence;
 139         struct pipe_query *render_cond = NULL;
 140         unsigned render_cond_mode = 0;
 141
 142         if (rfence)
 143                 *rfence = r600_create_fence(rctx);
 144
 145         /* Disable render condition. */
 146         if (rctx->current_render_cond) {
 147                 render_cond = rctx->current_render_cond;
 148                 render_cond_mode = rctx->current_render_cond_mode;
 149                 ctx->render_condition(ctx, NULL, 0);
 150         }
 151
 152         r600_context_flush(rctx, flags);
 153
 154         /* Re-enable render condition. */
 155         if (render_cond) {
 156                 ctx->render_condition(ctx, render_cond, render_cond_mode);
 157         }
 158 }
 159
 160 static void r600_flush_from_st(struct pipe_context *ctx,
 161                                struct pipe_fence_handle **fence)
 162 {
 163         r600_flush(ctx, fence, 0);
 164 }
 165
 166 static void r600_flush_from_winsys(void *ctx, unsigned flags)
 167 {
 168         r600_flush((struct pipe_context*)ctx, NULL, flags);
 169 }
 170
 171 static void r600_update_num_contexts(struct r600_screen *rscreen, int diff)
 172 {
 173         pipe_mutex_lock(rscreen->mutex_num_contexts);
 174         if (diff > 0) {
 175                 rscreen->num_contexts++;
 176
 177                 if (rscreen->num_contexts > 1)
 178                         util_slab_set_thread_safety(&rscreen->pool_buffers,
 179                                                     UTIL_SLAB_MULTITHREADED);
 180         } else {
 181                 rscreen->num_contexts--;
 182
 183                 if (rscreen->num_contexts <= 1)
 184                         util_slab_set_thread_safety(&rscreen->pool_buffers,
 185                                                     UTIL_SLAB_SINGLETHREADED);
 186         }
 187         pipe_mutex_unlock(rscreen->mutex_num_contexts);
 188 }
 189
 190 static void r600_destroy_context(struct pipe_context *context)
 191 {
 192         struct r600_context *rctx = (struct r600_context *)context;
 193
 194         rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
 195         util_unreference_framebuffer_state(&rctx->framebuffer);
 196
 197         r600_context_fini(rctx);
 198
 199         util_blitter_destroy(rctx->blitter);
 200
 201         for (int i = 0; i < R600_PIPE_NSTATES; i++) {
 202                 free(rctx->states[i]);
 203         }
 204
 205         u_vbuf_destroy(rctx->vbuf_mgr);
 206         util_slab_destroy(&rctx->pool_transfers);
 207
 208         r600_update_num_contexts(rctx->screen, -1);
 209
 210         FREE(rctx);
 211 }
 212
 213 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 214 {
 215         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 216         struct r600_screen* rscreen = (struct r600_screen *)screen;
 217
 218         if (rctx == NULL)
 219                 return NULL;
 220
 221         r600_update_num_contexts(rscreen, 1);
 222
 223         rctx->context.screen = screen;
 224         rctx->context.priv = priv;
 225         rctx->context.destroy = r600_destroy_context;
 226         rctx->context.flush = r600_flush_from_st;
 227
 228         /* Easy accessing of screen/winsys. */
 229         rctx->screen = rscreen;
 230         rctx->ws = rscreen->ws;
 231         rctx->family = rscreen->family;
 232         rctx->chip_class = rscreen->chip_class;
 233
 234         r600_init_blit_functions(rctx);
 235         r600_init_query_functions(rctx);
 236         r600_init_context_resource_functions(rctx);
 237         r600_init_surface_functions(rctx);
 238         rctx->context.draw_vbo = r600_draw_vbo;
 239
 240         rctx->context.create_video_decoder = vl_create_decoder;
 241         rctx->context.create_video_buffer = vl_video_buffer_create;
 242
 243         r600_init_common_atoms(rctx);
 244
 245         switch (rctx->chip_class) {
 246         case R600:
 247         case R700:
 248                 r600_init_state_functions(rctx);
 249                 if (r600_context_init(rctx)) {
 250                         r600_destroy_context(&rctx->context);
 251                         return NULL;
 252                 }
 253                 r600_init_config(rctx);
 254                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 255                 break;
 256         case EVERGREEN:
 257         case CAYMAN:
 258                 evergreen_init_state_functions(rctx);
 259                 if (evergreen_context_init(rctx)) {
 260                         r600_destroy_context(&rctx->context);
 261                         return NULL;
 262                 }
 263                 evergreen_init_config(rctx);
 264                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 265                 break;
 266         default:
 267                 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
 268                 r600_destroy_context(&rctx->context);
 269                 return NULL;
 270         }
 271
 272         rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx);
 273
 274         util_slab_create(&rctx->pool_transfers,
 275                          sizeof(struct pipe_transfer), 64,
 276                          UTIL_SLAB_SINGLETHREADED);
 277
 278         rctx->vbuf_mgr = u_vbuf_create(&rctx->context, 1024 * 1024, 256,
 279                                            PIPE_BIND_VERTEX_BUFFER |
 280                                            PIPE_BIND_INDEX_BUFFER |
 281                                            PIPE_BIND_CONSTANT_BUFFER,
 282                                            U_VERTEX_FETCH_DWORD_ALIGNED);
 283         if (!rctx->vbuf_mgr) {
 284                 r600_destroy_context(&rctx->context);
 285                 return NULL;
 286         }
 287         rctx->vbuf_mgr->caps.format_fixed32 = 0;
 288
 289         rctx->blitter = util_blitter_create(&rctx->context);
 290         if (rctx->blitter == NULL) {
 291                 r600_destroy_context(&rctx->context);
 292                 return NULL;
 293         }
 294
 295         LIST_INITHEAD(&rctx->dirty_states);
 296
 297         r600_get_backend_mask(rctx); /* this emits commands and must be last */
 298
 299         return &rctx->context;
 300 }
 301
 302 /*
 303  * pipe_screen
 304  */
 305 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 306 {
 307         return "X.Org";
 308 }
 309
 310 static const char *r600_get_family_name(enum radeon_family family)
 311 {
 312         switch(family) {
 313         case CHIP_R600: return "AMD R600";
 314         case CHIP_RV610: return "AMD RV610";
 315         case CHIP_RV630: return "AMD RV630";
 316         case CHIP_RV670: return "AMD RV670";
 317         case CHIP_RV620: return "AMD RV620";
 318         case CHIP_RV635: return "AMD RV635";
 319         case CHIP_RS780: return "AMD RS780";
 320         case CHIP_RS880: return "AMD RS880";
 321         case CHIP_RV770: return "AMD RV770";
 322         case CHIP_RV730: return "AMD RV730";
 323         case CHIP_RV710: return "AMD RV710";
 324         case CHIP_RV740: return "AMD RV740";
 325         case CHIP_CEDAR: return "AMD CEDAR";
 326         case CHIP_REDWOOD: return "AMD REDWOOD";
 327         case CHIP_JUNIPER: return "AMD JUNIPER";
 328         case CHIP_CYPRESS: return "AMD CYPRESS";
 329         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 330         case CHIP_PALM: return "AMD PALM";
 331         case CHIP_SUMO: return "AMD SUMO";
 332         case CHIP_SUMO2: return "AMD SUMO2";
 333         case CHIP_BARTS: return "AMD BARTS";
 334         case CHIP_TURKS: return "AMD TURKS";
 335         case CHIP_CAICOS: return "AMD CAICOS";
 336         case CHIP_CAYMAN: return "AMD CAYMAN";
 337         default: return "AMD unknown";
 338         }
 339 }
 340
 341 static const char* r600_get_name(struct pipe_screen* pscreen)
 342 {
 343         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 344
 345         return r600_get_family_name(rscreen->family);
 346 }
 347
 348 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 349 {
 350         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 351         enum radeon_family family = rscreen->family;
 352
 353         switch (param) {
 354         /* Supported features (boolean caps). */
 355         case PIPE_CAP_NPOT_TEXTURES:
 356         case PIPE_CAP_TWO_SIDED_STENCIL:
 357         case PIPE_CAP_DUAL_SOURCE_BLEND:
 358         case PIPE_CAP_ANISOTROPIC_FILTER:
 359         case PIPE_CAP_POINT_SPRITE:
 360         case PIPE_CAP_OCCLUSION_QUERY:
 361         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 362         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 363         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 364         case PIPE_CAP_TEXTURE_SWIZZLE:
 365         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 366         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 367         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 368         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 369         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 370         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 371         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 372         case PIPE_CAP_SM3:
 373         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 374         case PIPE_CAP_PRIMITIVE_RESTART:
 375         case PIPE_CAP_CONDITIONAL_RENDER:
 376         case PIPE_CAP_TEXTURE_BARRIER:
 377         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 378         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 379                 return 1;
 380
 381         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 382                 return debug_get_bool_option("R600_GLSL130", FALSE) ? 130 : 120;
 383
 384         /* Supported except the original R600. */
 385         case PIPE_CAP_INDEP_BLEND_ENABLE:
 386         case PIPE_CAP_INDEP_BLEND_FUNC:
 387                 /* R600 doesn't support per-MRT blends */
 388                 return family == CHIP_R600 ? 0 : 1;
 389
 390         /* Supported on Evergreen. */
 391         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 392                 return family >= CHIP_CEDAR ? 1 : 0;
 393
 394         /* Unsupported features. */
 395         case PIPE_CAP_TGSI_INSTANCEID:
 396         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 397         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 398         case PIPE_CAP_SCALED_RESOLVE:
 399         case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 400         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 401         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 402         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 403                 return 0;
 404
 405         /* Stream output. */
 406         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 407                 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 4 : 0;
 408         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 409                 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 1 : 0;
 410         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 411         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 412                 return 16*4;
 413
 414         /* Texturing. */
 415         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 416         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 417         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 418                 if (family >= CHIP_CEDAR)
 419                         return 15;
 420                 else
 421                         return 14;
 422         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 423                 return rscreen->info.drm_minor >= 9 ?
 424                         (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
 425         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 426                 return 32;
 427
 428         /* Render targets. */
 429         case PIPE_CAP_MAX_RENDER_TARGETS:
 430                 /* FIXME some r6xx are buggy and can only do 4 */
 431                 return 8;
 432
 433         /* Timer queries, present when the clock frequency is non zero. */
 434         case PIPE_CAP_TIMER_QUERY:
 435                 return rscreen->info.r600_clock_crystal_freq != 0;
 436
 437         case PIPE_CAP_MIN_TEXEL_OFFSET:
 438                 return -8;
 439
 440         case PIPE_CAP_MAX_TEXEL_OFFSET:
 441                 return 7;
 442         }
 443         return 0;
 444 }
 445
 446 static float r600_get_paramf(struct pipe_screen* pscreen,
 447                              enum pipe_capf param)
 448 {
 449         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 450         enum radeon_family family = rscreen->family;
 451
 452         switch (param) {
 453         case PIPE_CAPF_MAX_LINE_WIDTH:
 454         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 455         case PIPE_CAPF_MAX_POINT_WIDTH:
 456         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 457                 if (family >= CHIP_CEDAR)
 458                         return 16384.0f;
 459                 else
 460                         return 8192.0f;
 461         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 462                 return 16.0f;
 463         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 464                 return 16.0f;
 465         case PIPE_CAPF_GUARD_BAND_LEFT:
 466         case PIPE_CAPF_GUARD_BAND_TOP:
 467         case PIPE_CAPF_GUARD_BAND_RIGHT:
 468         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 469                 return 0.0f;
 470         }
 471         return 0.0f;
 472 }
 473
 474 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 475 {
 476         switch(shader)
 477         {
 478         case PIPE_SHADER_FRAGMENT:
 479         case PIPE_SHADER_VERTEX:
 480                 break;
 481         case PIPE_SHADER_GEOMETRY:
 482                 /* TODO: support and enable geometry programs */
 483                 return 0;
 484         default:
 485                 /* TODO: support tessellation on Evergreen */
 486                 return 0;
 487         }
 488
 489         /* TODO: all these should be fixed, since r600 surely supports much more! */
 490         switch (param) {
 491         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 492         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 493         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 494         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 495                 return 16384;
 496         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 497                 return 8; /* FIXME */
 498         case PIPE_SHADER_CAP_MAX_INPUTS:
 499                 if(shader == PIPE_SHADER_FRAGMENT)
 500                         return 34;
 501                 else
 502                         return 32;
 503         case PIPE_SHADER_CAP_MAX_TEMPS:
 504                 return 256; /* Max native temporaries. */
 505         case PIPE_SHADER_CAP_MAX_ADDRS:
 506                 /* FIXME Isn't this equal to TEMPS? */
 507                 return 1; /* Max native address registers */
 508         case PIPE_SHADER_CAP_MAX_CONSTS:
 509                 return R600_MAX_CONST_BUFFER_SIZE;
 510         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 511                 return R600_MAX_CONST_BUFFERS-1;
 512         case PIPE_SHADER_CAP_MAX_PREDS:
 513                 return 0; /* FIXME */
 514         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 515                 return 1;
 516         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 517         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 518         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 519         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 520                 return 1;
 521         case PIPE_SHADER_CAP_SUBROUTINES:
 522                 return 0;
 523         case PIPE_SHADER_CAP_INTEGERS:
 524                 return 0;
 525         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 526                 return 16;
 527         case PIPE_SHADER_CAP_OUTPUT_READ:
 528                 return 1;
 529         }
 530         return 0;
 531 }
 532
 533 static int r600_get_video_param(struct pipe_screen *screen,
 534                                 enum pipe_video_profile profile,
 535                                 enum pipe_video_cap param)
 536 {
 537         switch (param) {
 538         case PIPE_VIDEO_CAP_SUPPORTED:
 539                 return vl_profile_supported(screen, profile);
 540         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 541                 return 1;
 542         case PIPE_VIDEO_CAP_MAX_WIDTH:
 543         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 544                 return vl_video_buffer_max_size(screen);
 545         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 546                 return PIPE_FORMAT_NV12;
 547         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 548                 return false;
 549         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 550                 return false;
 551         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 552                 return true;
 553         default:
 554                 return 0;
 555         }
 556 }
 557
 558 static void r600_destroy_screen(struct pipe_screen* pscreen)
 559 {
 560         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 561
 562         if (rscreen == NULL)
 563                 return;
 564
 565         if (rscreen->fences.bo) {
 566                 struct r600_fence_block *entry, *tmp;
 567
 568                 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
 569                         LIST_DEL(&entry->head);
 570                         FREE(entry);
 571                 }
 572
 573                 rscreen->ws->buffer_unmap(rscreen->fences.bo->buf);
 574                 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
 575         }
 576         pipe_mutex_destroy(rscreen->fences.mutex);
 577
 578         rscreen->ws->destroy(rscreen->ws);
 579
 580         util_slab_destroy(&rscreen->pool_buffers);
 581         pipe_mutex_destroy(rscreen->mutex_num_contexts);
 582         FREE(rscreen);
 583 }
 584
 585 static void r600_fence_reference(struct pipe_screen *pscreen,
 586                                  struct pipe_fence_handle **ptr,
 587                                  struct pipe_fence_handle *fence)
 588 {
 589         struct r600_fence **oldf = (struct r600_fence**)ptr;
 590         struct r600_fence *newf = (struct r600_fence*)fence;
 591
 592         if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
 593                 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 594                 pipe_mutex_lock(rscreen->fences.mutex);
 595                 pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL);
 596                 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
 597                 pipe_mutex_unlock(rscreen->fences.mutex);
 598         }
 599
 600         *ptr = fence;
 601 }
 602
 603 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
 604                                     struct pipe_fence_handle *fence)
 605 {
 606         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 607         struct r600_fence *rfence = (struct r600_fence*)fence;
 608
 609         return rscreen->fences.data[rfence->index];
 610 }
 611
 612 static boolean r600_fence_finish(struct pipe_screen *pscreen,
 613                                  struct pipe_fence_handle *fence,
 614                                  uint64_t timeout)
 615 {
 616         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 617         struct r600_fence *rfence = (struct r600_fence*)fence;
 618         int64_t start_time = 0;
 619         unsigned spins = 0;
 620
 621         if (timeout != PIPE_TIMEOUT_INFINITE) {
 622                 start_time = os_time_get();
 623
 624                 /* Convert to microseconds. */
 625                 timeout /= 1000;
 626         }
 627
 628         while (rscreen->fences.data[rfence->index] == 0) {
 629                 /* Special-case infinite timeout - wait for the dummy BO to become idle */
 630                 if (timeout == PIPE_TIMEOUT_INFINITE) {
 631                         rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
 632                         break;
 633                 }
 634
 635                 /* The dummy BO will be busy until the CS including the fence has completed, or
 636                  * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
 637                 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
 638                         break;
 639
 640                 if (++spins % 256)
 641                         continue;
 642 #ifdef PIPE_OS_UNIX
 643                 sched_yield();
 644 #else
 645                 os_time_sleep(10);
 646 #endif
 647                 if (timeout != PIPE_TIMEOUT_INFINITE &&
 648                     os_time_get() - start_time >= timeout) {
 649                         break;
 650                 }
 651         }
 652
 653         return rscreen->fences.data[rfence->index] != 0;
 654 }
 655
 656 static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 657 {
 658         switch ((tiling_config & 0xe) >> 1) {
 659         case 0:
 660                 rscreen->tiling_info.num_channels = 1;
 661                 break;
 662         case 1:
 663                 rscreen->tiling_info.num_channels = 2;
 664                 break;
 665         case 2:
 666                 rscreen->tiling_info.num_channels = 4;
 667                 break;
 668         case 3:
 669                 rscreen->tiling_info.num_channels = 8;
 670                 break;
 671         default:
 672                 return -EINVAL;
 673         }
 674
 675         switch ((tiling_config & 0x30) >> 4) {
 676         case 0:
 677                 rscreen->tiling_info.num_banks = 4;
 678                 break;
 679         case 1:
 680                 rscreen->tiling_info.num_banks = 8;
 681                 break;
 682         default:
 683                 return -EINVAL;
 684
 685         }
 686         switch ((tiling_config & 0xc0) >> 6) {
 687         case 0:
 688                 rscreen->tiling_info.group_bytes = 256;
 689                 break;
 690         case 1:
 691                 rscreen->tiling_info.group_bytes = 512;
 692                 break;
 693         default:
 694                 return -EINVAL;
 695         }
 696         return 0;
 697 }
 698
 699 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 700 {
 701         switch (tiling_config & 0xf) {
 702         case 0:
 703                 rscreen->tiling_info.num_channels = 1;
 704                 break;
 705         case 1:
 706                 rscreen->tiling_info.num_channels = 2;
 707                 break;
 708         case 2:
 709                 rscreen->tiling_info.num_channels = 4;
 710                 break;
 711         case 3:
 712                 rscreen->tiling_info.num_channels = 8;
 713                 break;
 714         default:
 715                 return -EINVAL;
 716         }
 717
 718         switch ((tiling_config & 0xf0) >> 4) {
 719         case 0:
 720                 rscreen->tiling_info.num_banks = 4;
 721                 break;
 722         case 1:
 723                 rscreen->tiling_info.num_banks = 8;
 724                 break;
 725         case 2:
 726                 rscreen->tiling_info.num_banks = 16;
 727                 break;
 728         default:
 729                 return -EINVAL;
 730         }
 731
 732         switch ((tiling_config & 0xf00) >> 8) {
 733         case 0:
 734                 rscreen->tiling_info.group_bytes = 256;
 735                 break;
 736         case 1:
 737                 rscreen->tiling_info.group_bytes = 512;
 738                 break;
 739         default:
 740                 return -EINVAL;
 741         }
 742         return 0;
 743 }
 744
 745 static int r600_init_tiling(struct r600_screen *rscreen)
 746 {
 747         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 748
 749         /* set default group bytes, overridden by tiling info ioctl */
 750         if (rscreen->chip_class <= R700) {
 751                 rscreen->tiling_info.group_bytes = 256;
 752         } else {
 753                 rscreen->tiling_info.group_bytes = 512;
 754         }
 755
 756         if (!tiling_config)
 757                 return 0;
 758
 759         if (rscreen->chip_class <= R700) {
 760                 return r600_interpret_tiling(rscreen, tiling_config);
 761         } else {
 762                 return evergreen_interpret_tiling(rscreen, tiling_config);
 763         }
 764 }
 765
 766 static unsigned radeon_family_from_device(unsigned device)
 767 {
 768         switch (device) {
 769 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
 770 #include "pci_ids/r600_pci_ids.h"
 771 #undef CHIPSET
 772         default:
 773                 return CHIP_UNKNOWN;
 774         }
 775 }
 776
 777 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 778 {
 779         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 780         if (rscreen == NULL) {
 781                 return NULL;
 782         }
 783
 784         rscreen->ws = ws;
 785         ws->query_info(ws, &rscreen->info);
 786
 787         rscreen->family = radeon_family_from_device(rscreen->info.pci_id);
 788         if (rscreen->family == CHIP_UNKNOWN) {
 789                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
 790                 FREE(rscreen);
 791                 return NULL;
 792         }
 793
 794         /* setup class */
 795         if (rscreen->family == CHIP_CAYMAN) {
 796                 rscreen->chip_class = CAYMAN;
 797         } else if (rscreen->family >= CHIP_CEDAR) {
 798                 rscreen->chip_class = EVERGREEN;
 799         } else if (rscreen->family >= CHIP_RV770) {
 800                 rscreen->chip_class = R700;
 801         } else {
 802                 rscreen->chip_class = R600;
 803         }
 804
 805         if (r600_init_tiling(rscreen)) {
 806                 FREE(rscreen);
 807                 return NULL;
 808         }
 809
 810         rscreen->screen.destroy = r600_destroy_screen;
 811         rscreen->screen.get_name = r600_get_name;
 812         rscreen->screen.get_vendor = r600_get_vendor;
 813         rscreen->screen.get_param = r600_get_param;
 814         rscreen->screen.get_shader_param = r600_get_shader_param;
 815         rscreen->screen.get_paramf = r600_get_paramf;
 816         rscreen->screen.get_video_param = r600_get_video_param;
 817         if (rscreen->chip_class >= EVERGREEN) {
 818                 rscreen->screen.is_format_supported = evergreen_is_format_supported;
 819         } else {
 820                 rscreen->screen.is_format_supported = r600_is_format_supported;
 821         }
 822         rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
 823         rscreen->screen.context_create = r600_create_context;
 824         rscreen->screen.fence_reference = r600_fence_reference;
 825         rscreen->screen.fence_signalled = r600_fence_signalled;
 826         rscreen->screen.fence_finish = r600_fence_finish;
 827         r600_init_screen_resource_functions(&rscreen->screen);
 828
 829         util_format_s3tc_init();
 830
 831         util_slab_create(&rscreen->pool_buffers,
 832                          sizeof(struct r600_resource), 64,
 833                          UTIL_SLAB_SINGLETHREADED);
 834
 835         pipe_mutex_init(rscreen->mutex_num_contexts);
 836
 837         rscreen->fences.bo = NULL;
 838         rscreen->fences.data = NULL;
 839         rscreen->fences.next_index = 0;
 840         LIST_INITHEAD(&rscreen->fences.pool);
 841         LIST_INITHEAD(&rscreen->fences.blocks);
 842         pipe_mutex_init(rscreen->fences.mutex);
 843
 844         return &rscreen->screen;
 845 }