src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25 #include "r600_isa.h"
  26 #include "evergreen_compute.h"
  27 #include "r600d.h"
  28
  29 #include "sb/sb_public.h"
  30
  31 #include <errno.h>
  32 #include "pipe/p_shader_tokens.h"
  33 #include "util/u_debug.h"
  34 #include "util/u_memory.h"
  35 #include "util/u_simple_shaders.h"
  36 #include "util/u_upload_mgr.h"
  37 #include "util/u_math.h"
  38 #include "vl/vl_decoder.h"
  39 #include "vl/vl_video_buffer.h"
  40 #include "radeon/radeon_video.h"
  41 #include "radeon/radeon_uvd.h"
  42 #include "os/os_time.h"
  43
  44 static const struct debug_named_value r600_debug_options[] = {
  45         /* features */
  46         { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
  47
  48         /* shader backend */
  49         { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
  50         { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
  51         { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
  52         { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
  53         { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
  54         { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
  55         { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
  56         { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
  57
  58         DEBUG_NAMED_VALUE_END /* must be last */
  59 };
  60
  61 /*
  62  * pipe_context
  63  */
  64
  65 static void r600_destroy_context(struct pipe_context *context)
  66 {
  67         struct r600_context *rctx = (struct r600_context *)context;
  68         unsigned sh;
  69
  70         r600_isa_destroy(rctx->isa);
  71
  72         r600_sb_context_destroy(rctx->sb_context);
  73
  74         r600_resource_reference(&rctx->dummy_cmask, NULL);
  75         r600_resource_reference(&rctx->dummy_fmask, NULL);
  76
  77         for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
  78                 rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, NULL);
  79                 free(rctx->driver_consts[sh].constants);
  80         }
  81
  82         if (rctx->fixed_func_tcs_shader)
  83                 rctx->b.b.delete_tcs_state(&rctx->b.b, rctx->fixed_func_tcs_shader);
  84
  85         if (rctx->dummy_pixel_shader) {
  86                 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
  87         }
  88         if (rctx->custom_dsa_flush) {
  89                 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
  90         }
  91         if (rctx->custom_blend_resolve) {
  92                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
  93         }
  94         if (rctx->custom_blend_decompress) {
  95                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
  96         }
  97         if (rctx->custom_blend_fastclear) {
  98                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
  99         }
 100         util_unreference_framebuffer_state(&rctx->framebuffer.state);
 101
 102         if (rctx->blitter) {
 103                 util_blitter_destroy(rctx->blitter);
 104         }
 105         if (rctx->allocator_fetch_shader) {
 106                 u_suballocator_destroy(rctx->allocator_fetch_shader);
 107         }
 108
 109         r600_release_command_buffer(&rctx->start_cs_cmd);
 110
 111         FREE(rctx->start_compute_cs_cmd.buf);
 112
 113         r600_common_context_cleanup(&rctx->b);
 114
 115         r600_resource_reference(&rctx->trace_buf, NULL);
 116         r600_resource_reference(&rctx->last_trace_buf, NULL);
 117         radeon_clear_saved_cs(&rctx->last_gfx);
 118
 119         FREE(rctx);
 120 }
 121
 122 static struct pipe_context *r600_create_context(struct pipe_screen *screen,
 123                                                 void *priv, unsigned flags)
 124 {
 125         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 126         struct r600_screen* rscreen = (struct r600_screen *)screen;
 127         struct radeon_winsys *ws = rscreen->b.ws;
 128
 129         if (!rctx)
 130                 return NULL;
 131
 132         rctx->b.b.screen = screen;
 133         assert(!priv);
 134         rctx->b.b.priv = NULL; /* for threaded_context_unwrap_sync */
 135         rctx->b.b.destroy = r600_destroy_context;
 136         rctx->b.set_atom_dirty = (void *)r600_set_atom_dirty;
 137
 138         if (!r600_common_context_init(&rctx->b, &rscreen->b, flags))
 139                 goto fail;
 140
 141         rctx->screen = rscreen;
 142         LIST_INITHEAD(&rctx->texture_buffers);
 143
 144         r600_init_blit_functions(rctx);
 145
 146         if (rscreen->b.info.has_hw_decode) {
 147                 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
 148                 rctx->b.b.create_video_buffer = r600_video_buffer_create;
 149         } else {
 150                 rctx->b.b.create_video_codec = vl_create_decoder;
 151                 rctx->b.b.create_video_buffer = vl_video_buffer_create;
 152         }
 153
 154         if (getenv("R600_TRACE"))
 155                 rctx->is_debug = true;
 156         r600_init_common_state_functions(rctx);
 157
 158         switch (rctx->b.chip_class) {
 159         case R600:
 160         case R700:
 161                 r600_init_state_functions(rctx);
 162                 r600_init_atom_start_cs(rctx);
 163                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 164                 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
 165                                                                       : r600_create_resolve_blend(rctx);
 166                 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
 167                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
 168                                            rctx->b.family == CHIP_RV620 ||
 169                                            rctx->b.family == CHIP_RS780 ||
 170                                            rctx->b.family == CHIP_RS880 ||
 171                                            rctx->b.family == CHIP_RV710);
 172                 break;
 173         case EVERGREEN:
 174         case CAYMAN:
 175                 evergreen_init_state_functions(rctx);
 176                 evergreen_init_atom_start_cs(rctx);
 177                 evergreen_init_atom_start_compute_cs(rctx);
 178                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 179                 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
 180                 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
 181                 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
 182                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
 183                                            rctx->b.family == CHIP_PALM ||
 184                                            rctx->b.family == CHIP_SUMO ||
 185                                            rctx->b.family == CHIP_SUMO2 ||
 186                                            rctx->b.family == CHIP_CAICOS ||
 187                                            rctx->b.family == CHIP_CAYMAN ||
 188                                            rctx->b.family == CHIP_ARUBA);
 189                 break;
 190         default:
 191                 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
 192                 goto fail;
 193         }
 194
 195         rctx->b.gfx.cs = ws->cs_create(rctx->b.ctx, RING_GFX,
 196                                        r600_context_gfx_flush, rctx);
 197         rctx->b.gfx.flush = r600_context_gfx_flush;
 198
 199         rctx->allocator_fetch_shader =
 200                 u_suballocator_create(&rctx->b.b, 64 * 1024,
 201                                       0, PIPE_USAGE_DEFAULT, 0, FALSE);
 202         if (!rctx->allocator_fetch_shader)
 203                 goto fail;
 204
 205         rctx->isa = calloc(1, sizeof(struct r600_isa));
 206         if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
 207                 goto fail;
 208
 209         if (rscreen->b.debug_flags & DBG_FORCE_DMA)
 210                 rctx->b.b.resource_copy_region = rctx->b.dma_copy;
 211
 212         rctx->blitter = util_blitter_create(&rctx->b.b);
 213         if (rctx->blitter == NULL)
 214                 goto fail;
 215         util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
 216         rctx->blitter->draw_rectangle = r600_draw_rectangle;
 217
 218         r600_begin_new_cs(rctx);
 219
 220         rctx->dummy_pixel_shader =
 221                 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
 222                                                      TGSI_SEMANTIC_GENERIC,
 223                                                      TGSI_INTERPOLATE_CONSTANT);
 224         rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 225
 226         return &rctx->b.b;
 227
 228 fail:
 229         r600_destroy_context(&rctx->b.b);
 230         return NULL;
 231 }
 232
 233 /*
 234  * pipe_screen
 235  */
 236
 237 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 238 {
 239         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 240         enum radeon_family family = rscreen->b.family;
 241
 242         switch (param) {
 243         /* Supported features (boolean caps). */
 244         case PIPE_CAP_NPOT_TEXTURES:
 245         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 246         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 247         case PIPE_CAP_TWO_SIDED_STENCIL:
 248         case PIPE_CAP_ANISOTROPIC_FILTER:
 249         case PIPE_CAP_POINT_SPRITE:
 250         case PIPE_CAP_OCCLUSION_QUERY:
 251         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 252         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 253         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 254         case PIPE_CAP_TEXTURE_SWIZZLE:
 255         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 256         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 257         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 258         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 259         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 260         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 261         case PIPE_CAP_SM3:
 262         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 263         case PIPE_CAP_PRIMITIVE_RESTART:
 264         case PIPE_CAP_CONDITIONAL_RENDER:
 265         case PIPE_CAP_TEXTURE_BARRIER:
 266         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 267         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 268         case PIPE_CAP_TGSI_INSTANCEID:
 269         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 270         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 271         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 272         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 273         case PIPE_CAP_START_INSTANCE:
 274         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 275         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 276         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 277         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 278         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 279         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 280         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 281         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 282         case PIPE_CAP_SAMPLE_SHADING:
 283         case PIPE_CAP_CLIP_HALFZ:
 284         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 285         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 286         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 287         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 288         case PIPE_CAP_TGSI_TXQS:
 289         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 290         case PIPE_CAP_INVALIDATE_BUFFER:
 291         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 292         case PIPE_CAP_QUERY_MEMORY_INFO:
 293         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 294         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 295         case PIPE_CAP_CLEAR_TEXTURE:
 296         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 297         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 298         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 299                 return 1;
 300
 301         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 302                 return rscreen->b.info.drm_major == 2 && rscreen->b.info.drm_minor >= 43;
 303
 304         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 305                 return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;
 306
 307         case PIPE_CAP_COMPUTE:
 308                 return rscreen->b.chip_class > R700;
 309
 310         case PIPE_CAP_TGSI_TEXCOORD:
 311                 return 0;
 312
 313         case PIPE_CAP_FAKE_SW_MSAA:
 314                 return 0;
 315
 316         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 317                 return MIN2(rscreen->b.info.max_alloc_size, INT_MAX);
 318
 319         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 320                 return R600_MAP_BUFFER_ALIGNMENT;
 321
 322         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 323                 return 256;
 324
 325         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 326                 return 1;
 327
 328         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 329                 if (family >= CHIP_CEDAR)
 330                    return 410;
 331                 /* pre-evergreen geom shaders need newer kernel */
 332                 if (rscreen->b.info.drm_minor >= 37)
 333                    return 330;
 334                 return 140;
 335
 336         /* Supported except the original R600. */
 337         case PIPE_CAP_INDEP_BLEND_ENABLE:
 338         case PIPE_CAP_INDEP_BLEND_FUNC:
 339                 /* R600 doesn't support per-MRT blends */
 340                 return family == CHIP_R600 ? 0 : 1;
 341
 342         /* Supported on Evergreen. */
 343         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 344         case PIPE_CAP_CUBE_MAP_ARRAY:
 345         case PIPE_CAP_TEXTURE_GATHER_SM5:
 346         case PIPE_CAP_TEXTURE_QUERY_LOD:
 347         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 348         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 349         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 350                 return family >= CHIP_CEDAR ? 1 : 0;
 351         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 352                 return family >= CHIP_CEDAR ? 4 : 0;
 353         case PIPE_CAP_DRAW_INDIRECT:
 354                 /* kernel command checker support is also required */
 355                 return family >= CHIP_CEDAR && rscreen->b.info.drm_minor >= 41;
 356
 357         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 358                 return family >= CHIP_CEDAR ? 0 : 1;
 359
 360         /* Unsupported features. */
 361         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 362         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 363         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 364         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 365         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 366         case PIPE_CAP_USER_VERTEX_BUFFERS:
 367         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 368         case PIPE_CAP_VERTEXID_NOBASE:
 369         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 370         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 371         case PIPE_CAP_SHAREABLE_SHADERS:
 372         case PIPE_CAP_DRAW_PARAMETERS:
 373         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 374         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 375         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 376         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 377         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 378         case PIPE_CAP_GENERATE_MIPMAP:
 379         case PIPE_CAP_STRING_MARKER:
 380         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 381         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 382         case PIPE_CAP_CULL_DISTANCE:
 383         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 384         case PIPE_CAP_TGSI_VOTE:
 385         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 386         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 387         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 388         case PIPE_CAP_NATIVE_FENCE_FD:
 389         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 390         case PIPE_CAP_TGSI_FS_FBFETCH:
 391         case PIPE_CAP_INT64:
 392         case PIPE_CAP_INT64_DIVMOD:
 393         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 394         case PIPE_CAP_TGSI_CLOCK:
 395         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 396         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 397         case PIPE_CAP_TGSI_BALLOT:
 398         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 399         case PIPE_CAP_POST_DEPTH_COVERAGE:
 400         case PIPE_CAP_BINDLESS_TEXTURE:
 401                 return 0;
 402
 403         case PIPE_CAP_DOUBLES:
 404                 if (rscreen->b.family == CHIP_ARUBA ||
 405                     rscreen->b.family == CHIP_CAYMAN ||
 406                     rscreen->b.family == CHIP_CYPRESS ||
 407                     rscreen->b.family == CHIP_HEMLOCK)
 408                         return 1;
 409                 return 0;
 410
 411         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 412                 if (family >= CHIP_CEDAR)
 413                         return 30;
 414                 else
 415                         return 0;
 416         /* Stream output. */
 417         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 418                 return rscreen->b.has_streamout ? 4 : 0;
 419         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 420         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 421                 return rscreen->b.has_streamout ? 1 : 0;
 422         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 423         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 424                 return 32*4;
 425
 426         /* Geometry shader output. */
 427         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 428                 return 1024;
 429         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 430                 return 16384;
 431         case PIPE_CAP_MAX_VERTEX_STREAMS:
 432                 return family >= CHIP_CEDAR ? 4 : 1;
 433
 434         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 435                 return 2047;
 436
 437         /* Texturing. */
 438         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 439         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 440                 if (family >= CHIP_CEDAR)
 441                         return 15;
 442                 else
 443                         return 14;
 444         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 445                 /* textures support 8192, but layered rendering supports 2048 */
 446                 return 12;
 447         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 448                 /* textures support 8192, but layered rendering supports 2048 */
 449                 return 2048;
 450
 451         /* Render targets. */
 452         case PIPE_CAP_MAX_RENDER_TARGETS:
 453                 /* XXX some r6xx are buggy and can only do 4 */
 454                 return 8;
 455
 456         case PIPE_CAP_MAX_VIEWPORTS:
 457                 return R600_MAX_VIEWPORTS;
 458         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 459                 return 8;
 460
 461         /* Timer queries, present when the clock frequency is non zero. */
 462         case PIPE_CAP_QUERY_TIME_ELAPSED:
 463                 return rscreen->b.info.clock_crystal_freq != 0;
 464         case PIPE_CAP_QUERY_TIMESTAMP:
 465                 return rscreen->b.info.drm_minor >= 20 &&
 466                        rscreen->b.info.clock_crystal_freq != 0;
 467
 468         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 469         case PIPE_CAP_MIN_TEXEL_OFFSET:
 470                 return -8;
 471
 472         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 473         case PIPE_CAP_MAX_TEXEL_OFFSET:
 474                 return 7;
 475
 476         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 477                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 478         case PIPE_CAP_ENDIANNESS:
 479                 return PIPE_ENDIAN_LITTLE;
 480
 481         case PIPE_CAP_VENDOR_ID:
 482                 return ATI_VENDOR_ID;
 483         case PIPE_CAP_DEVICE_ID:
 484                 return rscreen->b.info.pci_id;
 485         case PIPE_CAP_ACCELERATED:
 486                 return 1;
 487         case PIPE_CAP_VIDEO_MEMORY:
 488                 return rscreen->b.info.vram_size >> 20;
 489         case PIPE_CAP_UMA:
 490                 return 0;
 491         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 492                 return rscreen->b.chip_class >= R700;
 493         case PIPE_CAP_PCI_GROUP:
 494                 return rscreen->b.info.pci_domain;
 495         case PIPE_CAP_PCI_BUS:
 496                 return rscreen->b.info.pci_bus;
 497         case PIPE_CAP_PCI_DEVICE:
 498                 return rscreen->b.info.pci_dev;
 499         case PIPE_CAP_PCI_FUNCTION:
 500                 return rscreen->b.info.pci_func;
 501         }
 502         return 0;
 503 }
 504
 505 static int r600_get_shader_param(struct pipe_screen* pscreen,
 506                                  enum pipe_shader_type shader,
 507                                  enum pipe_shader_cap param)
 508 {
 509         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 510
 511         switch(shader)
 512         {
 513         case PIPE_SHADER_FRAGMENT:
 514         case PIPE_SHADER_VERTEX:
 515         case PIPE_SHADER_COMPUTE:
 516                 break;
 517         case PIPE_SHADER_GEOMETRY:
 518                 if (rscreen->b.family >= CHIP_CEDAR)
 519                         break;
 520                 /* pre-evergreen geom shaders need newer kernel */
 521                 if (rscreen->b.info.drm_minor >= 37)
 522                         break;
 523                 return 0;
 524         case PIPE_SHADER_TESS_CTRL:
 525         case PIPE_SHADER_TESS_EVAL:
 526                 if (rscreen->b.family >= CHIP_CEDAR)
 527                         break;
 528         default:
 529                 return 0;
 530         }
 531
 532         switch (param) {
 533         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 534         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 535         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 536         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 537                 return 16384;
 538         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 539                 return 32;
 540         case PIPE_SHADER_CAP_MAX_INPUTS:
 541                 return shader == PIPE_SHADER_VERTEX ? 16 : 32;
 542         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 543                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 544         case PIPE_SHADER_CAP_MAX_TEMPS:
 545                 return 256; /* Max native temporaries. */
 546         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 547                 if (shader == PIPE_SHADER_COMPUTE) {
 548                         uint64_t max_const_buffer_size;
 549                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 550                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 551                                 &max_const_buffer_size);
 552                         return MIN2(max_const_buffer_size, INT_MAX);
 553
 554                 } else {
 555                         return R600_MAX_CONST_BUFFER_SIZE;
 556                 }
 557         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 558                 return R600_MAX_USER_CONST_BUFFERS;
 559         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 560                 return 1;
 561         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 562                 return 1;
 563         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 564         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 565         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 566         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 567                 return 1;
 568         case PIPE_SHADER_CAP_SUBROUTINES:
 569                 return 0;
 570         case PIPE_SHADER_CAP_INTEGERS:
 571         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 572                 return 1;
 573         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 574         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 575                 return 16;
 576         case PIPE_SHADER_CAP_PREFERRED_IR:
 577                 if (shader == PIPE_SHADER_COMPUTE) {
 578                         return PIPE_SHADER_IR_NATIVE;
 579                 } else {
 580                         return PIPE_SHADER_IR_TGSI;
 581                 }
 582         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 583                 return 0;
 584         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 585                 if (rscreen->b.family == CHIP_ARUBA ||
 586                     rscreen->b.family == CHIP_CAYMAN ||
 587                     rscreen->b.family == CHIP_CYPRESS ||
 588                     rscreen->b.family == CHIP_HEMLOCK)
 589                         return 1;
 590                 return 0;
 591         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 592         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 593         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 594         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 595         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 596         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 597                 return 0;
 598         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 599                 /* due to a bug in the shader compiler, some loops hang
 600                  * if they are not unrolled, see:
 601                  *    https://bugs.freedesktop.org/show_bug.cgi?id=86720
 602                  */
 603                 return 255;
 604         }
 605         return 0;
 606 }
 607
 608 static void r600_destroy_screen(struct pipe_screen* pscreen)
 609 {
 610         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 611
 612         if (!rscreen)
 613                 return;
 614
 615         if (!rscreen->b.ws->unref(rscreen->b.ws))
 616                 return;
 617
 618         if (rscreen->global_pool) {
 619                 compute_memory_pool_delete(rscreen->global_pool);
 620         }
 621
 622         r600_destroy_common_screen(&rscreen->b);
 623 }
 624
 625 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
 626                                                   const struct pipe_resource *templ)
 627 {
 628         if (templ->target == PIPE_BUFFER &&
 629             (templ->bind & PIPE_BIND_GLOBAL))
 630                 return r600_compute_global_buffer_create(screen, templ);
 631
 632         return r600_resource_create_common(screen, templ);
 633 }
 634
 635 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws, unsigned flags)
 636 {
 637         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 638
 639         if (!rscreen) {
 640                 return NULL;
 641         }
 642
 643         /* Set functions first. */
 644         rscreen->b.b.context_create = r600_create_context;
 645         rscreen->b.b.destroy = r600_destroy_screen;
 646         rscreen->b.b.get_param = r600_get_param;
 647         rscreen->b.b.get_shader_param = r600_get_shader_param;
 648         rscreen->b.b.resource_create = r600_resource_create;
 649
 650         if (!r600_common_screen_init(&rscreen->b, ws, flags)) {
 651                 FREE(rscreen);
 652                 return NULL;
 653         }
 654
 655         if (rscreen->b.info.chip_class >= EVERGREEN) {
 656                 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
 657         } else {
 658                 rscreen->b.b.is_format_supported = r600_is_format_supported;
 659         }
 660
 661         rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
 662         if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
 663                 rscreen->b.debug_flags |= DBG_COMPUTE;
 664         if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
 665                 rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS | DBG_TCS | DBG_TES;
 666         if (!debug_get_bool_option("R600_HYPERZ", TRUE))
 667                 rscreen->b.debug_flags |= DBG_NO_HYPERZ;
 668
 669         if (rscreen->b.family == CHIP_UNKNOWN) {
 670                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
 671                 FREE(rscreen);
 672                 return NULL;
 673         }
 674
 675         /* Figure out streamout kernel support. */
 676         switch (rscreen->b.chip_class) {
 677         case R600:
 678                 if (rscreen->b.family < CHIP_RS780) {
 679                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 680                 } else {
 681                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
 682                 }
 683                 break;
 684         case R700:
 685                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
 686                 break;
 687         case EVERGREEN:
 688         case CAYMAN:
 689                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 690                 break;
 691         default:
 692                 rscreen->b.has_streamout = FALSE;
 693                 break;
 694         }
 695
 696         /* MSAA support. */
 697         switch (rscreen->b.chip_class) {
 698         case R600:
 699         case R700:
 700                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
 701                 rscreen->has_compressed_msaa_texturing = false;
 702                 break;
 703         case EVERGREEN:
 704                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 705                 rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
 706                 break;
 707         case CAYMAN:
 708                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 709                 rscreen->has_compressed_msaa_texturing = true;
 710                 break;
 711         default:
 712                 rscreen->has_msaa = FALSE;
 713                 rscreen->has_compressed_msaa_texturing = false;
 714         }
 715
 716         rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
 717                               !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
 718
 719         rscreen->b.barrier_flags.cp_to_L2 =
 720                 R600_CONTEXT_INV_VERTEX_CACHE |
 721                 R600_CONTEXT_INV_TEX_CACHE |
 722                 R600_CONTEXT_INV_CONST_CACHE;
 723         rscreen->b.barrier_flags.compute_to_L2 = R600_CONTEXT_PS_PARTIAL_FLUSH;
 724
 725         rscreen->global_pool = compute_memory_pool_new(rscreen);
 726
 727         /* Create the auxiliary context. This must be done last. */
 728         rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL, 0);
 729
 730 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
 731         struct pipe_resource templ = {};
 732
 733         templ.width0 = 4;
 734         templ.height0 = 2048;
 735         templ.depth0 = 1;
 736         templ.array_size = 1;
 737         templ.target = PIPE_TEXTURE_2D;
 738         templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
 739         templ.usage = PIPE_USAGE_DEFAULT;
 740
 741         struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
 742         unsigned char *map = ws->buffer_map(res->buf, NULL, PIPE_TRANSFER_WRITE);
 743
 744         memset(map, 0, 256);
 745
 746         r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
 747         r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
 748         r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
 749         r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
 750         r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
 751
 752         ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
 753
 754         int i;
 755         for (i = 0; i < 256; i++) {
 756                 printf("%02X", map[i]);
 757                 if (i % 16 == 15)
 758                         printf("\n");
 759         }
 760 #endif
 761
 762         if (rscreen->b.debug_flags & DBG_TEST_DMA)
 763                 r600_test_dma(&rscreen->b);
 764
 765         r600_query_fix_enabled_rb_mask(&rscreen->b);
 766         return &rscreen->b.b;
 767 }