src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include <pipe/p_defines.h>
  26 #include <pipe/p_state.h>
  27 #include <pipe/p_context.h>
  28 #include <tgsi/tgsi_scan.h>
  29 #include <tgsi/tgsi_parse.h>
  30 #include <tgsi/tgsi_util.h>
  31 #include <util/u_blitter.h>
  32 #include <util/u_double_list.h>
  33 #include "util/u_format.h"
  34 #include <util/u_format_s3tc.h>
  35 #include <util/u_transfer.h>
  36 #include <util/u_surface.h>
  37 #include <util/u_pack_color.h>
  38 #include <util/u_memory.h>
  39 #include <util/u_inlines.h>
  40 #include "util/u_upload_mgr.h"
  41 #include "os/os_time.h"
  42 #include <pipebuffer/pb_buffer.h>
  43 #include "r600.h"
  44 #include "r600d.h"
  45 #include "r600_resource.h"
  46 #include "r600_shader.h"
  47 #include "r600_pipe.h"
  48
  49 /*
  50  * pipe_context
  51  */
  52 static struct r600_fence *r600_create_fence(struct r600_pipe_context *ctx)
  53 {
  54         struct r600_fence *fence = NULL;
  55
  56         if (!ctx->fences.bo) {
  57                 /* Create the shared buffer object */
  58                 ctx->fences.bo = r600_bo(ctx->radeon, 4096, 0, 0, 0);
  59                 if (!ctx->fences.bo) {
  60                         R600_ERR("r600: failed to create bo for fence objects\n");
  61                         return NULL;
  62                 }
  63                 ctx->fences.data = r600_bo_map(ctx->radeon, ctx->fences.bo, PB_USAGE_UNSYNCHRONIZED, NULL);
  64         }
  65
  66         if (!LIST_IS_EMPTY(&ctx->fences.pool)) {
  67                 struct r600_fence *entry;
  68
  69                 /* Try to find a freed fence that has been signalled */
  70                 LIST_FOR_EACH_ENTRY(entry, &ctx->fences.pool, head) {
  71                         if (ctx->fences.data[entry->index] != 0) {
  72                                 LIST_DELINIT(&entry->head);
  73                                 fence = entry;
  74                                 break;
  75                         }
  76                 }
  77         }
  78
  79         if (!fence) {
  80                 /* Allocate a new fence */
  81                 struct r600_fence_block *block;
  82                 unsigned index;
  83
  84                 if ((ctx->fences.next_index + 1) >= 1024) {
  85                         R600_ERR("r600: too many concurrent fences\n");
  86                         return NULL;
  87                 }
  88
  89                 index = ctx->fences.next_index++;
  90
  91                 if (!(index % FENCE_BLOCK_SIZE)) {
  92                         /* Allocate a new block */
  93                         block = CALLOC_STRUCT(r600_fence_block);
  94                         if (block == NULL)
  95                                 return NULL;
  96
  97                         LIST_ADD(&block->head, &ctx->fences.blocks);
  98                 } else {
  99                         block = LIST_ENTRY(struct r600_fence_block, ctx->fences.blocks.next, head);
 100                 }
 101
 102                 fence = &block->fences[index % FENCE_BLOCK_SIZE];
 103                 fence->ctx = ctx;
 104                 fence->index = index;
 105         }
 106
 107         pipe_reference_init(&fence->reference, 1);
 108
 109         ctx->fences.data[fence->index] = 0;
 110         r600_context_emit_fence(&ctx->ctx, ctx->fences.bo, fence->index, 1);
 111         return fence;
 112 }
 113
 114 static void r600_flush(struct pipe_context *ctx,
 115                         struct pipe_fence_handle **fence)
 116 {
 117         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 118         struct r600_fence **rfence = (struct r600_fence**)fence;
 119
 120 #if 0
 121         static int dc = 0;
 122         char dname[256];
 123 #endif
 124
 125         if (rfence)
 126                 *rfence = r600_create_fence(rctx);
 127
 128 #if 0
 129         sprintf(dname, "gallium-%08d.bof", dc);
 130         if (dc < 20) {
 131                 r600_context_dump_bof(&rctx->ctx, dname);
 132                 R600_ERR("dumped %s\n", dname);
 133         }
 134         dc++;
 135 #endif
 136         r600_context_flush(&rctx->ctx);
 137 }
 138
 139 static void r600_update_num_contexts(struct r600_screen *rscreen, int diff)
 140 {
 141         pipe_mutex_lock(rscreen->mutex_num_contexts);
 142         if (diff > 0) {
 143                 rscreen->num_contexts++;
 144
 145                 if (rscreen->num_contexts > 1)
 146                         util_slab_set_thread_safety(&rscreen->pool_buffers,
 147                                                     UTIL_SLAB_MULTITHREADED);
 148         } else {
 149                 rscreen->num_contexts--;
 150
 151                 if (rscreen->num_contexts <= 1)
 152                         util_slab_set_thread_safety(&rscreen->pool_buffers,
 153                                                     UTIL_SLAB_SINGLETHREADED);
 154         }
 155         pipe_mutex_unlock(rscreen->mutex_num_contexts);
 156 }
 157
 158 static void r600_destroy_context(struct pipe_context *context)
 159 {
 160         struct r600_pipe_context *rctx = (struct r600_pipe_context *)context;
 161
 162         rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
 163         util_unreference_framebuffer_state(&rctx->framebuffer);
 164
 165         r600_context_fini(&rctx->ctx);
 166
 167         util_blitter_destroy(rctx->blitter);
 168
 169         for (int i = 0; i < R600_PIPE_NSTATES; i++) {
 170                 free(rctx->states[i]);
 171         }
 172
 173         u_vbuf_mgr_destroy(rctx->vbuf_mgr);
 174         util_slab_destroy(&rctx->pool_transfers);
 175
 176         if (rctx->fences.bo) {
 177                 struct r600_fence_block *entry, *tmp;
 178
 179                 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rctx->fences.blocks, head) {
 180                         LIST_DEL(&entry->head);
 181                         FREE(entry);
 182                 }
 183
 184                 r600_bo_unmap(rctx->radeon, rctx->fences.bo);
 185                 r600_bo_reference(rctx->radeon, &rctx->fences.bo, NULL);
 186         }
 187
 188         r600_update_num_contexts(rctx->screen, -1);
 189
 190         FREE(rctx);
 191 }
 192
 193 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 194 {
 195         struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context);
 196         struct r600_screen* rscreen = (struct r600_screen *)screen;
 197
 198         if (rctx == NULL)
 199                 return NULL;
 200
 201         r600_update_num_contexts(rscreen, 1);
 202
 203         rctx->context.winsys = rscreen->screen.winsys;
 204         rctx->context.screen = screen;
 205         rctx->context.priv = priv;
 206         rctx->context.destroy = r600_destroy_context;
 207         rctx->context.flush = r600_flush;
 208
 209         /* Easy accessing of screen/winsys. */
 210         rctx->screen = rscreen;
 211         rctx->radeon = rscreen->radeon;
 212         rctx->family = r600_get_family(rctx->radeon);
 213         rctx->chip_class = r600_get_family_class(rctx->radeon);
 214
 215         rctx->fences.bo = NULL;
 216         rctx->fences.data = NULL;
 217         rctx->fences.next_index = 0;
 218         LIST_INITHEAD(&rctx->fences.pool);
 219         LIST_INITHEAD(&rctx->fences.blocks);
 220
 221         r600_init_blit_functions(rctx);
 222         r600_init_query_functions(rctx);
 223         r600_init_context_resource_functions(rctx);
 224         r600_init_surface_functions(rctx);
 225         rctx->context.draw_vbo = r600_draw_vbo;
 226
 227         switch (rctx->chip_class) {
 228         case R600:
 229         case R700:
 230                 r600_init_state_functions(rctx);
 231                 if (r600_context_init(&rctx->ctx, rctx->radeon)) {
 232                         r600_destroy_context(&rctx->context);
 233                         return NULL;
 234                 }
 235                 r600_init_config(rctx);
 236                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 237                 break;
 238         case EVERGREEN:
 239         case CAYMAN:
 240                 evergreen_init_state_functions(rctx);
 241                 if (evergreen_context_init(&rctx->ctx, rctx->radeon)) {
 242                         r600_destroy_context(&rctx->context);
 243                         return NULL;
 244                 }
 245                 evergreen_init_config(rctx);
 246                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 247                 break;
 248         default:
 249                 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
 250                 r600_destroy_context(&rctx->context);
 251                 return NULL;
 252         }
 253
 254         util_slab_create(&rctx->pool_transfers,
 255                          sizeof(struct pipe_transfer), 64,
 256                          UTIL_SLAB_SINGLETHREADED);
 257
 258         rctx->vbuf_mgr = u_vbuf_mgr_create(&rctx->context, 1024 * 1024, 256,
 259                                            PIPE_BIND_VERTEX_BUFFER |
 260                                            PIPE_BIND_INDEX_BUFFER |
 261                                            PIPE_BIND_CONSTANT_BUFFER,
 262                                            U_VERTEX_FETCH_DWORD_ALIGNED);
 263         if (!rctx->vbuf_mgr) {
 264                 r600_destroy_context(&rctx->context);
 265                 return NULL;
 266         }
 267
 268         rctx->blitter = util_blitter_create(&rctx->context);
 269         if (rctx->blitter == NULL) {
 270                 r600_destroy_context(&rctx->context);
 271                 return NULL;
 272         }
 273
 274         return &rctx->context;
 275 }
 276
 277 /*
 278  * pipe_screen
 279  */
 280 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 281 {
 282         return "X.Org";
 283 }
 284
 285 static const char *r600_get_family_name(enum radeon_family family)
 286 {
 287         switch(family) {
 288         case CHIP_R600: return "AMD R600";
 289         case CHIP_RV610: return "AMD RV610";
 290         case CHIP_RV630: return "AMD RV630";
 291         case CHIP_RV670: return "AMD RV670";
 292         case CHIP_RV620: return "AMD RV620";
 293         case CHIP_RV635: return "AMD RV635";
 294         case CHIP_RS780: return "AMD RS780";
 295         case CHIP_RS880: return "AMD RS880";
 296         case CHIP_RV770: return "AMD RV770";
 297         case CHIP_RV730: return "AMD RV730";
 298         case CHIP_RV710: return "AMD RV710";
 299         case CHIP_RV740: return "AMD RV740";
 300         case CHIP_CEDAR: return "AMD CEDAR";
 301         case CHIP_REDWOOD: return "AMD REDWOOD";
 302         case CHIP_JUNIPER: return "AMD JUNIPER";
 303         case CHIP_CYPRESS: return "AMD CYPRESS";
 304         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 305         case CHIP_PALM: return "AMD PALM";
 306         case CHIP_SUMO: return "AMD SUMO";
 307         case CHIP_SUMO2: return "AMD SUMO2";
 308         case CHIP_BARTS: return "AMD BARTS";
 309         case CHIP_TURKS: return "AMD TURKS";
 310         case CHIP_CAICOS: return "AMD CAICOS";
 311         case CHIP_CAYMAN: return "AMD CAYMAN";
 312         default: return "AMD unknown";
 313         }
 314 }
 315
 316 static const char* r600_get_name(struct pipe_screen* pscreen)
 317 {
 318         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 319         enum radeon_family family = r600_get_family(rscreen->radeon);
 320
 321         return r600_get_family_name(family);
 322 }
 323
 324 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 325 {
 326         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 327         enum radeon_family family = r600_get_family(rscreen->radeon);
 328
 329         switch (param) {
 330         /* Supported features (boolean caps). */
 331         case PIPE_CAP_NPOT_TEXTURES:
 332         case PIPE_CAP_TWO_SIDED_STENCIL:
 333         case PIPE_CAP_GLSL:
 334         case PIPE_CAP_DUAL_SOURCE_BLEND:
 335         case PIPE_CAP_ANISOTROPIC_FILTER:
 336         case PIPE_CAP_POINT_SPRITE:
 337         case PIPE_CAP_OCCLUSION_QUERY:
 338         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 339         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 340         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
 341         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 342         case PIPE_CAP_TEXTURE_SWIZZLE:
 343         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 344         case PIPE_CAP_DEPTH_CLAMP:
 345         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 346         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 347         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 348         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 349         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 350         case PIPE_CAP_SM3:
 351         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 352         case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
 353                 return 1;
 354
 355         /* Supported except the original R600. */
 356         case PIPE_CAP_INDEP_BLEND_ENABLE:
 357         case PIPE_CAP_INDEP_BLEND_FUNC:
 358                 /* R600 doesn't support per-MRT blends */
 359                 return family == CHIP_R600 ? 0 : 1;
 360
 361         /* Supported on Evergreen. */
 362         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 363                 return family >= CHIP_CEDAR ? 1 : 0;
 364
 365         /* Unsupported features. */
 366         case PIPE_CAP_STREAM_OUTPUT:
 367         case PIPE_CAP_PRIMITIVE_RESTART:
 368         case PIPE_CAP_TGSI_INSTANCEID:
 369         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 370         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 371                 return 0;
 372
 373         case PIPE_CAP_ARRAY_TEXTURES:
 374                 /* fix once the CS checker upstream is fixed */
 375                 return debug_get_bool_option("R600_ARRAY_TEXTURE", FALSE);
 376
 377         /* Texturing. */
 378         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 379         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 380         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 381                 if (family >= CHIP_CEDAR)
 382                         return 15;
 383                 else
 384                         return 14;
 385         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
 386         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
 387                 return 16;
 388         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 389                 return 32;
 390
 391         /* Render targets. */
 392         case PIPE_CAP_MAX_RENDER_TARGETS:
 393                 /* FIXME some r6xx are buggy and can only do 4 */
 394                 return 8;
 395
 396         /* Timer queries, present when the clock frequency is non zero. */
 397         case PIPE_CAP_TIMER_QUERY:
 398                 return r600_get_clock_crystal_freq(rscreen->radeon) != 0;
 399
 400         default:
 401                 R600_ERR("r600: unknown param %d\n", param);
 402                 return 0;
 403         }
 404 }
 405
 406 static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
 407 {
 408         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 409         enum radeon_family family = r600_get_family(rscreen->radeon);
 410
 411         switch (param) {
 412         case PIPE_CAP_MAX_LINE_WIDTH:
 413         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 414         case PIPE_CAP_MAX_POINT_WIDTH:
 415         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 416                 if (family >= CHIP_CEDAR)
 417                         return 16384.0f;
 418                 else
 419                         return 8192.0f;
 420         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 421                 return 16.0f;
 422         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 423                 return 16.0f;
 424         default:
 425                 R600_ERR("r600: unsupported paramf %d\n", param);
 426                 return 0.0f;
 427         }
 428 }
 429
 430 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 431 {
 432         switch(shader)
 433         {
 434         case PIPE_SHADER_FRAGMENT:
 435         case PIPE_SHADER_VERTEX:
 436                 break;
 437         case PIPE_SHADER_GEOMETRY:
 438                 /* TODO: support and enable geometry programs */
 439                 return 0;
 440         default:
 441                 /* TODO: support tessellation on Evergreen */
 442                 return 0;
 443         }
 444
 445         /* TODO: all these should be fixed, since r600 surely supports much more! */
 446         switch (param) {
 447         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 448         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 449         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 450         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 451                 return 16384;
 452         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 453                 return 8; /* FIXME */
 454         case PIPE_SHADER_CAP_MAX_INPUTS:
 455                 if(shader == PIPE_SHADER_FRAGMENT)
 456                         return 34;
 457                 else
 458                         return 32;
 459         case PIPE_SHADER_CAP_MAX_TEMPS:
 460                 return 256; /* Max native temporaries. */
 461         case PIPE_SHADER_CAP_MAX_ADDRS:
 462                 /* FIXME Isn't this equal to TEMPS? */
 463                 return 1; /* Max native address registers */
 464         case PIPE_SHADER_CAP_MAX_CONSTS:
 465                 return R600_MAX_CONST_BUFFER_SIZE;
 466         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 467                 return R600_MAX_CONST_BUFFERS;
 468         case PIPE_SHADER_CAP_MAX_PREDS:
 469                 return 0; /* FIXME */
 470         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 471                 return 1;
 472         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 473         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 474         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 475         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 476                 return 1;
 477         case PIPE_SHADER_CAP_SUBROUTINES:
 478                 return 0;
 479         default:
 480                 return 0;
 481         }
 482 }
 483
 484 static void r600_destroy_screen(struct pipe_screen* pscreen)
 485 {
 486         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 487
 488         if (rscreen == NULL)
 489                 return;
 490
 491         radeon_decref(rscreen->radeon);
 492
 493         util_slab_destroy(&rscreen->pool_buffers);
 494         pipe_mutex_destroy(rscreen->mutex_num_contexts);
 495         FREE(rscreen);
 496 }
 497
 498 static void r600_fence_reference(struct pipe_screen *pscreen,
 499                                  struct pipe_fence_handle **ptr,
 500                                  struct pipe_fence_handle *fence)
 501 {
 502         struct r600_fence **oldf = (struct r600_fence**)ptr;
 503         struct r600_fence *newf = (struct r600_fence*)fence;
 504
 505         if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
 506                 struct r600_pipe_context *ctx = (*oldf)->ctx;
 507                 LIST_ADDTAIL(&(*oldf)->head, &ctx->fences.pool);
 508         }
 509
 510         *ptr = fence;
 511 }
 512
 513 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
 514                                     struct pipe_fence_handle *fence)
 515 {
 516         struct r600_fence *rfence = (struct r600_fence*)fence;
 517         struct r600_pipe_context *ctx = rfence->ctx;
 518
 519         return ctx->fences.data[rfence->index];
 520 }
 521
 522 static boolean r600_fence_finish(struct pipe_screen *pscreen,
 523                                  struct pipe_fence_handle *fence,
 524                                  uint64_t timeout)
 525 {
 526         struct r600_fence *rfence = (struct r600_fence*)fence;
 527         struct r600_pipe_context *ctx = rfence->ctx;
 528         int64_t start_time = 0;
 529         unsigned spins = 0;
 530
 531         if (timeout != PIPE_TIMEOUT_INFINITE) {
 532                 start_time = os_time_get();
 533
 534                 /* Convert to microseconds. */
 535                 timeout /= 1000;
 536         }
 537
 538         while (ctx->fences.data[rfence->index] == 0) {
 539                 if (++spins % 256)
 540                         continue;
 541 #ifdef PIPE_OS_UNIX
 542                 sched_yield();
 543 #else
 544                 os_time_sleep(10);
 545 #endif
 546                 if (timeout != PIPE_TIMEOUT_INFINITE &&
 547                     os_time_get() - start_time >= timeout) {
 548                         return FALSE;
 549                 }
 550         }
 551
 552         return TRUE;
 553 }
 554
 555 struct pipe_screen *r600_screen_create(struct radeon *radeon)
 556 {
 557         struct r600_screen *rscreen;
 558
 559         rscreen = CALLOC_STRUCT(r600_screen);
 560         if (rscreen == NULL) {
 561                 return NULL;
 562         }
 563
 564         rscreen->radeon = radeon;
 565         rscreen->screen.winsys = (struct pipe_winsys*)radeon;
 566         rscreen->screen.destroy = r600_destroy_screen;
 567         rscreen->screen.get_name = r600_get_name;
 568         rscreen->screen.get_vendor = r600_get_vendor;
 569         rscreen->screen.get_param = r600_get_param;
 570         rscreen->screen.get_shader_param = r600_get_shader_param;
 571         rscreen->screen.get_paramf = r600_get_paramf;
 572         if (r600_get_family_class(radeon) >= EVERGREEN) {
 573                 rscreen->screen.is_format_supported = evergreen_is_format_supported;
 574         } else {
 575                 rscreen->screen.is_format_supported = r600_is_format_supported;
 576         }
 577         rscreen->screen.context_create = r600_create_context;
 578         rscreen->screen.fence_reference = r600_fence_reference;
 579         rscreen->screen.fence_signalled = r600_fence_signalled;
 580         rscreen->screen.fence_finish = r600_fence_finish;
 581         r600_init_screen_resource_functions(&rscreen->screen);
 582
 583         rscreen->tiling_info = r600_get_tiling_info(radeon);
 584         util_format_s3tc_init();
 585
 586         util_slab_create(&rscreen->pool_buffers,
 587                          sizeof(struct r600_resource_buffer), 64,
 588                          UTIL_SLAB_SINGLETHREADED);
 589
 590         pipe_mutex_init(rscreen->mutex_num_contexts);
 591
 592         return &rscreen->screen;
 593 }