gallium: include u_format.h for util_format_is_supported
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include <stdio.h>
24 #include <errno.h>
25 #include <pipe/p_defines.h>
26 #include <pipe/p_state.h>
27 #include <pipe/p_context.h>
28 #include <tgsi/tgsi_scan.h>
29 #include <tgsi/tgsi_parse.h>
30 #include <tgsi/tgsi_util.h>
31 #include <util/u_blitter.h>
32 #include <util/u_double_list.h>
33 #include "util/u_format.h"
34 #include <util/u_format_s3tc.h>
35 #include <util/u_transfer.h>
36 #include <util/u_surface.h>
37 #include <util/u_pack_color.h>
38 #include <util/u_memory.h>
39 #include <util/u_inlines.h>
40 #include "util/u_upload_mgr.h"
41 #include "os/os_time.h"
42 #include <pipebuffer/pb_buffer.h>
43 #include "r600.h"
44 #include "r600d.h"
45 #include "r600_resource.h"
46 #include "r600_shader.h"
47 #include "r600_pipe.h"
48 #include "r600_state_inlines.h"
49
50 /*
51 * pipe_context
52 */
53 static struct r600_fence *r600_create_fence(struct r600_pipe_context *ctx)
54 {
55 struct r600_fence *fence = NULL;
56
57 if (!ctx->fences.bo) {
58 /* Create the shared buffer object */
59 ctx->fences.bo = r600_bo(ctx->radeon, 4096, 0, 0, 0);
60 if (!ctx->fences.bo) {
61 R600_ERR("r600: failed to create bo for fence objects\n");
62 return NULL;
63 }
64 ctx->fences.data = r600_bo_map(ctx->radeon, ctx->fences.bo, PB_USAGE_UNSYNCHRONIZED, NULL);
65 }
66
67 if (!LIST_IS_EMPTY(&ctx->fences.pool)) {
68 struct r600_fence *entry;
69
70 /* Try to find a freed fence that has been signalled */
71 LIST_FOR_EACH_ENTRY(entry, &ctx->fences.pool, head) {
72 if (ctx->fences.data[entry->index] != 0) {
73 LIST_DELINIT(&entry->head);
74 fence = entry;
75 break;
76 }
77 }
78 }
79
80 if (!fence) {
81 /* Allocate a new fence */
82 struct r600_fence_block *block;
83 unsigned index;
84
85 if ((ctx->fences.next_index + 1) >= 1024) {
86 R600_ERR("r600: too many concurrent fences\n");
87 return NULL;
88 }
89
90 index = ctx->fences.next_index++;
91
92 if (!(index % FENCE_BLOCK_SIZE)) {
93 /* Allocate a new block */
94 block = CALLOC_STRUCT(r600_fence_block);
95 if (block == NULL)
96 return NULL;
97
98 LIST_ADD(&block->head, &ctx->fences.blocks);
99 } else {
100 block = LIST_ENTRY(struct r600_fence_block, ctx->fences.blocks.next, head);
101 }
102
103 fence = &block->fences[index % FENCE_BLOCK_SIZE];
104 fence->ctx = ctx;
105 fence->index = index;
106 }
107
108 pipe_reference_init(&fence->reference, 1);
109
110 ctx->fences.data[fence->index] = 0;
111 r600_context_emit_fence(&ctx->ctx, ctx->fences.bo, fence->index, 1);
112 return fence;
113 }
114
115 static void r600_flush(struct pipe_context *ctx,
116 struct pipe_fence_handle **fence)
117 {
118 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
119 struct r600_fence **rfence = (struct r600_fence**)fence;
120
121 #if 0
122 static int dc = 0;
123 char dname[256];
124 #endif
125
126 if (rfence)
127 *rfence = r600_create_fence(rctx);
128
129 if (!rctx->ctx.pm4_cdwords)
130 return;
131
132 #if 0
133 sprintf(dname, "gallium-%08d.bof", dc);
134 if (dc < 20) {
135 r600_context_dump_bof(&rctx->ctx, dname);
136 R600_ERR("dumped %s\n", dname);
137 }
138 dc++;
139 #endif
140 r600_context_flush(&rctx->ctx);
141
142 /* XXX This shouldn't be really necessary, but removing it breaks some tests.
143 * Needless buffer reallocations may significantly increase memory consumption,
144 * so getting rid of this call is important. */
145 u_upload_flush(rctx->vbuf_mgr->uploader);
146 }
147
148 static void r600_update_num_contexts(struct r600_screen *rscreen, int diff)
149 {
150 pipe_mutex_lock(rscreen->mutex_num_contexts);
151 if (diff > 0) {
152 rscreen->num_contexts++;
153
154 if (rscreen->num_contexts > 1)
155 util_slab_set_thread_safety(&rscreen->pool_buffers,
156 UTIL_SLAB_MULTITHREADED);
157 } else {
158 rscreen->num_contexts--;
159
160 if (rscreen->num_contexts <= 1)
161 util_slab_set_thread_safety(&rscreen->pool_buffers,
162 UTIL_SLAB_SINGLETHREADED);
163 }
164 pipe_mutex_unlock(rscreen->mutex_num_contexts);
165 }
166
167 static void r600_destroy_context(struct pipe_context *context)
168 {
169 struct r600_pipe_context *rctx = (struct r600_pipe_context *)context;
170
171 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
172 util_unreference_framebuffer_state(&rctx->framebuffer);
173
174 r600_context_fini(&rctx->ctx);
175
176 util_blitter_destroy(rctx->blitter);
177
178 for (int i = 0; i < R600_PIPE_NSTATES; i++) {
179 free(rctx->states[i]);
180 }
181
182 u_vbuf_mgr_destroy(rctx->vbuf_mgr);
183 util_slab_destroy(&rctx->pool_transfers);
184
185 if (rctx->fences.bo) {
186 struct r600_fence_block *entry, *tmp;
187
188 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rctx->fences.blocks, head) {
189 LIST_DEL(&entry->head);
190 FREE(entry);
191 }
192
193 r600_bo_unmap(rctx->radeon, rctx->fences.bo);
194 r600_bo_reference(rctx->radeon, &rctx->fences.bo, NULL);
195 }
196
197 r600_update_num_contexts(rctx->screen, -1);
198
199 FREE(rctx);
200 }
201
202 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
203 {
204 struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context);
205 struct r600_screen* rscreen = (struct r600_screen *)screen;
206 enum chip_class class;
207
208 if (rctx == NULL)
209 return NULL;
210
211 r600_update_num_contexts(rscreen, 1);
212
213 rctx->context.winsys = rscreen->screen.winsys;
214 rctx->context.screen = screen;
215 rctx->context.priv = priv;
216 rctx->context.destroy = r600_destroy_context;
217 rctx->context.flush = r600_flush;
218
219 /* Easy accessing of screen/winsys. */
220 rctx->screen = rscreen;
221 rctx->radeon = rscreen->radeon;
222 rctx->family = r600_get_family(rctx->radeon);
223
224 rctx->fences.bo = NULL;
225 rctx->fences.data = NULL;
226 rctx->fences.next_index = 0;
227 LIST_INITHEAD(&rctx->fences.pool);
228 LIST_INITHEAD(&rctx->fences.blocks);
229
230 r600_init_blit_functions(rctx);
231 r600_init_query_functions(rctx);
232 r600_init_context_resource_functions(rctx);
233 r600_init_surface_functions(rctx);
234 rctx->context.draw_vbo = r600_draw_vbo;
235
236 switch (r600_get_family(rctx->radeon)) {
237 case CHIP_R600:
238 case CHIP_RV610:
239 case CHIP_RV630:
240 case CHIP_RV670:
241 case CHIP_RV620:
242 case CHIP_RV635:
243 case CHIP_RS780:
244 case CHIP_RS880:
245 case CHIP_RV770:
246 case CHIP_RV730:
247 case CHIP_RV710:
248 case CHIP_RV740:
249 r600_init_state_functions(rctx);
250 if (r600_context_init(&rctx->ctx, rctx->radeon)) {
251 r600_destroy_context(&rctx->context);
252 return NULL;
253 }
254 r600_init_config(rctx);
255 break;
256 case CHIP_CEDAR:
257 case CHIP_REDWOOD:
258 case CHIP_JUNIPER:
259 case CHIP_CYPRESS:
260 case CHIP_HEMLOCK:
261 case CHIP_PALM:
262 case CHIP_BARTS:
263 case CHIP_TURKS:
264 case CHIP_CAICOS:
265 evergreen_init_state_functions(rctx);
266 if (evergreen_context_init(&rctx->ctx, rctx->radeon)) {
267 r600_destroy_context(&rctx->context);
268 return NULL;
269 }
270 evergreen_init_config(rctx);
271 break;
272 default:
273 R600_ERR("unsupported family %d\n", r600_get_family(rctx->radeon));
274 r600_destroy_context(&rctx->context);
275 return NULL;
276 }
277
278 util_slab_create(&rctx->pool_transfers,
279 sizeof(struct pipe_transfer), 64,
280 UTIL_SLAB_SINGLETHREADED);
281
282 rctx->vbuf_mgr = u_vbuf_mgr_create(&rctx->context, 1024 * 1024, 256,
283 PIPE_BIND_VERTEX_BUFFER |
284 PIPE_BIND_INDEX_BUFFER |
285 PIPE_BIND_CONSTANT_BUFFER,
286 U_VERTEX_FETCH_DWORD_ALIGNED);
287 if (!rctx->vbuf_mgr) {
288 r600_destroy_context(&rctx->context);
289 return NULL;
290 }
291
292 rctx->blitter = util_blitter_create(&rctx->context);
293 if (rctx->blitter == NULL) {
294 r600_destroy_context(&rctx->context);
295 return NULL;
296 }
297
298 class = r600_get_family_class(rctx->radeon);
299 if (class == R600 || class == R700)
300 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
301 else
302 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
303
304 return &rctx->context;
305 }
306
307 /*
308 * pipe_screen
309 */
310 static const char* r600_get_vendor(struct pipe_screen* pscreen)
311 {
312 return "X.Org";
313 }
314
315 static const char *r600_get_family_name(enum radeon_family family)
316 {
317 switch(family) {
318 case CHIP_R600: return "AMD R600";
319 case CHIP_RV610: return "AMD RV610";
320 case CHIP_RV630: return "AMD RV630";
321 case CHIP_RV670: return "AMD RV670";
322 case CHIP_RV620: return "AMD RV620";
323 case CHIP_RV635: return "AMD RV635";
324 case CHIP_RS780: return "AMD RS780";
325 case CHIP_RS880: return "AMD RS880";
326 case CHIP_RV770: return "AMD RV770";
327 case CHIP_RV730: return "AMD RV730";
328 case CHIP_RV710: return "AMD RV710";
329 case CHIP_RV740: return "AMD RV740";
330 case CHIP_CEDAR: return "AMD CEDAR";
331 case CHIP_REDWOOD: return "AMD REDWOOD";
332 case CHIP_JUNIPER: return "AMD JUNIPER";
333 case CHIP_CYPRESS: return "AMD CYPRESS";
334 case CHIP_HEMLOCK: return "AMD HEMLOCK";
335 case CHIP_PALM: return "AMD PALM";
336 case CHIP_BARTS: return "AMD BARTS";
337 case CHIP_TURKS: return "AMD TURKS";
338 case CHIP_CAICOS: return "AMD CAICOS";
339 default: return "AMD unknown";
340 }
341 }
342
343 static const char* r600_get_name(struct pipe_screen* pscreen)
344 {
345 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
346 enum radeon_family family = r600_get_family(rscreen->radeon);
347
348 return r600_get_family_name(family);
349 }
350
351 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
352 {
353 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
354 enum radeon_family family = r600_get_family(rscreen->radeon);
355
356 switch (param) {
357 /* Supported features (boolean caps). */
358 case PIPE_CAP_NPOT_TEXTURES:
359 case PIPE_CAP_TWO_SIDED_STENCIL:
360 case PIPE_CAP_GLSL:
361 case PIPE_CAP_DUAL_SOURCE_BLEND:
362 case PIPE_CAP_ANISOTROPIC_FILTER:
363 case PIPE_CAP_POINT_SPRITE:
364 case PIPE_CAP_OCCLUSION_QUERY:
365 case PIPE_CAP_TEXTURE_SHADOW_MAP:
366 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
367 case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
368 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
369 case PIPE_CAP_SM3:
370 case PIPE_CAP_TEXTURE_SWIZZLE:
371 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
372 case PIPE_CAP_DEPTH_CLAMP:
373 case PIPE_CAP_SHADER_STENCIL_EXPORT:
374 case PIPE_CAP_TGSI_INSTANCEID:
375 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
376 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
377 return 1;
378 case PIPE_CAP_INDEP_BLEND_ENABLE:
379 /* R600 doesn't support per-MRT blends */
380 if (family == CHIP_R600)
381 return 0;
382 else
383 return 1;
384
385 /* Unsupported features (boolean caps). */
386 case PIPE_CAP_STREAM_OUTPUT:
387 case PIPE_CAP_PRIMITIVE_RESTART:
388 case PIPE_CAP_INDEP_BLEND_FUNC: /* FIXME allow this */
389 case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
390 /* R600 doesn't support per-MRT blends */
391 if (family == CHIP_R600)
392 return 0;
393 else
394 return 0;
395
396 case PIPE_CAP_ARRAY_TEXTURES:
397 /* fix once the CS checker upstream is fixed */
398 return debug_get_bool_option("R600_ARRAY_TEXTURE", FALSE);
399
400 /* Texturing. */
401 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
402 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
403 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
404 if (family >= CHIP_CEDAR)
405 return 15;
406 else
407 return 14;
408 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
409 /* FIXME allow this once infrastructure is there */
410 return 16;
411 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
412 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
413 return 16;
414
415 /* Render targets. */
416 case PIPE_CAP_MAX_RENDER_TARGETS:
417 /* FIXME some r6xx are buggy and can only do 4 */
418 return 8;
419
420 /* Fragment coordinate conventions. */
421 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
422 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
423 return 1;
424 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
425 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
426 return 0;
427
428 /* Timer queries, present when the clock frequency is non zero. */
429 case PIPE_CAP_TIMER_QUERY:
430 return r600_get_clock_crystal_freq(rscreen->radeon) != 0;
431
432 default:
433 R600_ERR("r600: unknown param %d\n", param);
434 return 0;
435 }
436 }
437
438 static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
439 {
440 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
441 enum radeon_family family = r600_get_family(rscreen->radeon);
442
443 switch (param) {
444 case PIPE_CAP_MAX_LINE_WIDTH:
445 case PIPE_CAP_MAX_LINE_WIDTH_AA:
446 case PIPE_CAP_MAX_POINT_WIDTH:
447 case PIPE_CAP_MAX_POINT_WIDTH_AA:
448 if (family >= CHIP_CEDAR)
449 return 16384.0f;
450 else
451 return 8192.0f;
452 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
453 return 16.0f;
454 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
455 return 16.0f;
456 default:
457 R600_ERR("r600: unsupported paramf %d\n", param);
458 return 0.0f;
459 }
460 }
461
462 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
463 {
464 switch(shader)
465 {
466 case PIPE_SHADER_FRAGMENT:
467 case PIPE_SHADER_VERTEX:
468 break;
469 case PIPE_SHADER_GEOMETRY:
470 /* TODO: support and enable geometry programs */
471 return 0;
472 default:
473 /* TODO: support tessellation on Evergreen */
474 return 0;
475 }
476
477 /* TODO: all these should be fixed, since r600 surely supports much more! */
478 switch (param) {
479 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
480 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
481 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
482 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
483 return 16384;
484 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
485 return 8; /* FIXME */
486 case PIPE_SHADER_CAP_MAX_INPUTS:
487 if(shader == PIPE_SHADER_FRAGMENT)
488 return 10;
489 else
490 return 16;
491 case PIPE_SHADER_CAP_MAX_TEMPS:
492 return 256; //max native temporaries
493 case PIPE_SHADER_CAP_MAX_ADDRS:
494 return 1; //max native address registers/* FIXME Isn't this equal to TEMPS? */
495 case PIPE_SHADER_CAP_MAX_CONSTS:
496 return R600_MAX_CONST_BUFFER_SIZE;
497 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
498 return R600_MAX_CONST_BUFFERS;
499 case PIPE_SHADER_CAP_MAX_PREDS:
500 return 0; /* FIXME */
501 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
502 return 1;
503 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
504 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
505 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
506 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
507 return 1;
508 case PIPE_SHADER_CAP_SUBROUTINES:
509 return 0;
510 default:
511 return 0;
512 }
513 }
514
515 static boolean r600_is_format_supported(struct pipe_screen* screen,
516 enum pipe_format format,
517 enum pipe_texture_target target,
518 unsigned sample_count,
519 unsigned usage)
520 {
521 unsigned retval = 0;
522 if (target >= PIPE_MAX_TEXTURE_TYPES) {
523 R600_ERR("r600: unsupported texture type %d\n", target);
524 return FALSE;
525 }
526
527 if (!util_format_is_supported(format, usage))
528 return FALSE;
529
530 /* Multisample */
531 if (sample_count > 1)
532 return FALSE;
533
534 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
535 r600_is_sampler_format_supported(screen, format)) {
536 retval |= PIPE_BIND_SAMPLER_VIEW;
537 }
538
539 if ((usage & (PIPE_BIND_RENDER_TARGET |
540 PIPE_BIND_DISPLAY_TARGET |
541 PIPE_BIND_SCANOUT |
542 PIPE_BIND_SHARED)) &&
543 r600_is_colorbuffer_format_supported(format)) {
544 retval |= usage &
545 (PIPE_BIND_RENDER_TARGET |
546 PIPE_BIND_DISPLAY_TARGET |
547 PIPE_BIND_SCANOUT |
548 PIPE_BIND_SHARED);
549 }
550
551 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
552 r600_is_zs_format_supported(format)) {
553 retval |= PIPE_BIND_DEPTH_STENCIL;
554 }
555
556 if (usage & PIPE_BIND_VERTEX_BUFFER) {
557 struct r600_screen *rscreen = (struct r600_screen *)screen;
558 enum radeon_family family = r600_get_family(rscreen->radeon);
559
560 if (r600_is_vertex_format_supported(format, family)) {
561 retval |= PIPE_BIND_VERTEX_BUFFER;
562 }
563 }
564
565 if (usage & PIPE_BIND_TRANSFER_READ)
566 retval |= PIPE_BIND_TRANSFER_READ;
567 if (usage & PIPE_BIND_TRANSFER_WRITE)
568 retval |= PIPE_BIND_TRANSFER_WRITE;
569
570 return retval == usage;
571 }
572
573 static void r600_destroy_screen(struct pipe_screen* pscreen)
574 {
575 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
576
577 if (rscreen == NULL)
578 return;
579
580 radeon_decref(rscreen->radeon);
581
582 util_slab_destroy(&rscreen->pool_buffers);
583 pipe_mutex_destroy(rscreen->mutex_num_contexts);
584 FREE(rscreen);
585 }
586
587 static void r600_fence_reference(struct pipe_screen *pscreen,
588 struct pipe_fence_handle **ptr,
589 struct pipe_fence_handle *fence)
590 {
591 struct r600_fence **oldf = (struct r600_fence**)ptr;
592 struct r600_fence *newf = (struct r600_fence*)fence;
593
594 if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
595 struct r600_pipe_context *ctx = (*oldf)->ctx;
596 LIST_ADDTAIL(&(*oldf)->head, &ctx->fences.pool);
597 }
598
599 *ptr = fence;
600 }
601
602 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
603 struct pipe_fence_handle *fence)
604 {
605 struct r600_fence *rfence = (struct r600_fence*)fence;
606 struct r600_pipe_context *ctx = rfence->ctx;
607
608 return ctx->fences.data[rfence->index];
609 }
610
611 static boolean r600_fence_finish(struct pipe_screen *pscreen,
612 struct pipe_fence_handle *fence,
613 uint64_t timeout)
614 {
615 struct r600_fence *rfence = (struct r600_fence*)fence;
616 struct r600_pipe_context *ctx = rfence->ctx;
617 int64_t start_time = 0;
618 unsigned spins = 0;
619
620 if (timeout != PIPE_TIMEOUT_INFINITE) {
621 start_time = os_time_get();
622
623 /* Convert to microseconds. */
624 timeout /= 1000;
625 }
626
627 while (ctx->fences.data[rfence->index] == 0) {
628 if (++spins % 256)
629 continue;
630 #ifdef PIPE_OS_UNIX
631 sched_yield();
632 #else
633 os_time_sleep(10);
634 #endif
635 if (timeout != PIPE_TIMEOUT_INFINITE &&
636 os_time_get() - start_time >= timeout) {
637 return FALSE;
638 }
639 }
640
641 return TRUE;
642 }
643
644 struct pipe_screen *r600_screen_create(struct radeon *radeon)
645 {
646 struct r600_screen *rscreen;
647
648 rscreen = CALLOC_STRUCT(r600_screen);
649 if (rscreen == NULL) {
650 return NULL;
651 }
652
653 rscreen->radeon = radeon;
654 rscreen->screen.winsys = (struct pipe_winsys*)radeon;
655 rscreen->screen.destroy = r600_destroy_screen;
656 rscreen->screen.get_name = r600_get_name;
657 rscreen->screen.get_vendor = r600_get_vendor;
658 rscreen->screen.get_param = r600_get_param;
659 rscreen->screen.get_shader_param = r600_get_shader_param;
660 rscreen->screen.get_paramf = r600_get_paramf;
661 rscreen->screen.is_format_supported = r600_is_format_supported;
662 rscreen->screen.context_create = r600_create_context;
663 rscreen->screen.fence_reference = r600_fence_reference;
664 rscreen->screen.fence_signalled = r600_fence_signalled;
665 rscreen->screen.fence_finish = r600_fence_finish;
666 r600_init_screen_resource_functions(&rscreen->screen);
667
668 rscreen->tiling_info = r600_get_tiling_info(radeon);
669 util_format_s3tc_init();
670
671 util_slab_create(&rscreen->pool_buffers,
672 sizeof(struct r600_resource_buffer), 64,
673 UTIL_SLAB_SINGLETHREADED);
674
675 pipe_mutex_init(rscreen->mutex_num_contexts);
676
677 return &rscreen->screen;
678 }