src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "pipe/p_context.h"
  28 #include "tgsi/tgsi_scan.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "tgsi/tgsi_util.h"
  31 #include "util/u_blitter.h"
  32 #include "util/u_double_list.h"
  33 #include "util/u_format.h"
  34 #include "util/u_format_s3tc.h"
  35 #include "util/u_transfer.h"
  36 #include "util/u_surface.h"
  37 #include "util/u_pack_color.h"
  38 #include "util/u_memory.h"
  39 #include "util/u_inlines.h"
  40 #include "util/u_upload_mgr.h"
  41 #include "vl/vl_decoder.h"
  42 #include "vl/vl_video_buffer.h"
  43 #include "os/os_time.h"
  44 #include "pipebuffer/pb_buffer.h"
  45 #include "r600.h"
  46 #include "r600d.h"
  47 #include "r600_resource.h"
  48 #include "r600_shader.h"
  49 #include "r600_pipe.h"
  50
  51 /*
  52  * pipe_context
  53  */
  54 static struct r600_fence *r600_create_fence(struct r600_pipe_context *ctx)
  55 {
  56         struct r600_screen *rscreen = ctx->screen;
  57         struct r600_fence *fence = NULL;
  58
  59         pipe_mutex_lock(rscreen->fences.mutex);
  60
  61         if (!rscreen->fences.bo) {
  62                 /* Create the shared buffer object */
  63                 rscreen->fences.bo = (struct r600_resource*)
  64                         pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
  65                                            PIPE_USAGE_STAGING, 4096);
  66                 if (!rscreen->fences.bo) {
  67                         R600_ERR("r600: failed to create bo for fence objects\n");
  68                         goto out;
  69                 }
  70                 rscreen->fences.data = ctx->ws->buffer_map(rscreen->fences.bo->buf,
  71                                                            ctx->ctx.cs,
  72                                                            PIPE_TRANSFER_READ_WRITE);
  73         }
  74
  75         if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
  76                 struct r600_fence *entry;
  77
  78                 /* Try to find a freed fence that has been signalled */
  79                 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
  80                         if (rscreen->fences.data[entry->index] != 0) {
  81                                 LIST_DELINIT(&entry->head);
  82                                 fence = entry;
  83                                 break;
  84                         }
  85                 }
  86         }
  87
  88         if (!fence) {
  89                 /* Allocate a new fence */
  90                 struct r600_fence_block *block;
  91                 unsigned index;
  92
  93                 if ((rscreen->fences.next_index + 1) >= 1024) {
  94                         R600_ERR("r600: too many concurrent fences\n");
  95                         goto out;
  96                 }
  97
  98                 index = rscreen->fences.next_index++;
  99
 100                 if (!(index % FENCE_BLOCK_SIZE)) {
 101                         /* Allocate a new block */
 102                         block = CALLOC_STRUCT(r600_fence_block);
 103                         if (block == NULL)
 104                                 goto out;
 105
 106                         LIST_ADD(&block->head, &rscreen->fences.blocks);
 107                 } else {
 108                         block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
 109                 }
 110
 111                 fence = &block->fences[index % FENCE_BLOCK_SIZE];
 112                 fence->index = index;
 113         }
 114
 115         pipe_reference_init(&fence->reference, 1);
 116
 117         rscreen->fences.data[fence->index] = 0;
 118         r600_context_emit_fence(&ctx->ctx, rscreen->fences.bo, fence->index, 1);
 119 out:
 120         pipe_mutex_unlock(rscreen->fences.mutex);
 121         return fence;
 122 }
 123
 124
 125 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 126                 unsigned flags)
 127 {
 128         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 129         struct r600_fence **rfence = (struct r600_fence**)fence;
 130         struct pipe_query *render_cond = NULL;
 131         unsigned render_cond_mode = 0;
 132
 133         if (rfence)
 134                 *rfence = r600_create_fence(rctx);
 135
 136         /* Disable render condition. */
 137         if (rctx->current_render_cond) {
 138                 render_cond = rctx->current_render_cond;
 139                 render_cond_mode = rctx->current_render_cond_mode;
 140                 ctx->render_condition(ctx, NULL, 0);
 141         }
 142
 143         r600_context_flush(&rctx->ctx, flags);
 144
 145         /* Re-enable render condition. */
 146         if (render_cond) {
 147                 ctx->render_condition(ctx, render_cond, render_cond_mode);
 148         }
 149 }
 150
 151 static void r600_flush_from_st(struct pipe_context *ctx,
 152                                struct pipe_fence_handle **fence)
 153 {
 154         r600_flush(ctx, fence, 0);
 155 }
 156
 157 static void r600_flush_from_winsys(void *ctx, unsigned flags)
 158 {
 159         r600_flush((struct pipe_context*)ctx, NULL, flags);
 160 }
 161
 162 static void r600_update_num_contexts(struct r600_screen *rscreen, int diff)
 163 {
 164         pipe_mutex_lock(rscreen->mutex_num_contexts);
 165         if (diff > 0) {
 166                 rscreen->num_contexts++;
 167
 168                 if (rscreen->num_contexts > 1)
 169                         util_slab_set_thread_safety(&rscreen->pool_buffers,
 170                                                     UTIL_SLAB_MULTITHREADED);
 171         } else {
 172                 rscreen->num_contexts--;
 173
 174                 if (rscreen->num_contexts <= 1)
 175                         util_slab_set_thread_safety(&rscreen->pool_buffers,
 176                                                     UTIL_SLAB_SINGLETHREADED);
 177         }
 178         pipe_mutex_unlock(rscreen->mutex_num_contexts);
 179 }
 180
 181 static void r600_destroy_context(struct pipe_context *context)
 182 {
 183         struct r600_pipe_context *rctx = (struct r600_pipe_context *)context;
 184
 185         rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
 186         util_unreference_framebuffer_state(&rctx->framebuffer);
 187
 188         r600_context_fini(&rctx->ctx);
 189
 190         util_blitter_destroy(rctx->blitter);
 191
 192         for (int i = 0; i < R600_PIPE_NSTATES; i++) {
 193                 free(rctx->states[i]);
 194         }
 195
 196         u_vbuf_destroy(rctx->vbuf_mgr);
 197         util_slab_destroy(&rctx->pool_transfers);
 198
 199         r600_update_num_contexts(rctx->screen, -1);
 200
 201         FREE(rctx);
 202 }
 203
 204 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 205 {
 206         struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context);
 207         struct r600_screen* rscreen = (struct r600_screen *)screen;
 208
 209         if (rctx == NULL)
 210                 return NULL;
 211
 212         r600_update_num_contexts(rscreen, 1);
 213
 214         rctx->context.winsys = rscreen->screen.winsys;
 215         rctx->context.screen = screen;
 216         rctx->context.priv = priv;
 217         rctx->context.destroy = r600_destroy_context;
 218         rctx->context.flush = r600_flush_from_st;
 219
 220         /* Easy accessing of screen/winsys. */
 221         rctx->screen = rscreen;
 222         rctx->ws = rscreen->ws;
 223         rctx->family = rscreen->family;
 224         rctx->chip_class = rscreen->chip_class;
 225
 226         r600_init_blit_functions(rctx);
 227         r600_init_query_functions(rctx);
 228         r600_init_context_resource_functions(rctx);
 229         r600_init_surface_functions(rctx);
 230         rctx->context.draw_vbo = r600_draw_vbo;
 231
 232         rctx->context.create_video_decoder = vl_create_decoder;
 233         rctx->context.create_video_buffer = vl_video_buffer_create;
 234
 235         switch (rctx->chip_class) {
 236         case R600:
 237         case R700:
 238                 r600_init_state_functions(rctx);
 239                 if (r600_context_init(&rctx->ctx, rctx->screen)) {
 240                         r600_destroy_context(&rctx->context);
 241                         return NULL;
 242                 }
 243                 r600_init_config(rctx);
 244                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 245                 break;
 246         case EVERGREEN:
 247         case CAYMAN:
 248                 evergreen_init_state_functions(rctx);
 249                 if (evergreen_context_init(&rctx->ctx, rctx->screen)) {
 250                         r600_destroy_context(&rctx->context);
 251                         return NULL;
 252                 }
 253                 evergreen_init_config(rctx);
 254                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 255                 break;
 256         default:
 257                 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
 258                 r600_destroy_context(&rctx->context);
 259                 return NULL;
 260         }
 261
 262         rctx->ctx.pipe = &rctx->context;
 263         rctx->ctx.flush = r600_flush_from_winsys;
 264         rctx->ws->cs_set_flush_callback(rctx->ctx.cs, r600_flush_from_winsys, rctx);
 265
 266         util_slab_create(&rctx->pool_transfers,
 267                          sizeof(struct pipe_transfer), 64,
 268                          UTIL_SLAB_SINGLETHREADED);
 269
 270         rctx->vbuf_mgr = u_vbuf_create(&rctx->context, 1024 * 1024, 256,
 271                                            PIPE_BIND_VERTEX_BUFFER |
 272                                            PIPE_BIND_INDEX_BUFFER |
 273                                            PIPE_BIND_CONSTANT_BUFFER,
 274                                            U_VERTEX_FETCH_DWORD_ALIGNED);
 275         if (!rctx->vbuf_mgr) {
 276                 r600_destroy_context(&rctx->context);
 277                 return NULL;
 278         }
 279         rctx->vbuf_mgr->caps.format_fixed32 = 0;
 280
 281         rctx->blitter = util_blitter_create(&rctx->context);
 282         if (rctx->blitter == NULL) {
 283                 r600_destroy_context(&rctx->context);
 284                 return NULL;
 285         }
 286
 287         r600_get_backend_mask(&rctx->ctx); /* this emits commands and must be last */
 288
 289         return &rctx->context;
 290 }
 291
 292 /*
 293  * pipe_screen
 294  */
 295 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 296 {
 297         return "X.Org";
 298 }
 299
 300 static const char *r600_get_family_name(enum radeon_family family)
 301 {
 302         switch(family) {
 303         case CHIP_R600: return "AMD R600";
 304         case CHIP_RV610: return "AMD RV610";
 305         case CHIP_RV630: return "AMD RV630";
 306         case CHIP_RV670: return "AMD RV670";
 307         case CHIP_RV620: return "AMD RV620";
 308         case CHIP_RV635: return "AMD RV635";
 309         case CHIP_RS780: return "AMD RS780";
 310         case CHIP_RS880: return "AMD RS880";
 311         case CHIP_RV770: return "AMD RV770";
 312         case CHIP_RV730: return "AMD RV730";
 313         case CHIP_RV710: return "AMD RV710";
 314         case CHIP_RV740: return "AMD RV740";
 315         case CHIP_CEDAR: return "AMD CEDAR";
 316         case CHIP_REDWOOD: return "AMD REDWOOD";
 317         case CHIP_JUNIPER: return "AMD JUNIPER";
 318         case CHIP_CYPRESS: return "AMD CYPRESS";
 319         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 320         case CHIP_PALM: return "AMD PALM";
 321         case CHIP_SUMO: return "AMD SUMO";
 322         case CHIP_SUMO2: return "AMD SUMO2";
 323         case CHIP_BARTS: return "AMD BARTS";
 324         case CHIP_TURKS: return "AMD TURKS";
 325         case CHIP_CAICOS: return "AMD CAICOS";
 326         case CHIP_CAYMAN: return "AMD CAYMAN";
 327         default: return "AMD unknown";
 328         }
 329 }
 330
 331 static const char* r600_get_name(struct pipe_screen* pscreen)
 332 {
 333         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 334
 335         return r600_get_family_name(rscreen->family);
 336 }
 337
 338 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 339 {
 340         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 341         enum radeon_family family = rscreen->family;
 342
 343         switch (param) {
 344         /* Supported features (boolean caps). */
 345         case PIPE_CAP_NPOT_TEXTURES:
 346         case PIPE_CAP_TWO_SIDED_STENCIL:
 347         case PIPE_CAP_DUAL_SOURCE_BLEND:
 348         case PIPE_CAP_ANISOTROPIC_FILTER:
 349         case PIPE_CAP_POINT_SPRITE:
 350         case PIPE_CAP_OCCLUSION_QUERY:
 351         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 352         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 353         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 354         case PIPE_CAP_TEXTURE_SWIZZLE:
 355         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 356         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 357         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 358         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 359         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 360         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 361         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 362         case PIPE_CAP_SM3:
 363         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 364         case PIPE_CAP_PRIMITIVE_RESTART:
 365         case PIPE_CAP_CONDITIONAL_RENDER:
 366         case PIPE_CAP_TEXTURE_BARRIER:
 367         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 368         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 369                 return 1;
 370
 371         /* Supported except the original R600. */
 372         case PIPE_CAP_INDEP_BLEND_ENABLE:
 373         case PIPE_CAP_INDEP_BLEND_FUNC:
 374                 /* R600 doesn't support per-MRT blends */
 375                 return family == CHIP_R600 ? 0 : 1;
 376
 377         /* Supported on Evergreen. */
 378         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 379                 return family >= CHIP_CEDAR ? 1 : 0;
 380
 381         /* Unsupported features. */
 382         case PIPE_CAP_TGSI_INSTANCEID:
 383         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 384         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 385         case PIPE_CAP_SCALED_RESOLVE:
 386         case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 387         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 388         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 389         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 390                 return 0;
 391
 392         /* Stream output. */
 393         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 394                 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 4 : 0;
 395         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 396         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 397                 return 16*4;
 398
 399         /* Texturing. */
 400         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 401         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 402         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 403                 if (family >= CHIP_CEDAR)
 404                         return 15;
 405                 else
 406                         return 14;
 407         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 408                 return rscreen->info.drm_minor >= 9 ?
 409                         (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
 410         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 411                 return 32;
 412
 413         /* Render targets. */
 414         case PIPE_CAP_MAX_RENDER_TARGETS:
 415                 /* FIXME some r6xx are buggy and can only do 4 */
 416                 return 8;
 417
 418         /* Timer queries, present when the clock frequency is non zero. */
 419         case PIPE_CAP_TIMER_QUERY:
 420                 return rscreen->info.r600_clock_crystal_freq != 0;
 421
 422         case PIPE_CAP_MIN_TEXEL_OFFSET:
 423                 return -8;
 424
 425         case PIPE_CAP_MAX_TEXEL_OFFSET:
 426                 return 7;
 427         }
 428         return 0;
 429 }
 430
 431 static float r600_get_paramf(struct pipe_screen* pscreen,
 432                              enum pipe_capf param)
 433 {
 434         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 435         enum radeon_family family = rscreen->family;
 436
 437         switch (param) {
 438         case PIPE_CAPF_MAX_LINE_WIDTH:
 439         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 440         case PIPE_CAPF_MAX_POINT_WIDTH:
 441         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 442                 if (family >= CHIP_CEDAR)
 443                         return 16384.0f;
 444                 else
 445                         return 8192.0f;
 446         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 447                 return 16.0f;
 448         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 449                 return 16.0f;
 450         case PIPE_CAPF_GUARD_BAND_LEFT:
 451         case PIPE_CAPF_GUARD_BAND_TOP:
 452         case PIPE_CAPF_GUARD_BAND_RIGHT:
 453         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 454                 return 0.0f;
 455         }
 456         return 0.0f;
 457 }
 458
 459 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 460 {
 461         switch(shader)
 462         {
 463         case PIPE_SHADER_FRAGMENT:
 464         case PIPE_SHADER_VERTEX:
 465                 break;
 466         case PIPE_SHADER_GEOMETRY:
 467                 /* TODO: support and enable geometry programs */
 468                 return 0;
 469         default:
 470                 /* TODO: support tessellation on Evergreen */
 471                 return 0;
 472         }
 473
 474         /* TODO: all these should be fixed, since r600 surely supports much more! */
 475         switch (param) {
 476         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 477         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 478         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 479         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 480                 return 16384;
 481         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 482                 return 8; /* FIXME */
 483         case PIPE_SHADER_CAP_MAX_INPUTS:
 484                 if(shader == PIPE_SHADER_FRAGMENT)
 485                         return 34;
 486                 else
 487                         return 32;
 488         case PIPE_SHADER_CAP_MAX_TEMPS:
 489                 return 256; /* Max native temporaries. */
 490         case PIPE_SHADER_CAP_MAX_ADDRS:
 491                 /* FIXME Isn't this equal to TEMPS? */
 492                 return 1; /* Max native address registers */
 493         case PIPE_SHADER_CAP_MAX_CONSTS:
 494                 return R600_MAX_CONST_BUFFER_SIZE;
 495         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 496                 return R600_MAX_CONST_BUFFERS-1;
 497         case PIPE_SHADER_CAP_MAX_PREDS:
 498                 return 0; /* FIXME */
 499         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 500                 return 1;
 501         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 502         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 503         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 504         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 505                 return 1;
 506         case PIPE_SHADER_CAP_SUBROUTINES:
 507                 return 0;
 508         case PIPE_SHADER_CAP_INTEGERS:
 509                 return 0;
 510         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 511                 return 16;
 512         case PIPE_SHADER_CAP_OUTPUT_READ:
 513                 return 1;
 514         }
 515         return 0;
 516 }
 517
 518 static int r600_get_video_param(struct pipe_screen *screen,
 519                                 enum pipe_video_profile profile,
 520                                 enum pipe_video_cap param)
 521 {
 522         switch (param) {
 523         case PIPE_VIDEO_CAP_SUPPORTED:
 524                 return vl_profile_supported(screen, profile);
 525         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 526                 return 1;
 527         case PIPE_VIDEO_CAP_MAX_WIDTH:
 528         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 529                 return vl_video_buffer_max_size(screen);
 530         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 531                 return PIPE_FORMAT_NV12;
 532         default:
 533                 return 0;
 534         }
 535 }
 536
 537 static void r600_destroy_screen(struct pipe_screen* pscreen)
 538 {
 539         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 540
 541         if (rscreen == NULL)
 542                 return;
 543
 544         if (rscreen->fences.bo) {
 545                 struct r600_fence_block *entry, *tmp;
 546
 547                 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
 548                         LIST_DEL(&entry->head);
 549                         FREE(entry);
 550                 }
 551
 552                 rscreen->ws->buffer_unmap(rscreen->fences.bo->buf);
 553                 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
 554         }
 555         pipe_mutex_destroy(rscreen->fences.mutex);
 556
 557         rscreen->ws->destroy(rscreen->ws);
 558
 559         util_slab_destroy(&rscreen->pool_buffers);
 560         pipe_mutex_destroy(rscreen->mutex_num_contexts);
 561         FREE(rscreen);
 562 }
 563
 564 static void r600_fence_reference(struct pipe_screen *pscreen,
 565                                  struct pipe_fence_handle **ptr,
 566                                  struct pipe_fence_handle *fence)
 567 {
 568         struct r600_fence **oldf = (struct r600_fence**)ptr;
 569         struct r600_fence *newf = (struct r600_fence*)fence;
 570
 571         if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
 572                 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 573                 pipe_mutex_lock(rscreen->fences.mutex);
 574                 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
 575                 pipe_mutex_unlock(rscreen->fences.mutex);
 576         }
 577
 578         *ptr = fence;
 579 }
 580
 581 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
 582                                     struct pipe_fence_handle *fence)
 583 {
 584         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 585         struct r600_fence *rfence = (struct r600_fence*)fence;
 586
 587         return rscreen->fences.data[rfence->index];
 588 }
 589
 590 static boolean r600_fence_finish(struct pipe_screen *pscreen,
 591                                  struct pipe_fence_handle *fence,
 592                                  uint64_t timeout)
 593 {
 594         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 595         struct r600_fence *rfence = (struct r600_fence*)fence;
 596         int64_t start_time = 0;
 597         unsigned spins = 0;
 598
 599         if (timeout != PIPE_TIMEOUT_INFINITE) {
 600                 start_time = os_time_get();
 601
 602                 /* Convert to microseconds. */
 603                 timeout /= 1000;
 604         }
 605
 606         while (rscreen->fences.data[rfence->index] == 0) {
 607                 if (++spins % 256)
 608                         continue;
 609 #ifdef PIPE_OS_UNIX
 610                 sched_yield();
 611 #else
 612                 os_time_sleep(10);
 613 #endif
 614                 if (timeout != PIPE_TIMEOUT_INFINITE &&
 615                     os_time_get() - start_time >= timeout) {
 616                         return FALSE;
 617                 }
 618         }
 619
 620         return TRUE;
 621 }
 622
 623 static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 624 {
 625         switch ((tiling_config & 0xe) >> 1) {
 626         case 0:
 627                 rscreen->tiling_info.num_channels = 1;
 628                 break;
 629         case 1:
 630                 rscreen->tiling_info.num_channels = 2;
 631                 break;
 632         case 2:
 633                 rscreen->tiling_info.num_channels = 4;
 634                 break;
 635         case 3:
 636                 rscreen->tiling_info.num_channels = 8;
 637                 break;
 638         default:
 639                 return -EINVAL;
 640         }
 641
 642         switch ((tiling_config & 0x30) >> 4) {
 643         case 0:
 644                 rscreen->tiling_info.num_banks = 4;
 645                 break;
 646         case 1:
 647                 rscreen->tiling_info.num_banks = 8;
 648                 break;
 649         default:
 650                 return -EINVAL;
 651
 652         }
 653         switch ((tiling_config & 0xc0) >> 6) {
 654         case 0:
 655                 rscreen->tiling_info.group_bytes = 256;
 656                 break;
 657         case 1:
 658                 rscreen->tiling_info.group_bytes = 512;
 659                 break;
 660         default:
 661                 return -EINVAL;
 662         }
 663         return 0;
 664 }
 665
 666 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 667 {
 668         switch (tiling_config & 0xf) {
 669         case 0:
 670                 rscreen->tiling_info.num_channels = 1;
 671                 break;
 672         case 1:
 673                 rscreen->tiling_info.num_channels = 2;
 674                 break;
 675         case 2:
 676                 rscreen->tiling_info.num_channels = 4;
 677                 break;
 678         case 3:
 679                 rscreen->tiling_info.num_channels = 8;
 680                 break;
 681         default:
 682                 return -EINVAL;
 683         }
 684
 685         switch ((tiling_config & 0xf0) >> 4) {
 686         case 0:
 687                 rscreen->tiling_info.num_banks = 4;
 688                 break;
 689         case 1:
 690                 rscreen->tiling_info.num_banks = 8;
 691                 break;
 692         case 2:
 693                 rscreen->tiling_info.num_banks = 16;
 694                 break;
 695         default:
 696                 return -EINVAL;
 697         }
 698
 699         switch ((tiling_config & 0xf00) >> 8) {
 700         case 0:
 701                 rscreen->tiling_info.group_bytes = 256;
 702                 break;
 703         case 1:
 704                 rscreen->tiling_info.group_bytes = 512;
 705                 break;
 706         default:
 707                 return -EINVAL;
 708         }
 709         return 0;
 710 }
 711
 712 static int r600_init_tiling(struct r600_screen *rscreen)
 713 {
 714         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 715
 716         /* set default group bytes, overridden by tiling info ioctl */
 717         if (rscreen->chip_class <= R700) {
 718                 rscreen->tiling_info.group_bytes = 256;
 719         } else {
 720                 rscreen->tiling_info.group_bytes = 512;
 721         }
 722
 723         if (!tiling_config)
 724                 return 0;
 725
 726         if (rscreen->chip_class <= R700) {
 727                 return r600_interpret_tiling(rscreen, tiling_config);
 728         } else {
 729                 return evergreen_interpret_tiling(rscreen, tiling_config);
 730         }
 731 }
 732
 733 static unsigned radeon_family_from_device(unsigned device)
 734 {
 735         switch (device) {
 736 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
 737 #include "pci_ids/r600_pci_ids.h"
 738 #undef CHIPSET
 739         default:
 740                 return CHIP_UNKNOWN;
 741         }
 742 }
 743
 744 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 745 {
 746         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 747         if (rscreen == NULL) {
 748                 return NULL;
 749         }
 750
 751         rscreen->ws = ws;
 752         ws->query_info(ws, &rscreen->info);
 753
 754         rscreen->family = radeon_family_from_device(rscreen->info.pci_id);
 755         if (rscreen->family == CHIP_UNKNOWN) {
 756                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
 757                 FREE(rscreen);
 758                 return NULL;
 759         }
 760
 761         /* setup class */
 762         if (rscreen->family == CHIP_CAYMAN) {
 763                 rscreen->chip_class = CAYMAN;
 764         } else if (rscreen->family >= CHIP_CEDAR) {
 765                 rscreen->chip_class = EVERGREEN;
 766         } else if (rscreen->family >= CHIP_RV770) {
 767                 rscreen->chip_class = R700;
 768         } else {
 769                 rscreen->chip_class = R600;
 770         }
 771
 772         if (r600_init_tiling(rscreen)) {
 773                 FREE(rscreen);
 774                 return NULL;
 775         }
 776
 777         rscreen->screen.winsys = (struct pipe_winsys*)ws;
 778         rscreen->screen.destroy = r600_destroy_screen;
 779         rscreen->screen.get_name = r600_get_name;
 780         rscreen->screen.get_vendor = r600_get_vendor;
 781         rscreen->screen.get_param = r600_get_param;
 782         rscreen->screen.get_shader_param = r600_get_shader_param;
 783         rscreen->screen.get_paramf = r600_get_paramf;
 784         rscreen->screen.get_video_param = r600_get_video_param;
 785         if (rscreen->chip_class >= EVERGREEN) {
 786                 rscreen->screen.is_format_supported = evergreen_is_format_supported;
 787         } else {
 788                 rscreen->screen.is_format_supported = r600_is_format_supported;
 789         }
 790         rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
 791         rscreen->screen.context_create = r600_create_context;
 792         rscreen->screen.fence_reference = r600_fence_reference;
 793         rscreen->screen.fence_signalled = r600_fence_signalled;
 794         rscreen->screen.fence_finish = r600_fence_finish;
 795         r600_init_screen_resource_functions(&rscreen->screen);
 796
 797         util_format_s3tc_init();
 798
 799         util_slab_create(&rscreen->pool_buffers,
 800                          sizeof(struct r600_resource), 64,
 801                          UTIL_SLAB_SINGLETHREADED);
 802
 803         pipe_mutex_init(rscreen->mutex_num_contexts);
 804
 805         rscreen->fences.bo = NULL;
 806         rscreen->fences.data = NULL;
 807         rscreen->fences.next_index = 0;
 808         LIST_INITHEAD(&rscreen->fences.pool);
 809         LIST_INITHEAD(&rscreen->fences.blocks);
 810         pipe_mutex_init(rscreen->fences.mutex);
 811
 812         return &rscreen->screen;
 813 }