2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_pipe.h"
24 #include "r600_public.h"
26 #include "evergreen_compute.h"
29 #include "sb/sb_public.h"
32 #include "pipe/p_shader_tokens.h"
33 #include "util/u_blitter.h"
34 #include "util/u_debug.h"
35 #include "util/u_memory.h"
36 #include "util/u_simple_shaders.h"
37 #include "util/u_upload_mgr.h"
38 #include "util/u_math.h"
39 #include "vl/vl_decoder.h"
40 #include "vl/vl_video_buffer.h"
41 #include "radeon/radeon_uvd.h"
42 #include "os/os_time.h"
44 static const struct debug_named_value r600_debug_options
[] = {
46 #if defined(R600_USE_LLVM)
47 { "nollvm", DBG_NO_LLVM
, "Disable the LLVM shader compiler" },
49 { "nocpdma", DBG_NO_CP_DMA
, "Disable CP DMA" },
50 { "nodma", DBG_NO_ASYNC_DMA
, "Disable asynchronous DMA" },
53 { "nosb", DBG_NO_SB
, "Disable sb backend for graphics shaders" },
54 { "sbcl", DBG_SB_CS
, "Enable sb backend for compute shaders" },
55 { "sbdry", DBG_SB_DRY_RUN
, "Don't use optimized bytecode (just print the dumps)" },
56 { "sbstat", DBG_SB_STAT
, "Print optimization statistics for shaders" },
57 { "sbdump", DBG_SB_DUMP
, "Print IR dumps after some optimization passes" },
58 { "sbnofallback", DBG_SB_NO_FALLBACK
, "Abort on errors instead of fallback" },
59 { "sbdisasm", DBG_SB_DISASM
, "Use sb disassembler for shader dumps" },
60 { "sbsafemath", DBG_SB_SAFEMATH
, "Disable unsafe math optimizations" },
62 DEBUG_NAMED_VALUE_END
/* must be last */
69 static void r600_flush(struct pipe_context
*ctx
, unsigned flags
)
71 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
72 struct pipe_query
*render_cond
= NULL
;
73 unsigned render_cond_mode
= 0;
74 boolean render_cond_cond
= FALSE
;
76 if (rctx
->b
.rings
.gfx
.cs
->cdw
== rctx
->initial_gfx_cs_size
)
79 rctx
->b
.rings
.gfx
.flushing
= true;
80 /* Disable render condition. */
81 if (rctx
->b
.current_render_cond
) {
82 render_cond
= rctx
->b
.current_render_cond
;
83 render_cond_cond
= rctx
->b
.current_render_cond_cond
;
84 render_cond_mode
= rctx
->b
.current_render_cond_mode
;
85 ctx
->render_condition(ctx
, NULL
, FALSE
, 0);
88 r600_context_flush(rctx
, flags
);
89 rctx
->b
.rings
.gfx
.flushing
= false;
90 r600_begin_new_cs(rctx
);
92 /* Re-enable render condition. */
94 ctx
->render_condition(ctx
, render_cond
, render_cond_cond
, render_cond_mode
);
97 rctx
->initial_gfx_cs_size
= rctx
->b
.rings
.gfx
.cs
->cdw
;
100 static void r600_flush_from_st(struct pipe_context
*ctx
,
101 struct pipe_fence_handle
**fence
,
104 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
107 fflags
= flags
& PIPE_FLUSH_END_OF_FRAME
? RADEON_FLUSH_END_OF_FRAME
: 0;
109 *fence
= rctx
->b
.ws
->cs_create_fence(rctx
->b
.rings
.gfx
.cs
);
111 /* flush gfx & dma ring, order does not matter as only one can be live */
112 if (rctx
->b
.rings
.dma
.cs
) {
113 rctx
->b
.rings
.dma
.flush(rctx
, fflags
);
115 rctx
->b
.rings
.gfx
.flush(rctx
, fflags
);
118 static void r600_flush_gfx_ring(void *ctx
, unsigned flags
)
120 r600_flush((struct pipe_context
*)ctx
, flags
);
123 static void r600_flush_dma_ring(void *ctx
, unsigned flags
)
125 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
126 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.dma
.cs
;
132 rctx
->b
.rings
.dma
.flushing
= true;
133 rctx
->b
.ws
->cs_flush(cs
, flags
, 0);
134 rctx
->b
.rings
.dma
.flushing
= false;
137 static void r600_flush_from_winsys(void *ctx
, unsigned flags
)
139 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
141 rctx
->b
.rings
.gfx
.flush(rctx
, flags
);
144 static void r600_flush_dma_from_winsys(void *ctx
, unsigned flags
)
146 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
148 rctx
->b
.rings
.dma
.flush(rctx
, flags
);
151 static void r600_destroy_context(struct pipe_context
*context
)
153 struct r600_context
*rctx
= (struct r600_context
*)context
;
155 r600_isa_destroy(rctx
->isa
);
157 r600_sb_context_destroy(rctx
->sb_context
);
159 pipe_resource_reference((struct pipe_resource
**)&rctx
->dummy_cmask
, NULL
);
160 pipe_resource_reference((struct pipe_resource
**)&rctx
->dummy_fmask
, NULL
);
162 if (rctx
->dummy_pixel_shader
) {
163 rctx
->b
.b
.delete_fs_state(&rctx
->b
.b
, rctx
->dummy_pixel_shader
);
165 if (rctx
->custom_dsa_flush
) {
166 rctx
->b
.b
.delete_depth_stencil_alpha_state(&rctx
->b
.b
, rctx
->custom_dsa_flush
);
168 if (rctx
->custom_blend_resolve
) {
169 rctx
->b
.b
.delete_blend_state(&rctx
->b
.b
, rctx
->custom_blend_resolve
);
171 if (rctx
->custom_blend_decompress
) {
172 rctx
->b
.b
.delete_blend_state(&rctx
->b
.b
, rctx
->custom_blend_decompress
);
174 if (rctx
->custom_blend_fastclear
) {
175 rctx
->b
.b
.delete_blend_state(&rctx
->b
.b
, rctx
->custom_blend_fastclear
);
177 util_unreference_framebuffer_state(&rctx
->framebuffer
.state
);
180 util_blitter_destroy(rctx
->blitter
);
182 if (rctx
->allocator_fetch_shader
) {
183 u_suballocator_destroy(rctx
->allocator_fetch_shader
);
186 r600_release_command_buffer(&rctx
->start_cs_cmd
);
188 FREE(rctx
->start_compute_cs_cmd
.buf
);
190 r600_common_context_cleanup(&rctx
->b
);
194 static struct pipe_context
*r600_create_context(struct pipe_screen
*screen
, void *priv
)
196 struct r600_context
*rctx
= CALLOC_STRUCT(r600_context
);
197 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
202 rctx
->b
.b
.screen
= screen
;
203 rctx
->b
.b
.priv
= priv
;
204 rctx
->b
.b
.destroy
= r600_destroy_context
;
205 rctx
->b
.b
.flush
= r600_flush_from_st
;
207 if (!r600_common_context_init(&rctx
->b
, &rscreen
->b
))
210 rctx
->screen
= rscreen
;
211 rctx
->keep_tiling_flags
= rscreen
->b
.info
.drm_minor
>= 12;
213 r600_init_blit_functions(rctx
);
215 if (rscreen
->b
.info
.has_uvd
) {
216 rctx
->b
.b
.create_video_codec
= r600_uvd_create_decoder
;
217 rctx
->b
.b
.create_video_buffer
= r600_video_buffer_create
;
219 rctx
->b
.b
.create_video_codec
= vl_create_decoder
;
220 rctx
->b
.b
.create_video_buffer
= vl_video_buffer_create
;
223 r600_init_common_state_functions(rctx
);
225 switch (rctx
->b
.chip_class
) {
228 r600_init_state_functions(rctx
);
229 r600_init_atom_start_cs(rctx
);
230 rctx
->custom_dsa_flush
= r600_create_db_flush_dsa(rctx
);
231 rctx
->custom_blend_resolve
= rctx
->b
.chip_class
== R700
? r700_create_resolve_blend(rctx
)
232 : r600_create_resolve_blend(rctx
);
233 rctx
->custom_blend_decompress
= r600_create_decompress_blend(rctx
);
234 rctx
->has_vertex_cache
= !(rctx
->b
.family
== CHIP_RV610
||
235 rctx
->b
.family
== CHIP_RV620
||
236 rctx
->b
.family
== CHIP_RS780
||
237 rctx
->b
.family
== CHIP_RS880
||
238 rctx
->b
.family
== CHIP_RV710
);
242 evergreen_init_state_functions(rctx
);
243 evergreen_init_atom_start_cs(rctx
);
244 evergreen_init_atom_start_compute_cs(rctx
);
245 rctx
->custom_dsa_flush
= evergreen_create_db_flush_dsa(rctx
);
246 rctx
->custom_blend_resolve
= evergreen_create_resolve_blend(rctx
);
247 rctx
->custom_blend_decompress
= evergreen_create_decompress_blend(rctx
);
248 rctx
->custom_blend_fastclear
= evergreen_create_fastclear_blend(rctx
);
249 rctx
->has_vertex_cache
= !(rctx
->b
.family
== CHIP_CEDAR
||
250 rctx
->b
.family
== CHIP_PALM
||
251 rctx
->b
.family
== CHIP_SUMO
||
252 rctx
->b
.family
== CHIP_SUMO2
||
253 rctx
->b
.family
== CHIP_CAICOS
||
254 rctx
->b
.family
== CHIP_CAYMAN
||
255 rctx
->b
.family
== CHIP_ARUBA
);
258 R600_ERR("Unsupported chip class %d.\n", rctx
->b
.chip_class
);
262 if (rscreen
->b
.trace_bo
) {
263 rctx
->b
.rings
.gfx
.cs
= rctx
->b
.ws
->cs_create(rctx
->b
.ws
, RING_GFX
, rscreen
->b
.trace_bo
->cs_buf
);
265 rctx
->b
.rings
.gfx
.cs
= rctx
->b
.ws
->cs_create(rctx
->b
.ws
, RING_GFX
, NULL
);
267 rctx
->b
.rings
.gfx
.flush
= r600_flush_gfx_ring
;
268 rctx
->b
.ws
->cs_set_flush_callback(rctx
->b
.rings
.gfx
.cs
, r600_flush_from_winsys
, rctx
);
269 rctx
->b
.rings
.gfx
.flushing
= false;
271 rctx
->b
.rings
.dma
.cs
= NULL
;
272 if (rscreen
->b
.info
.r600_has_dma
&& !(rscreen
->b
.debug_flags
& DBG_NO_ASYNC_DMA
)) {
273 rctx
->b
.rings
.dma
.cs
= rctx
->b
.ws
->cs_create(rctx
->b
.ws
, RING_DMA
, NULL
);
274 rctx
->b
.rings
.dma
.flush
= r600_flush_dma_ring
;
275 rctx
->b
.ws
->cs_set_flush_callback(rctx
->b
.rings
.dma
.cs
, r600_flush_dma_from_winsys
, rctx
);
276 rctx
->b
.rings
.dma
.flushing
= false;
279 rctx
->allocator_fetch_shader
= u_suballocator_create(&rctx
->b
.b
, 64 * 1024, 256,
280 0, PIPE_USAGE_STATIC
, FALSE
);
281 if (!rctx
->allocator_fetch_shader
)
284 rctx
->isa
= calloc(1, sizeof(struct r600_isa
));
285 if (!rctx
->isa
|| r600_isa_init(rctx
, rctx
->isa
))
288 rctx
->blitter
= util_blitter_create(&rctx
->b
.b
);
289 if (rctx
->blitter
== NULL
)
291 util_blitter_set_texture_multisample(rctx
->blitter
, rscreen
->has_msaa
);
292 rctx
->blitter
->draw_rectangle
= r600_draw_rectangle
;
294 r600_begin_new_cs(rctx
);
295 r600_query_init_backend_mask(&rctx
->b
); /* this emits commands and must be last */
297 rctx
->dummy_pixel_shader
=
298 util_make_fragment_cloneinput_shader(&rctx
->b
.b
, 0,
299 TGSI_SEMANTIC_GENERIC
,
300 TGSI_INTERPOLATE_CONSTANT
);
301 rctx
->b
.b
.bind_fs_state(&rctx
->b
.b
, rctx
->dummy_pixel_shader
);
306 r600_destroy_context(&rctx
->b
.b
);
314 static int r600_get_param(struct pipe_screen
* pscreen
, enum pipe_cap param
)
316 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
317 enum radeon_family family
= rscreen
->b
.family
;
320 /* Supported features (boolean caps). */
321 case PIPE_CAP_NPOT_TEXTURES
:
322 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
323 case PIPE_CAP_TWO_SIDED_STENCIL
:
324 case PIPE_CAP_ANISOTROPIC_FILTER
:
325 case PIPE_CAP_POINT_SPRITE
:
326 case PIPE_CAP_OCCLUSION_QUERY
:
327 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
328 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
329 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
330 case PIPE_CAP_TEXTURE_SWIZZLE
:
331 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
332 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
333 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
334 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
335 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
336 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
338 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
339 case PIPE_CAP_PRIMITIVE_RESTART
:
340 case PIPE_CAP_CONDITIONAL_RENDER
:
341 case PIPE_CAP_TEXTURE_BARRIER
:
342 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
343 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
344 case PIPE_CAP_TGSI_INSTANCEID
:
345 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
346 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
347 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
348 case PIPE_CAP_USER_INDEX_BUFFERS
:
349 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
350 case PIPE_CAP_COMPUTE
:
351 case PIPE_CAP_START_INSTANCE
:
352 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
353 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
354 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
355 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
356 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
359 case PIPE_CAP_TGSI_TEXCOORD
:
362 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
363 return MIN2(rscreen
->b
.info
.vram_size
, 0xFFFFFFFF);
365 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
366 return R600_MAP_BUFFER_ALIGNMENT
;
368 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
371 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
374 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
375 return family
>= CHIP_CEDAR
? 330 : 140;
377 /* Supported except the original R600. */
378 case PIPE_CAP_INDEP_BLEND_ENABLE
:
379 case PIPE_CAP_INDEP_BLEND_FUNC
:
380 /* R600 doesn't support per-MRT blends */
381 return family
== CHIP_R600
? 0 : 1;
383 /* Supported on Evergreen. */
384 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
385 case PIPE_CAP_CUBE_MAP_ARRAY
:
386 case PIPE_CAP_TGSI_VS_LAYER
:
387 return family
>= CHIP_CEDAR
? 1 : 0;
389 /* Unsupported features. */
390 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
391 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
392 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
393 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
394 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
395 case PIPE_CAP_USER_VERTEX_BUFFERS
:
399 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
400 return rscreen
->b
.has_streamout
? 4 : 0;
401 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
402 return rscreen
->b
.has_streamout
? 1 : 0;
403 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
404 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
408 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
409 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
410 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
411 if (family
>= CHIP_CEDAR
)
415 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
416 return rscreen
->b
.info
.drm_minor
>= 9 ?
417 (family
>= CHIP_CEDAR
? 16384 : 8192) : 0;
419 /* Render targets. */
420 case PIPE_CAP_MAX_RENDER_TARGETS
:
421 /* XXX some r6xx are buggy and can only do 4 */
424 case PIPE_CAP_MAX_VIEWPORTS
:
427 /* Timer queries, present when the clock frequency is non zero. */
428 case PIPE_CAP_QUERY_TIME_ELAPSED
:
429 return rscreen
->b
.info
.r600_clock_crystal_freq
!= 0;
430 case PIPE_CAP_QUERY_TIMESTAMP
:
431 return rscreen
->b
.info
.drm_minor
>= 20 &&
432 rscreen
->b
.info
.r600_clock_crystal_freq
!= 0;
434 case PIPE_CAP_MIN_TEXEL_OFFSET
:
437 case PIPE_CAP_MAX_TEXEL_OFFSET
:
440 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
441 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600
;
442 case PIPE_CAP_ENDIANNESS
:
443 return PIPE_ENDIAN_LITTLE
;
448 static int r600_get_shader_param(struct pipe_screen
* pscreen
, unsigned shader
, enum pipe_shader_cap param
)
450 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
454 case PIPE_SHADER_FRAGMENT
:
455 case PIPE_SHADER_VERTEX
:
456 case PIPE_SHADER_COMPUTE
:
458 case PIPE_SHADER_GEOMETRY
:
459 if (rscreen
->b
.chip_class
< EVERGREEN
)
463 /* XXX: support tessellation on Evergreen */
468 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
469 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
470 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
471 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
473 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
475 case PIPE_SHADER_CAP_MAX_INPUTS
:
477 case PIPE_SHADER_CAP_MAX_TEMPS
:
478 return 256; /* Max native temporaries. */
479 case PIPE_SHADER_CAP_MAX_ADDRS
:
480 /* XXX Isn't this equal to TEMPS? */
481 return 1; /* Max native address registers */
482 case PIPE_SHADER_CAP_MAX_CONSTS
:
483 return R600_MAX_CONST_BUFFER_SIZE
;
484 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
485 return R600_MAX_USER_CONST_BUFFERS
;
486 case PIPE_SHADER_CAP_MAX_PREDS
:
487 return 0; /* nothing uses this */
488 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
490 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
492 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
493 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
494 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
495 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
497 case PIPE_SHADER_CAP_SUBROUTINES
:
499 case PIPE_SHADER_CAP_INTEGERS
:
501 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
502 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
504 case PIPE_SHADER_CAP_PREFERRED_IR
:
505 if (shader
== PIPE_SHADER_COMPUTE
) {
506 return PIPE_SHADER_IR_LLVM
;
508 return PIPE_SHADER_IR_TGSI
;
514 static void r600_destroy_screen(struct pipe_screen
* pscreen
)
516 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
521 if (!radeon_winsys_unref(rscreen
->b
.ws
))
524 if (rscreen
->global_pool
) {
525 compute_memory_pool_delete(rscreen
->global_pool
);
528 r600_destroy_common_screen(&rscreen
->b
);
531 static struct pipe_resource
*r600_resource_create(struct pipe_screen
*screen
,
532 const struct pipe_resource
*templ
)
534 if (templ
->target
== PIPE_BUFFER
&&
535 (templ
->bind
& PIPE_BIND_GLOBAL
))
536 return r600_compute_global_buffer_create(screen
, templ
);
538 return r600_resource_create_common(screen
, templ
);
541 struct pipe_screen
*r600_screen_create(struct radeon_winsys
*ws
)
543 struct r600_screen
*rscreen
= CALLOC_STRUCT(r600_screen
);
545 if (rscreen
== NULL
) {
549 /* Set functions first. */
550 rscreen
->b
.b
.context_create
= r600_create_context
;
551 rscreen
->b
.b
.destroy
= r600_destroy_screen
;
552 rscreen
->b
.b
.get_param
= r600_get_param
;
553 rscreen
->b
.b
.get_shader_param
= r600_get_shader_param
;
554 rscreen
->b
.b
.resource_create
= r600_resource_create
;
556 if (!r600_common_screen_init(&rscreen
->b
, ws
)) {
561 if (rscreen
->b
.info
.chip_class
>= EVERGREEN
) {
562 rscreen
->b
.b
.is_format_supported
= evergreen_is_format_supported
;
564 rscreen
->b
.b
.is_format_supported
= r600_is_format_supported
;
567 rscreen
->b
.debug_flags
|= debug_get_flags_option("R600_DEBUG", r600_debug_options
, 0);
568 if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE
))
569 rscreen
->b
.debug_flags
|= DBG_COMPUTE
;
570 if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE
))
571 rscreen
->b
.debug_flags
|= DBG_FS
| DBG_VS
| DBG_GS
| DBG_PS
| DBG_CS
;
572 if (!debug_get_bool_option("R600_HYPERZ", TRUE
))
573 rscreen
->b
.debug_flags
|= DBG_NO_HYPERZ
;
574 if (!debug_get_bool_option("R600_LLVM", TRUE
))
575 rscreen
->b
.debug_flags
|= DBG_NO_LLVM
;
577 if (rscreen
->b
.family
== CHIP_UNKNOWN
) {
578 fprintf(stderr
, "r600: Unknown chipset 0x%04X\n", rscreen
->b
.info
.pci_id
);
583 /* Figure out streamout kernel support. */
584 switch (rscreen
->b
.chip_class
) {
586 if (rscreen
->b
.family
< CHIP_RS780
) {
587 rscreen
->b
.has_streamout
= rscreen
->b
.info
.drm_minor
>= 14;
589 rscreen
->b
.has_streamout
= rscreen
->b
.info
.drm_minor
>= 23;
593 rscreen
->b
.has_streamout
= rscreen
->b
.info
.drm_minor
>= 17;
597 rscreen
->b
.has_streamout
= rscreen
->b
.info
.drm_minor
>= 14;
600 rscreen
->b
.has_streamout
= FALSE
;
605 switch (rscreen
->b
.chip_class
) {
608 rscreen
->has_msaa
= rscreen
->b
.info
.drm_minor
>= 22;
609 rscreen
->has_compressed_msaa_texturing
= false;
612 rscreen
->has_msaa
= rscreen
->b
.info
.drm_minor
>= 19;
613 rscreen
->has_compressed_msaa_texturing
= rscreen
->b
.info
.drm_minor
>= 24;
616 rscreen
->has_msaa
= rscreen
->b
.info
.drm_minor
>= 19;
617 rscreen
->has_compressed_msaa_texturing
= true;
620 rscreen
->has_msaa
= FALSE
;
621 rscreen
->has_compressed_msaa_texturing
= false;
624 rscreen
->b
.has_cp_dma
= rscreen
->b
.info
.drm_minor
>= 27 &&
625 !(rscreen
->b
.debug_flags
& DBG_NO_CP_DMA
);
627 rscreen
->global_pool
= compute_memory_pool_new(rscreen
);
629 /* Create the auxiliary context. This must be done last. */
630 rscreen
->b
.aux_context
= rscreen
->b
.b
.context_create(&rscreen
->b
.b
, NULL
);
632 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
633 struct pipe_resource templ
= {};
636 templ
.height0
= 2048;
638 templ
.array_size
= 1;
639 templ
.target
= PIPE_TEXTURE_2D
;
640 templ
.format
= PIPE_FORMAT_R8G8B8A8_UNORM
;
641 templ
.usage
= PIPE_USAGE_STATIC
;
643 struct r600_resource
*res
= r600_resource(rscreen
->screen
.resource_create(&rscreen
->screen
, &templ
));
644 unsigned char *map
= ws
->buffer_map(res
->cs_buf
, NULL
, PIPE_TRANSFER_WRITE
);
648 r600_screen_clear_buffer(rscreen
, &res
->b
.b
, 4, 4, 0xCC);
649 r600_screen_clear_buffer(rscreen
, &res
->b
.b
, 8, 4, 0xDD);
650 r600_screen_clear_buffer(rscreen
, &res
->b
.b
, 12, 4, 0xEE);
651 r600_screen_clear_buffer(rscreen
, &res
->b
.b
, 20, 4, 0xFF);
652 r600_screen_clear_buffer(rscreen
, &res
->b
.b
, 32, 20, 0x87);
654 ws
->buffer_wait(res
->buf
, RADEON_USAGE_WRITE
);
657 for (i
= 0; i
< 256; i
++) {
658 printf("%02X", map
[i
]);
664 return &rscreen
->b
.b
;