src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25 #include "r600_isa.h"
  26 #include "evergreen_compute.h"
  27 #include "r600d.h"
  28
  29 #include "sb/sb_public.h"
  30
  31 #include <errno.h>
  32 #include "pipe/p_shader_tokens.h"
  33 #include "util/u_debug.h"
  34 #include "util/u_memory.h"
  35 #include "util/u_simple_shaders.h"
  36 #include "util/u_upload_mgr.h"
  37 #include "util/u_math.h"
  38 #include "vl/vl_decoder.h"
  39 #include "vl/vl_video_buffer.h"
  40 #include "radeon/radeon_video.h"
  41 #include "radeon/radeon_uvd.h"
  42 #include "os/os_time.h"
  43
  44 static const struct debug_named_value r600_debug_options[] = {
  45         /* features */
  46 #if defined(R600_USE_LLVM)
  47         { "llvm", DBG_LLVM, "Enable the LLVM shader compiler" },
  48 #endif
  49         { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
  50
  51         /* shader backend */
  52         { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
  53         { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
  54         { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
  55         { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
  56         { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
  57         { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
  58         { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
  59         { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
  60
  61         DEBUG_NAMED_VALUE_END /* must be last */
  62 };
  63
  64 /*
  65  * pipe_context
  66  */
  67
  68 static void r600_destroy_context(struct pipe_context *context)
  69 {
  70         struct r600_context *rctx = (struct r600_context *)context;
  71         unsigned sh;
  72
  73         r600_isa_destroy(rctx->isa);
  74
  75         r600_sb_context_destroy(rctx->sb_context);
  76
  77         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
  78         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
  79
  80         for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
  81                 rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, NULL);
  82                 free(rctx->driver_consts[sh].constants);
  83         }
  84
  85         if (rctx->fixed_func_tcs_shader)
  86                 rctx->b.b.delete_tcs_state(&rctx->b.b, rctx->fixed_func_tcs_shader);
  87
  88         if (rctx->dummy_pixel_shader) {
  89                 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
  90         }
  91         if (rctx->custom_dsa_flush) {
  92                 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
  93         }
  94         if (rctx->custom_blend_resolve) {
  95                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
  96         }
  97         if (rctx->custom_blend_decompress) {
  98                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
  99         }
 100         if (rctx->custom_blend_fastclear) {
 101                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
 102         }
 103         util_unreference_framebuffer_state(&rctx->framebuffer.state);
 104
 105         if (rctx->blitter) {
 106                 util_blitter_destroy(rctx->blitter);
 107         }
 108         if (rctx->allocator_fetch_shader) {
 109                 u_suballocator_destroy(rctx->allocator_fetch_shader);
 110         }
 111
 112         r600_release_command_buffer(&rctx->start_cs_cmd);
 113
 114         FREE(rctx->start_compute_cs_cmd.buf);
 115
 116         r600_common_context_cleanup(&rctx->b);
 117         FREE(rctx);
 118 }
 119
 120 static struct pipe_context *r600_create_context(struct pipe_screen *screen,
 121                                                 void *priv, unsigned flags)
 122 {
 123         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 124         struct r600_screen* rscreen = (struct r600_screen *)screen;
 125         struct radeon_winsys *ws = rscreen->b.ws;
 126
 127         if (!rctx)
 128                 return NULL;
 129
 130         rctx->b.b.screen = screen;
 131         rctx->b.b.priv = priv;
 132         rctx->b.b.destroy = r600_destroy_context;
 133         rctx->b.set_atom_dirty = (void *)r600_set_atom_dirty;
 134
 135         if (!r600_common_context_init(&rctx->b, &rscreen->b))
 136                 goto fail;
 137
 138         rctx->screen = rscreen;
 139         rctx->keep_tiling_flags = rscreen->b.info.drm_minor >= 12;
 140
 141         r600_init_blit_functions(rctx);
 142
 143         if (rscreen->b.info.has_uvd) {
 144                 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
 145                 rctx->b.b.create_video_buffer = r600_video_buffer_create;
 146         } else {
 147                 rctx->b.b.create_video_codec = vl_create_decoder;
 148                 rctx->b.b.create_video_buffer = vl_video_buffer_create;
 149         }
 150
 151         r600_init_common_state_functions(rctx);
 152
 153         switch (rctx->b.chip_class) {
 154         case R600:
 155         case R700:
 156                 r600_init_state_functions(rctx);
 157                 r600_init_atom_start_cs(rctx);
 158                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 159                 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
 160                                                                       : r600_create_resolve_blend(rctx);
 161                 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
 162                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
 163                                            rctx->b.family == CHIP_RV620 ||
 164                                            rctx->b.family == CHIP_RS780 ||
 165                                            rctx->b.family == CHIP_RS880 ||
 166                                            rctx->b.family == CHIP_RV710);
 167                 break;
 168         case EVERGREEN:
 169         case CAYMAN:
 170                 evergreen_init_state_functions(rctx);
 171                 evergreen_init_atom_start_cs(rctx);
 172                 evergreen_init_atom_start_compute_cs(rctx);
 173                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 174                 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
 175                 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
 176                 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
 177                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
 178                                            rctx->b.family == CHIP_PALM ||
 179                                            rctx->b.family == CHIP_SUMO ||
 180                                            rctx->b.family == CHIP_SUMO2 ||
 181                                            rctx->b.family == CHIP_CAICOS ||
 182                                            rctx->b.family == CHIP_CAYMAN ||
 183                                            rctx->b.family == CHIP_ARUBA);
 184                 break;
 185         default:
 186                 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
 187                 goto fail;
 188         }
 189
 190         rctx->b.gfx.cs = ws->cs_create(rctx->b.ctx, RING_GFX,
 191                                        r600_context_gfx_flush, rctx,
 192                                        rscreen->b.trace_bo ?
 193                                                rscreen->b.trace_bo->buf : NULL);
 194         rctx->b.gfx.flush = r600_context_gfx_flush;
 195
 196         rctx->allocator_fetch_shader = u_suballocator_create(&rctx->b.b, 64 * 1024, 256,
 197                                                              0, PIPE_USAGE_DEFAULT, FALSE);
 198         if (!rctx->allocator_fetch_shader)
 199                 goto fail;
 200
 201         rctx->isa = calloc(1, sizeof(struct r600_isa));
 202         if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
 203                 goto fail;
 204
 205         if (rscreen->b.debug_flags & DBG_FORCE_DMA)
 206                 rctx->b.b.resource_copy_region = rctx->b.dma_copy;
 207
 208         rctx->blitter = util_blitter_create(&rctx->b.b);
 209         if (rctx->blitter == NULL)
 210                 goto fail;
 211         util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
 212         rctx->blitter->draw_rectangle = r600_draw_rectangle;
 213
 214         r600_begin_new_cs(rctx);
 215         r600_query_init_backend_mask(&rctx->b); /* this emits commands and must be last */
 216
 217         rctx->dummy_pixel_shader =
 218                 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
 219                                                      TGSI_SEMANTIC_GENERIC,
 220                                                      TGSI_INTERPOLATE_CONSTANT);
 221         rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 222
 223         return &rctx->b.b;
 224
 225 fail:
 226         r600_destroy_context(&rctx->b.b);
 227         return NULL;
 228 }
 229
 230 /*
 231  * pipe_screen
 232  */
 233
 234 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 235 {
 236         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 237         enum radeon_family family = rscreen->b.family;
 238
 239         switch (param) {
 240         /* Supported features (boolean caps). */
 241         case PIPE_CAP_NPOT_TEXTURES:
 242         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 243         case PIPE_CAP_TWO_SIDED_STENCIL:
 244         case PIPE_CAP_ANISOTROPIC_FILTER:
 245         case PIPE_CAP_POINT_SPRITE:
 246         case PIPE_CAP_OCCLUSION_QUERY:
 247         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 248         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 249         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 250         case PIPE_CAP_TEXTURE_SWIZZLE:
 251         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 252         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 253         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 254         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 255         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 256         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 257         case PIPE_CAP_SM3:
 258         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 259         case PIPE_CAP_PRIMITIVE_RESTART:
 260         case PIPE_CAP_CONDITIONAL_RENDER:
 261         case PIPE_CAP_TEXTURE_BARRIER:
 262         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 263         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 264         case PIPE_CAP_TGSI_INSTANCEID:
 265         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 266         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 267         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 268         case PIPE_CAP_USER_INDEX_BUFFERS:
 269         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 270         case PIPE_CAP_START_INSTANCE:
 271         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 272         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 273         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 274         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 275         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 276         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 277         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 278         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 279         case PIPE_CAP_SAMPLE_SHADING:
 280         case PIPE_CAP_CLIP_HALFZ:
 281         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 282         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 283         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 284         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 285         case PIPE_CAP_TGSI_TXQS:
 286         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 287         case PIPE_CAP_INVALIDATE_BUFFER:
 288                 return 1;
 289
 290         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 291                 return rscreen->b.info.drm_major == 2 && rscreen->b.info.drm_minor >= 43;
 292
 293         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 294                 return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;
 295
 296         case PIPE_CAP_COMPUTE:
 297                 return rscreen->b.chip_class > R700;
 298
 299         case PIPE_CAP_TGSI_TEXCOORD:
 300                 return 0;
 301
 302         case PIPE_CAP_FAKE_SW_MSAA:
 303                 return 0;
 304
 305         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 306                 return MIN2(rscreen->b.info.vram_size, 0xFFFFFFFF);
 307
 308         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 309                 return R600_MAP_BUFFER_ALIGNMENT;
 310
 311         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 312                 return 256;
 313
 314         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 315                 return 1;
 316
 317         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 318                 if (family >= CHIP_CEDAR)
 319                    return 410;
 320                 /* pre-evergreen geom shaders need newer kernel */
 321                 if (rscreen->b.info.drm_minor >= 37)
 322                    return 330;
 323                 return 140;
 324
 325         /* Supported except the original R600. */
 326         case PIPE_CAP_INDEP_BLEND_ENABLE:
 327         case PIPE_CAP_INDEP_BLEND_FUNC:
 328                 /* R600 doesn't support per-MRT blends */
 329                 return family == CHIP_R600 ? 0 : 1;
 330
 331         /* Supported on Evergreen. */
 332         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 333         case PIPE_CAP_CUBE_MAP_ARRAY:
 334         case PIPE_CAP_TEXTURE_GATHER_SM5:
 335         case PIPE_CAP_TEXTURE_QUERY_LOD:
 336         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 337         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 338                 return family >= CHIP_CEDAR ? 1 : 0;
 339         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 340                 return family >= CHIP_CEDAR ? 4 : 0;
 341         case PIPE_CAP_DRAW_INDIRECT:
 342                 /* kernel command checker support is also required */
 343                 return family >= CHIP_CEDAR && rscreen->b.info.drm_minor >= 41;
 344
 345         /* Unsupported features. */
 346         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 347         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 348         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 349         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 350         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 351         case PIPE_CAP_USER_VERTEX_BUFFERS:
 352         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 353         case PIPE_CAP_VERTEXID_NOBASE:
 354         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 355         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 356         case PIPE_CAP_SHAREABLE_SHADERS:
 357         case PIPE_CAP_CLEAR_TEXTURE:
 358         case PIPE_CAP_DRAW_PARAMETERS:
 359         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 360         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 361         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 362         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 363         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 364         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 365         case PIPE_CAP_GENERATE_MIPMAP:
 366         case PIPE_CAP_STRING_MARKER:
 367                 return 0;
 368
 369         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 370                 if (family >= CHIP_CEDAR)
 371                         return 30;
 372                 else
 373                         return 0;
 374         /* Stream output. */
 375         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 376                 return rscreen->b.has_streamout ? 4 : 0;
 377         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 378                 return rscreen->b.has_streamout ? 1 : 0;
 379         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 380         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 381                 return 32*4;
 382
 383         /* Geometry shader output. */
 384         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 385                 return 1024;
 386         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 387                 return 16384;
 388         case PIPE_CAP_MAX_VERTEX_STREAMS:
 389                 return family >= CHIP_CEDAR ? 4 : 1;
 390
 391         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 392                 return 2047;
 393
 394         /* Texturing. */
 395         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 396         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 397                 if (family >= CHIP_CEDAR)
 398                         return 15;
 399                 else
 400                         return 14;
 401         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 402                 /* textures support 8192, but layered rendering supports 2048 */
 403                 return 12;
 404         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 405                 /* textures support 8192, but layered rendering supports 2048 */
 406                 return rscreen->b.info.drm_minor >= 9 ? 2048 : 0;
 407
 408         /* Render targets. */
 409         case PIPE_CAP_MAX_RENDER_TARGETS:
 410                 /* XXX some r6xx are buggy and can only do 4 */
 411                 return 8;
 412
 413         case PIPE_CAP_MAX_VIEWPORTS:
 414                 return R600_MAX_VIEWPORTS;
 415
 416         /* Timer queries, present when the clock frequency is non zero. */
 417         case PIPE_CAP_QUERY_TIME_ELAPSED:
 418                 return rscreen->b.info.r600_clock_crystal_freq != 0;
 419         case PIPE_CAP_QUERY_TIMESTAMP:
 420                 return rscreen->b.info.drm_minor >= 20 &&
 421                        rscreen->b.info.r600_clock_crystal_freq != 0;
 422
 423         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 424         case PIPE_CAP_MIN_TEXEL_OFFSET:
 425                 return -8;
 426
 427         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 428         case PIPE_CAP_MAX_TEXEL_OFFSET:
 429                 return 7;
 430
 431         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 432                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 433         case PIPE_CAP_ENDIANNESS:
 434                 return PIPE_ENDIAN_LITTLE;
 435
 436         case PIPE_CAP_VENDOR_ID:
 437                 return 0x1002;
 438         case PIPE_CAP_DEVICE_ID:
 439                 return rscreen->b.info.pci_id;
 440         case PIPE_CAP_ACCELERATED:
 441                 return 1;
 442         case PIPE_CAP_VIDEO_MEMORY:
 443                 return rscreen->b.info.vram_size >> 20;
 444         case PIPE_CAP_UMA:
 445                 return 0;
 446         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 447                 return rscreen->b.chip_class >= R700;
 448         }
 449         return 0;
 450 }
 451
 452 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 453 {
 454         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 455
 456         switch(shader)
 457         {
 458         case PIPE_SHADER_FRAGMENT:
 459         case PIPE_SHADER_VERTEX:
 460         case PIPE_SHADER_COMPUTE:
 461                 break;
 462         case PIPE_SHADER_GEOMETRY:
 463                 if (rscreen->b.family >= CHIP_CEDAR)
 464                         break;
 465                 /* pre-evergreen geom shaders need newer kernel */
 466                 if (rscreen->b.info.drm_minor >= 37)
 467                         break;
 468                 return 0;
 469         case PIPE_SHADER_TESS_CTRL:
 470         case PIPE_SHADER_TESS_EVAL:
 471                 if (rscreen->b.family >= CHIP_CEDAR)
 472                         break;
 473         default:
 474                 return 0;
 475         }
 476
 477         switch (param) {
 478         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 479         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 480         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 481         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 482                 return 16384;
 483         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 484                 return 32;
 485         case PIPE_SHADER_CAP_MAX_INPUTS:
 486                 return shader == PIPE_SHADER_VERTEX ? 16 : 32;
 487         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 488                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 489         case PIPE_SHADER_CAP_MAX_TEMPS:
 490                 return 256; /* Max native temporaries. */
 491         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 492                 if (shader == PIPE_SHADER_COMPUTE) {
 493                         uint64_t max_const_buffer_size;
 494                         pscreen->get_compute_param(pscreen,
 495                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 496                                 &max_const_buffer_size);
 497                         return max_const_buffer_size;
 498
 499                 } else {
 500                         return R600_MAX_CONST_BUFFER_SIZE;
 501                 }
 502         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 503                 return R600_MAX_USER_CONST_BUFFERS;
 504         case PIPE_SHADER_CAP_MAX_PREDS:
 505                 return 0; /* nothing uses this */
 506         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 507                 return 1;
 508         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 509                 return 1;
 510         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 511         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 512         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 513         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 514                 return 1;
 515         case PIPE_SHADER_CAP_SUBROUTINES:
 516                 return 0;
 517         case PIPE_SHADER_CAP_INTEGERS:
 518         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 519                 return 1;
 520         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 521         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 522                 return 16;
 523         case PIPE_SHADER_CAP_PREFERRED_IR:
 524                 if (shader == PIPE_SHADER_COMPUTE) {
 525 #if HAVE_LLVM < 0x0306
 526                         return PIPE_SHADER_IR_LLVM;
 527 #else
 528                         return PIPE_SHADER_IR_NATIVE;
 529 #endif
 530                 } else {
 531                         return PIPE_SHADER_IR_TGSI;
 532                 }
 533         case PIPE_SHADER_CAP_DOUBLES:
 534                 if (rscreen->b.family == CHIP_CYPRESS ||
 535                         rscreen->b.family == CHIP_CAYMAN || rscreen->b.family == CHIP_ARUBA)
 536                         return 1;
 537                 return 0;
 538         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 539         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 540         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 541         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 542                 return 0;
 543         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 544                 /* due to a bug in the shader compiler, some loops hang
 545                  * if they are not unrolled, see:
 546                  *    https://bugs.freedesktop.org/show_bug.cgi?id=86720
 547                  */
 548                 return 255;
 549         }
 550         return 0;
 551 }
 552
 553 static void r600_destroy_screen(struct pipe_screen* pscreen)
 554 {
 555         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 556
 557         if (!rscreen)
 558                 return;
 559
 560         if (!rscreen->b.ws->unref(rscreen->b.ws))
 561                 return;
 562
 563         if (rscreen->global_pool) {
 564                 compute_memory_pool_delete(rscreen->global_pool);
 565         }
 566
 567         r600_destroy_common_screen(&rscreen->b);
 568 }
 569
 570 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
 571                                                   const struct pipe_resource *templ)
 572 {
 573         if (templ->target == PIPE_BUFFER &&
 574             (templ->bind & PIPE_BIND_GLOBAL))
 575                 return r600_compute_global_buffer_create(screen, templ);
 576
 577         return r600_resource_create_common(screen, templ);
 578 }
 579
 580 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 581 {
 582         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 583
 584         if (!rscreen) {
 585                 return NULL;
 586         }
 587
 588         /* Set functions first. */
 589         rscreen->b.b.context_create = r600_create_context;
 590         rscreen->b.b.destroy = r600_destroy_screen;
 591         rscreen->b.b.get_param = r600_get_param;
 592         rscreen->b.b.get_shader_param = r600_get_shader_param;
 593         rscreen->b.b.resource_create = r600_resource_create;
 594
 595         if (!r600_common_screen_init(&rscreen->b, ws)) {
 596                 FREE(rscreen);
 597                 return NULL;
 598         }
 599
 600         if (rscreen->b.info.chip_class >= EVERGREEN) {
 601                 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
 602         } else {
 603                 rscreen->b.b.is_format_supported = r600_is_format_supported;
 604         }
 605
 606         rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
 607         if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
 608                 rscreen->b.debug_flags |= DBG_COMPUTE;
 609         if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
 610                 rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS | DBG_TCS | DBG_TES;
 611         if (!debug_get_bool_option("R600_HYPERZ", TRUE))
 612                 rscreen->b.debug_flags |= DBG_NO_HYPERZ;
 613         if (debug_get_bool_option("R600_LLVM", FALSE))
 614                 rscreen->b.debug_flags |= DBG_LLVM;
 615
 616         if (rscreen->b.family == CHIP_UNKNOWN) {
 617                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
 618                 FREE(rscreen);
 619                 return NULL;
 620         }
 621
 622         /* Figure out streamout kernel support. */
 623         switch (rscreen->b.chip_class) {
 624         case R600:
 625                 if (rscreen->b.family < CHIP_RS780) {
 626                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 627                 } else {
 628                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
 629                 }
 630                 break;
 631         case R700:
 632                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
 633                 break;
 634         case EVERGREEN:
 635         case CAYMAN:
 636                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 637                 break;
 638         default:
 639                 rscreen->b.has_streamout = FALSE;
 640                 break;
 641         }
 642
 643         /* MSAA support. */
 644         switch (rscreen->b.chip_class) {
 645         case R600:
 646         case R700:
 647                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
 648                 rscreen->has_compressed_msaa_texturing = false;
 649                 break;
 650         case EVERGREEN:
 651                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 652                 rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
 653                 break;
 654         case CAYMAN:
 655                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 656                 rscreen->has_compressed_msaa_texturing = true;
 657                 break;
 658         default:
 659                 rscreen->has_msaa = FALSE;
 660                 rscreen->has_compressed_msaa_texturing = false;
 661         }
 662
 663         rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
 664                               !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
 665
 666         rscreen->global_pool = compute_memory_pool_new(rscreen);
 667
 668         /* Create the auxiliary context. This must be done last. */
 669         rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL, 0);
 670
 671 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
 672         struct pipe_resource templ = {};
 673
 674         templ.width0 = 4;
 675         templ.height0 = 2048;
 676         templ.depth0 = 1;
 677         templ.array_size = 1;
 678         templ.target = PIPE_TEXTURE_2D;
 679         templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
 680         templ.usage = PIPE_USAGE_DEFAULT;
 681
 682         struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
 683         unsigned char *map = ws->buffer_map(res->buf, NULL, PIPE_TRANSFER_WRITE);
 684
 685         memset(map, 0, 256);
 686
 687         r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
 688         r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
 689         r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
 690         r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
 691         r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
 692
 693         ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
 694
 695         int i;
 696         for (i = 0; i < 256; i++) {
 697                 printf("%02X", map[i]);
 698                 if (i % 16 == 15)
 699                         printf("\n");
 700         }
 701 #endif
 702
 703         return &rscreen->b.b;
 704 }