2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "r600_pipe.h"
24 #include "r600_public.h"
27 #include "pipe/p_shader_tokens.h"
28 #include "util/u_blitter.h"
29 #include "util/u_format_s3tc.h"
30 #include "util/u_simple_shaders.h"
31 #include "vl/vl_decoder.h"
32 #include "vl/vl_video_buffer.h"
33 #include "os/os_time.h"
38 static struct r600_fence
*r600_create_fence(struct r600_context
*rctx
)
40 struct r600_screen
*rscreen
= rctx
->screen
;
41 struct r600_fence
*fence
= NULL
;
43 pipe_mutex_lock(rscreen
->fences
.mutex
);
45 if (!rscreen
->fences
.bo
) {
46 /* Create the shared buffer object */
47 rscreen
->fences
.bo
= (struct r600_resource
*)
48 pipe_buffer_create(&rscreen
->screen
, PIPE_BIND_CUSTOM
,
49 PIPE_USAGE_STAGING
, 4096);
50 if (!rscreen
->fences
.bo
) {
51 R600_ERR("r600: failed to create bo for fence objects\n");
54 rscreen
->fences
.data
= rctx
->ws
->buffer_map(rscreen
->fences
.bo
->buf
,
56 PIPE_TRANSFER_READ_WRITE
);
59 if (!LIST_IS_EMPTY(&rscreen
->fences
.pool
)) {
60 struct r600_fence
*entry
;
62 /* Try to find a freed fence that has been signalled */
63 LIST_FOR_EACH_ENTRY(entry
, &rscreen
->fences
.pool
, head
) {
64 if (rscreen
->fences
.data
[entry
->index
] != 0) {
65 LIST_DELINIT(&entry
->head
);
73 /* Allocate a new fence */
74 struct r600_fence_block
*block
;
77 if ((rscreen
->fences
.next_index
+ 1) >= 1024) {
78 R600_ERR("r600: too many concurrent fences\n");
82 index
= rscreen
->fences
.next_index
++;
84 if (!(index
% FENCE_BLOCK_SIZE
)) {
85 /* Allocate a new block */
86 block
= CALLOC_STRUCT(r600_fence_block
);
90 LIST_ADD(&block
->head
, &rscreen
->fences
.blocks
);
92 block
= LIST_ENTRY(struct r600_fence_block
, rscreen
->fences
.blocks
.next
, head
);
95 fence
= &block
->fences
[index
% FENCE_BLOCK_SIZE
];
99 pipe_reference_init(&fence
->reference
, 1);
101 rscreen
->fences
.data
[fence
->index
] = 0;
102 r600_context_emit_fence(rctx
, rscreen
->fences
.bo
, fence
->index
, 1);
104 /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
105 fence
->sleep_bo
= (struct r600_resource
*)
106 pipe_buffer_create(&rctx
->screen
->screen
, PIPE_BIND_CUSTOM
,
107 PIPE_USAGE_STAGING
, 1);
108 /* Add the fence as a dummy relocation. */
109 r600_context_bo_reloc(rctx
, fence
->sleep_bo
, RADEON_USAGE_READWRITE
);
112 pipe_mutex_unlock(rscreen
->fences
.mutex
);
117 void r600_flush(struct pipe_context
*ctx
, struct pipe_fence_handle
**fence
,
120 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
121 struct r600_fence
**rfence
= (struct r600_fence
**)fence
;
122 struct pipe_query
*render_cond
= NULL
;
123 unsigned render_cond_mode
= 0;
126 *rfence
= r600_create_fence(rctx
);
128 /* Disable render condition. */
129 if (rctx
->current_render_cond
) {
130 render_cond
= rctx
->current_render_cond
;
131 render_cond_mode
= rctx
->current_render_cond_mode
;
132 ctx
->render_condition(ctx
, NULL
, 0);
135 r600_context_flush(rctx
, flags
);
137 /* Re-enable render condition. */
139 ctx
->render_condition(ctx
, render_cond
, render_cond_mode
);
143 static void r600_flush_from_st(struct pipe_context
*ctx
,
144 struct pipe_fence_handle
**fence
)
146 r600_flush(ctx
, fence
, 0);
149 static void r600_flush_from_winsys(void *ctx
, unsigned flags
)
151 r600_flush((struct pipe_context
*)ctx
, NULL
, flags
);
154 static void r600_update_num_contexts(struct r600_screen
*rscreen
, int diff
)
156 pipe_mutex_lock(rscreen
->mutex_num_contexts
);
158 rscreen
->num_contexts
++;
160 if (rscreen
->num_contexts
> 1)
161 util_slab_set_thread_safety(&rscreen
->pool_buffers
,
162 UTIL_SLAB_MULTITHREADED
);
164 rscreen
->num_contexts
--;
166 if (rscreen
->num_contexts
<= 1)
167 util_slab_set_thread_safety(&rscreen
->pool_buffers
,
168 UTIL_SLAB_SINGLETHREADED
);
170 pipe_mutex_unlock(rscreen
->mutex_num_contexts
);
173 static void r600_destroy_context(struct pipe_context
*context
)
175 struct r600_context
*rctx
= (struct r600_context
*)context
;
177 if (rctx
->dummy_pixel_shader
) {
178 rctx
->context
.delete_fs_state(&rctx
->context
, rctx
->dummy_pixel_shader
);
180 if (rctx
->custom_dsa_flush
) {
181 rctx
->context
.delete_depth_stencil_alpha_state(&rctx
->context
, rctx
->custom_dsa_flush
);
183 util_unreference_framebuffer_state(&rctx
->framebuffer
);
185 r600_context_fini(rctx
);
188 util_blitter_destroy(rctx
->blitter
);
190 for (int i
= 0; i
< R600_PIPE_NSTATES
; i
++) {
191 free(rctx
->states
[i
]);
194 if (rctx
->vbuf_mgr
) {
195 u_vbuf_destroy(rctx
->vbuf_mgr
);
197 util_slab_destroy(&rctx
->pool_transfers
);
199 r600_update_num_contexts(rctx
->screen
, -1);
201 r600_release_command_buffer(&rctx
->start_cs_cmd
);
204 rctx
->ws
->cs_destroy(rctx
->cs
);
211 static struct pipe_context
*r600_create_context(struct pipe_screen
*screen
, void *priv
)
213 struct r600_context
*rctx
= CALLOC_STRUCT(r600_context
);
214 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
219 util_slab_create(&rctx
->pool_transfers
,
220 sizeof(struct pipe_transfer
), 64,
221 UTIL_SLAB_SINGLETHREADED
);
223 r600_update_num_contexts(rscreen
, 1);
225 rctx
->context
.screen
= screen
;
226 rctx
->context
.priv
= priv
;
227 rctx
->context
.destroy
= r600_destroy_context
;
228 rctx
->context
.flush
= r600_flush_from_st
;
230 /* Easy accessing of screen/winsys. */
231 rctx
->screen
= rscreen
;
232 rctx
->ws
= rscreen
->ws
;
233 rctx
->family
= rscreen
->family
;
234 rctx
->chip_class
= rscreen
->chip_class
;
236 LIST_INITHEAD(&rctx
->dirty_states
);
237 LIST_INITHEAD(&rctx
->active_timer_queries
);
238 LIST_INITHEAD(&rctx
->active_nontimer_queries
);
239 LIST_INITHEAD(&rctx
->dirty
);
240 LIST_INITHEAD(&rctx
->resource_dirty
);
241 LIST_INITHEAD(&rctx
->enable_list
);
243 rctx
->range
= CALLOC(NUM_RANGES
, sizeof(struct r600_range
));
247 r600_init_blit_functions(rctx
);
248 r600_init_query_functions(rctx
);
249 r600_init_context_resource_functions(rctx
);
250 r600_init_surface_functions(rctx
);
251 rctx
->context
.draw_vbo
= r600_draw_vbo
;
253 rctx
->context
.create_video_decoder
= vl_create_decoder
;
254 rctx
->context
.create_video_buffer
= vl_video_buffer_create
;
256 r600_init_common_atoms(rctx
);
258 switch (rctx
->chip_class
) {
261 r600_init_state_functions(rctx
);
262 r600_init_atom_start_cs(rctx
);
263 if (r600_context_init(rctx
))
265 rctx
->custom_dsa_flush
= r600_create_db_flush_dsa(rctx
);
269 evergreen_init_state_functions(rctx
);
270 evergreen_init_atom_start_cs(rctx
);
271 if (evergreen_context_init(rctx
))
273 rctx
->custom_dsa_flush
= evergreen_create_db_flush_dsa(rctx
);
276 R600_ERR("Unsupported chip class %d.\n", rctx
->chip_class
);
280 rctx
->cs
= rctx
->ws
->cs_create(rctx
->ws
);
281 rctx
->ws
->cs_set_flush_callback(rctx
->cs
, r600_flush_from_winsys
, rctx
);
282 r600_emit_atom(rctx
, &rctx
->start_cs_cmd
.atom
);
284 rctx
->vbuf_mgr
= u_vbuf_create(&rctx
->context
, 1024 * 1024, 256,
285 PIPE_BIND_VERTEX_BUFFER
|
286 PIPE_BIND_INDEX_BUFFER
|
287 PIPE_BIND_CONSTANT_BUFFER
,
288 U_VERTEX_FETCH_DWORD_ALIGNED
);
291 rctx
->vbuf_mgr
->caps
.format_fixed32
= 0;
293 rctx
->blitter
= util_blitter_create(&rctx
->context
);
294 if (rctx
->blitter
== NULL
)
297 r600_get_backend_mask(rctx
); /* this emits commands and must be last */
299 if (rctx
->chip_class
== R600
)
300 r600_set_max_scissor(rctx
);
302 rctx
->dummy_pixel_shader
=
303 util_make_fragment_cloneinput_shader(&rctx
->context
, 0,
304 TGSI_SEMANTIC_GENERIC
,
305 TGSI_INTERPOLATE_CONSTANT
);
306 rctx
->context
.bind_fs_state(&rctx
->context
, rctx
->dummy_pixel_shader
);
308 return &rctx
->context
;
311 r600_destroy_context(&rctx
->context
);
318 static const char* r600_get_vendor(struct pipe_screen
* pscreen
)
323 static const char *r600_get_family_name(enum radeon_family family
)
326 case CHIP_R600
: return "AMD R600";
327 case CHIP_RV610
: return "AMD RV610";
328 case CHIP_RV630
: return "AMD RV630";
329 case CHIP_RV670
: return "AMD RV670";
330 case CHIP_RV620
: return "AMD RV620";
331 case CHIP_RV635
: return "AMD RV635";
332 case CHIP_RS780
: return "AMD RS780";
333 case CHIP_RS880
: return "AMD RS880";
334 case CHIP_RV770
: return "AMD RV770";
335 case CHIP_RV730
: return "AMD RV730";
336 case CHIP_RV710
: return "AMD RV710";
337 case CHIP_RV740
: return "AMD RV740";
338 case CHIP_CEDAR
: return "AMD CEDAR";
339 case CHIP_REDWOOD
: return "AMD REDWOOD";
340 case CHIP_JUNIPER
: return "AMD JUNIPER";
341 case CHIP_CYPRESS
: return "AMD CYPRESS";
342 case CHIP_HEMLOCK
: return "AMD HEMLOCK";
343 case CHIP_PALM
: return "AMD PALM";
344 case CHIP_SUMO
: return "AMD SUMO";
345 case CHIP_SUMO2
: return "AMD SUMO2";
346 case CHIP_BARTS
: return "AMD BARTS";
347 case CHIP_TURKS
: return "AMD TURKS";
348 case CHIP_CAICOS
: return "AMD CAICOS";
349 case CHIP_CAYMAN
: return "AMD CAYMAN";
350 default: return "AMD unknown";
354 static const char* r600_get_name(struct pipe_screen
* pscreen
)
356 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
358 return r600_get_family_name(rscreen
->family
);
361 static int r600_get_param(struct pipe_screen
* pscreen
, enum pipe_cap param
)
363 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
364 enum radeon_family family
= rscreen
->family
;
367 /* Supported features (boolean caps). */
368 case PIPE_CAP_NPOT_TEXTURES
:
369 case PIPE_CAP_TWO_SIDED_STENCIL
:
370 case PIPE_CAP_DUAL_SOURCE_BLEND
:
371 case PIPE_CAP_ANISOTROPIC_FILTER
:
372 case PIPE_CAP_POINT_SPRITE
:
373 case PIPE_CAP_OCCLUSION_QUERY
:
374 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
375 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
376 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
377 case PIPE_CAP_TEXTURE_SWIZZLE
:
378 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE
:
379 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
380 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
381 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
382 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
383 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
384 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
386 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
387 case PIPE_CAP_PRIMITIVE_RESTART
:
388 case PIPE_CAP_CONDITIONAL_RENDER
:
389 case PIPE_CAP_TEXTURE_BARRIER
:
390 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
391 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
394 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
395 return debug_get_bool_option("R600_GLSL130", FALSE
) ? 130 : 120;
397 /* Supported except the original R600. */
398 case PIPE_CAP_INDEP_BLEND_ENABLE
:
399 case PIPE_CAP_INDEP_BLEND_FUNC
:
400 /* R600 doesn't support per-MRT blends */
401 return family
== CHIP_R600
? 0 : 1;
403 /* Supported on Evergreen. */
404 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
405 return family
>= CHIP_CEDAR
? 1 : 0;
407 /* Unsupported features. */
408 case PIPE_CAP_TGSI_INSTANCEID
:
409 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
410 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
411 case PIPE_CAP_SCALED_RESOLVE
:
412 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS
:
413 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
414 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
415 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
419 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
420 return rscreen
->info
.r600_has_streamout
? 4 : 0;
421 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
422 return rscreen
->info
.r600_has_streamout
? 1 : 0;
423 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
424 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
428 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
429 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
430 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
431 if (family
>= CHIP_CEDAR
)
435 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
436 return rscreen
->info
.drm_minor
>= 9 ?
437 (family
>= CHIP_CEDAR
? 16384 : 8192) : 0;
438 case PIPE_CAP_MAX_COMBINED_SAMPLERS
:
441 /* Render targets. */
442 case PIPE_CAP_MAX_RENDER_TARGETS
:
443 /* XXX some r6xx are buggy and can only do 4 */
446 /* Timer queries, present when the clock frequency is non zero. */
447 case PIPE_CAP_TIMER_QUERY
:
448 return rscreen
->info
.r600_clock_crystal_freq
!= 0;
450 case PIPE_CAP_MIN_TEXEL_OFFSET
:
453 case PIPE_CAP_MAX_TEXEL_OFFSET
:
459 static float r600_get_paramf(struct pipe_screen
* pscreen
,
460 enum pipe_capf param
)
462 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
463 enum radeon_family family
= rscreen
->family
;
466 case PIPE_CAPF_MAX_LINE_WIDTH
:
467 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
468 case PIPE_CAPF_MAX_POINT_WIDTH
:
469 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
470 if (family
>= CHIP_CEDAR
)
474 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
476 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
478 case PIPE_CAPF_GUARD_BAND_LEFT
:
479 case PIPE_CAPF_GUARD_BAND_TOP
:
480 case PIPE_CAPF_GUARD_BAND_RIGHT
:
481 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
487 static int r600_get_shader_param(struct pipe_screen
* pscreen
, unsigned shader
, enum pipe_shader_cap param
)
491 case PIPE_SHADER_FRAGMENT
:
492 case PIPE_SHADER_VERTEX
:
494 case PIPE_SHADER_GEOMETRY
:
495 /* XXX: support and enable geometry programs */
498 /* XXX: support tessellation on Evergreen */
502 /* XXX: all these should be fixed, since r600 surely supports much more! */
504 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
505 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
506 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
507 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
509 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
511 case PIPE_SHADER_CAP_MAX_INPUTS
:
512 if(shader
== PIPE_SHADER_FRAGMENT
)
516 case PIPE_SHADER_CAP_MAX_TEMPS
:
517 return 256; /* Max native temporaries. */
518 case PIPE_SHADER_CAP_MAX_ADDRS
:
519 /* XXX Isn't this equal to TEMPS? */
520 return 1; /* Max native address registers */
521 case PIPE_SHADER_CAP_MAX_CONSTS
:
522 return R600_MAX_CONST_BUFFER_SIZE
;
523 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
524 return R600_MAX_CONST_BUFFERS
-1;
525 case PIPE_SHADER_CAP_MAX_PREDS
:
526 return 0; /* nothing uses this */
527 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
529 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
530 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
531 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
532 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
534 case PIPE_SHADER_CAP_SUBROUTINES
:
536 case PIPE_SHADER_CAP_INTEGERS
:
538 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
544 static int r600_get_video_param(struct pipe_screen
*screen
,
545 enum pipe_video_profile profile
,
546 enum pipe_video_cap param
)
549 case PIPE_VIDEO_CAP_SUPPORTED
:
550 return vl_profile_supported(screen
, profile
);
551 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
553 case PIPE_VIDEO_CAP_MAX_WIDTH
:
554 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
555 return vl_video_buffer_max_size(screen
);
556 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
557 return PIPE_FORMAT_NV12
;
558 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
560 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
562 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
569 static void r600_destroy_screen(struct pipe_screen
* pscreen
)
571 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
576 if (rscreen
->fences
.bo
) {
577 struct r600_fence_block
*entry
, *tmp
;
579 LIST_FOR_EACH_ENTRY_SAFE(entry
, tmp
, &rscreen
->fences
.blocks
, head
) {
580 LIST_DEL(&entry
->head
);
584 rscreen
->ws
->buffer_unmap(rscreen
->fences
.bo
->buf
);
585 pipe_resource_reference((struct pipe_resource
**)&rscreen
->fences
.bo
, NULL
);
587 pipe_mutex_destroy(rscreen
->fences
.mutex
);
589 rscreen
->ws
->destroy(rscreen
->ws
);
591 util_slab_destroy(&rscreen
->pool_buffers
);
592 pipe_mutex_destroy(rscreen
->mutex_num_contexts
);
596 static void r600_fence_reference(struct pipe_screen
*pscreen
,
597 struct pipe_fence_handle
**ptr
,
598 struct pipe_fence_handle
*fence
)
600 struct r600_fence
**oldf
= (struct r600_fence
**)ptr
;
601 struct r600_fence
*newf
= (struct r600_fence
*)fence
;
603 if (pipe_reference(&(*oldf
)->reference
, &newf
->reference
)) {
604 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
605 pipe_mutex_lock(rscreen
->fences
.mutex
);
606 pipe_resource_reference((struct pipe_resource
**)&(*oldf
)->sleep_bo
, NULL
);
607 LIST_ADDTAIL(&(*oldf
)->head
, &rscreen
->fences
.pool
);
608 pipe_mutex_unlock(rscreen
->fences
.mutex
);
614 static boolean
r600_fence_signalled(struct pipe_screen
*pscreen
,
615 struct pipe_fence_handle
*fence
)
617 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
618 struct r600_fence
*rfence
= (struct r600_fence
*)fence
;
620 return rscreen
->fences
.data
[rfence
->index
];
623 static boolean
r600_fence_finish(struct pipe_screen
*pscreen
,
624 struct pipe_fence_handle
*fence
,
627 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
628 struct r600_fence
*rfence
= (struct r600_fence
*)fence
;
629 int64_t start_time
= 0;
632 if (timeout
!= PIPE_TIMEOUT_INFINITE
) {
633 start_time
= os_time_get();
635 /* Convert to microseconds. */
639 while (rscreen
->fences
.data
[rfence
->index
] == 0) {
640 /* Special-case infinite timeout - wait for the dummy BO to become idle */
641 if (timeout
== PIPE_TIMEOUT_INFINITE
) {
642 rscreen
->ws
->buffer_wait(rfence
->sleep_bo
->buf
, RADEON_USAGE_READWRITE
);
646 /* The dummy BO will be busy until the CS including the fence has completed, or
647 * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
648 if (!rscreen
->ws
->buffer_is_busy(rfence
->sleep_bo
->buf
, RADEON_USAGE_READWRITE
))
658 if (timeout
!= PIPE_TIMEOUT_INFINITE
&&
659 os_time_get() - start_time
>= timeout
) {
664 return rscreen
->fences
.data
[rfence
->index
] != 0;
667 static int r600_interpret_tiling(struct r600_screen
*rscreen
, uint32_t tiling_config
)
669 switch ((tiling_config
& 0xe) >> 1) {
671 rscreen
->tiling_info
.num_channels
= 1;
674 rscreen
->tiling_info
.num_channels
= 2;
677 rscreen
->tiling_info
.num_channels
= 4;
680 rscreen
->tiling_info
.num_channels
= 8;
686 switch ((tiling_config
& 0x30) >> 4) {
688 rscreen
->tiling_info
.num_banks
= 4;
691 rscreen
->tiling_info
.num_banks
= 8;
697 switch ((tiling_config
& 0xc0) >> 6) {
699 rscreen
->tiling_info
.group_bytes
= 256;
702 rscreen
->tiling_info
.group_bytes
= 512;
710 static int evergreen_interpret_tiling(struct r600_screen
*rscreen
, uint32_t tiling_config
)
712 switch (tiling_config
& 0xf) {
714 rscreen
->tiling_info
.num_channels
= 1;
717 rscreen
->tiling_info
.num_channels
= 2;
720 rscreen
->tiling_info
.num_channels
= 4;
723 rscreen
->tiling_info
.num_channels
= 8;
729 switch ((tiling_config
& 0xf0) >> 4) {
731 rscreen
->tiling_info
.num_banks
= 4;
734 rscreen
->tiling_info
.num_banks
= 8;
737 rscreen
->tiling_info
.num_banks
= 16;
743 switch ((tiling_config
& 0xf00) >> 8) {
745 rscreen
->tiling_info
.group_bytes
= 256;
748 rscreen
->tiling_info
.group_bytes
= 512;
756 static int r600_init_tiling(struct r600_screen
*rscreen
)
758 uint32_t tiling_config
= rscreen
->info
.r600_tiling_config
;
760 /* set default group bytes, overridden by tiling info ioctl */
761 if (rscreen
->chip_class
<= R700
) {
762 rscreen
->tiling_info
.group_bytes
= 256;
764 rscreen
->tiling_info
.group_bytes
= 512;
770 if (rscreen
->chip_class
<= R700
) {
771 return r600_interpret_tiling(rscreen
, tiling_config
);
773 return evergreen_interpret_tiling(rscreen
, tiling_config
);
777 static unsigned radeon_family_from_device(unsigned device
)
780 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
781 #include "pci_ids/r600_pci_ids.h"
788 struct pipe_screen
*r600_screen_create(struct radeon_winsys
*ws
)
790 struct r600_screen
*rscreen
= CALLOC_STRUCT(r600_screen
);
791 if (rscreen
== NULL
) {
796 ws
->query_info(ws
, &rscreen
->info
);
798 rscreen
->family
= radeon_family_from_device(rscreen
->info
.pci_id
);
799 if (rscreen
->family
== CHIP_UNKNOWN
) {
800 fprintf(stderr
, "r600: Unknown chipset 0x%04X\n", rscreen
->info
.pci_id
);
806 if (rscreen
->family
== CHIP_CAYMAN
) {
807 rscreen
->chip_class
= CAYMAN
;
808 } else if (rscreen
->family
>= CHIP_CEDAR
) {
809 rscreen
->chip_class
= EVERGREEN
;
810 } else if (rscreen
->family
>= CHIP_RV770
) {
811 rscreen
->chip_class
= R700
;
813 rscreen
->chip_class
= R600
;
816 if (r600_init_tiling(rscreen
)) {
821 rscreen
->screen
.destroy
= r600_destroy_screen
;
822 rscreen
->screen
.get_name
= r600_get_name
;
823 rscreen
->screen
.get_vendor
= r600_get_vendor
;
824 rscreen
->screen
.get_param
= r600_get_param
;
825 rscreen
->screen
.get_shader_param
= r600_get_shader_param
;
826 rscreen
->screen
.get_paramf
= r600_get_paramf
;
827 rscreen
->screen
.get_video_param
= r600_get_video_param
;
828 if (rscreen
->chip_class
>= EVERGREEN
) {
829 rscreen
->screen
.is_format_supported
= evergreen_is_format_supported
;
831 rscreen
->screen
.is_format_supported
= r600_is_format_supported
;
833 rscreen
->screen
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
834 rscreen
->screen
.context_create
= r600_create_context
;
835 rscreen
->screen
.fence_reference
= r600_fence_reference
;
836 rscreen
->screen
.fence_signalled
= r600_fence_signalled
;
837 rscreen
->screen
.fence_finish
= r600_fence_finish
;
838 r600_init_screen_resource_functions(&rscreen
->screen
);
840 util_format_s3tc_init();
842 util_slab_create(&rscreen
->pool_buffers
,
843 sizeof(struct r600_resource
), 64,
844 UTIL_SLAB_SINGLETHREADED
);
846 pipe_mutex_init(rscreen
->mutex_num_contexts
);
848 rscreen
->fences
.bo
= NULL
;
849 rscreen
->fences
.data
= NULL
;
850 rscreen
->fences
.next_index
= 0;
851 LIST_INITHEAD(&rscreen
->fences
.pool
);
852 LIST_INITHEAD(&rscreen
->fences
.blocks
);
853 pipe_mutex_init(rscreen
->fences
.mutex
);
855 rscreen
->use_surface_alloc
= debug_get_bool_option("R600_SURF", TRUE
);
857 return &rscreen
->screen
;