2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "pipe/p_context.h"
28 #include "tgsi/tgsi_scan.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
31 #include "util/u_blitter.h"
32 #include "util/u_double_list.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_transfer.h"
36 #include "util/u_surface.h"
37 #include "util/u_pack_color.h"
38 #include "util/u_memory.h"
39 #include "util/u_inlines.h"
40 #include "util/u_upload_mgr.h"
41 #include "vl/vl_decoder.h"
42 #include "vl/vl_video_buffer.h"
43 #include "os/os_time.h"
44 #include "pipebuffer/pb_buffer.h"
47 #include "r600_resource.h"
48 #include "r600_shader.h"
49 #include "r600_pipe.h"
54 static struct r600_fence
*r600_create_fence(struct r600_pipe_context
*ctx
)
56 struct r600_fence
*fence
= NULL
;
58 if (!ctx
->fences
.bo
) {
59 /* Create the shared buffer object */
60 ctx
->fences
.bo
= (struct r600_resource
*)
61 pipe_buffer_create(&ctx
->screen
->screen
, PIPE_BIND_CUSTOM
,
62 PIPE_USAGE_STAGING
, 4096);
63 if (!ctx
->fences
.bo
) {
64 R600_ERR("r600: failed to create bo for fence objects\n");
67 ctx
->fences
.data
= ctx
->ws
->buffer_map(ctx
->fences
.bo
->buf
, ctx
->ctx
.cs
,
71 if (!LIST_IS_EMPTY(&ctx
->fences
.pool
)) {
72 struct r600_fence
*entry
;
74 /* Try to find a freed fence that has been signalled */
75 LIST_FOR_EACH_ENTRY(entry
, &ctx
->fences
.pool
, head
) {
76 if (ctx
->fences
.data
[entry
->index
] != 0) {
77 LIST_DELINIT(&entry
->head
);
85 /* Allocate a new fence */
86 struct r600_fence_block
*block
;
89 if ((ctx
->fences
.next_index
+ 1) >= 1024) {
90 R600_ERR("r600: too many concurrent fences\n");
94 index
= ctx
->fences
.next_index
++;
96 if (!(index
% FENCE_BLOCK_SIZE
)) {
97 /* Allocate a new block */
98 block
= CALLOC_STRUCT(r600_fence_block
);
102 LIST_ADD(&block
->head
, &ctx
->fences
.blocks
);
104 block
= LIST_ENTRY(struct r600_fence_block
, ctx
->fences
.blocks
.next
, head
);
107 fence
= &block
->fences
[index
% FENCE_BLOCK_SIZE
];
109 fence
->index
= index
;
112 pipe_reference_init(&fence
->reference
, 1);
114 ctx
->fences
.data
[fence
->index
] = 0;
115 r600_context_emit_fence(&ctx
->ctx
, ctx
->fences
.bo
, fence
->index
, 1);
120 void r600_flush(struct pipe_context
*ctx
, struct pipe_fence_handle
**fence
,
123 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
124 struct r600_fence
**rfence
= (struct r600_fence
**)fence
;
125 struct pipe_query
*render_cond
= NULL
;
126 unsigned render_cond_mode
= 0;
129 *rfence
= r600_create_fence(rctx
);
131 /* Disable render condition. */
132 if (rctx
->current_render_cond
) {
133 render_cond
= rctx
->current_render_cond
;
134 render_cond_mode
= rctx
->current_render_cond_mode
;
135 ctx
->render_condition(ctx
, NULL
, 0);
138 r600_context_flush(&rctx
->ctx
, flags
);
140 /* Re-enable render condition. */
142 ctx
->render_condition(ctx
, render_cond
, render_cond_mode
);
146 static void r600_flush_from_st(struct pipe_context
*ctx
,
147 struct pipe_fence_handle
**fence
)
149 r600_flush(ctx
, fence
, 0);
152 static void r600_flush_from_winsys(void *ctx
, unsigned flags
)
154 r600_flush((struct pipe_context
*)ctx
, NULL
, flags
);
157 static void r600_update_num_contexts(struct r600_screen
*rscreen
, int diff
)
159 pipe_mutex_lock(rscreen
->mutex_num_contexts
);
161 rscreen
->num_contexts
++;
163 if (rscreen
->num_contexts
> 1)
164 util_slab_set_thread_safety(&rscreen
->pool_buffers
,
165 UTIL_SLAB_MULTITHREADED
);
167 rscreen
->num_contexts
--;
169 if (rscreen
->num_contexts
<= 1)
170 util_slab_set_thread_safety(&rscreen
->pool_buffers
,
171 UTIL_SLAB_SINGLETHREADED
);
173 pipe_mutex_unlock(rscreen
->mutex_num_contexts
);
176 static void r600_destroy_context(struct pipe_context
*context
)
178 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)context
;
180 rctx
->context
.delete_depth_stencil_alpha_state(&rctx
->context
, rctx
->custom_dsa_flush
);
181 util_unreference_framebuffer_state(&rctx
->framebuffer
);
183 r600_context_fini(&rctx
->ctx
);
185 util_blitter_destroy(rctx
->blitter
);
187 for (int i
= 0; i
< R600_PIPE_NSTATES
; i
++) {
188 free(rctx
->states
[i
]);
191 u_vbuf_destroy(rctx
->vbuf_mgr
);
192 util_slab_destroy(&rctx
->pool_transfers
);
194 if (rctx
->fences
.bo
) {
195 struct r600_fence_block
*entry
, *tmp
;
197 LIST_FOR_EACH_ENTRY_SAFE(entry
, tmp
, &rctx
->fences
.blocks
, head
) {
198 LIST_DEL(&entry
->head
);
202 rctx
->ws
->buffer_unmap(rctx
->fences
.bo
->buf
);
203 pipe_resource_reference((struct pipe_resource
**)&rctx
->fences
.bo
, NULL
);
206 r600_update_num_contexts(rctx
->screen
, -1);
211 static struct pipe_context
*r600_create_context(struct pipe_screen
*screen
, void *priv
)
213 struct r600_pipe_context
*rctx
= CALLOC_STRUCT(r600_pipe_context
);
214 struct r600_screen
* rscreen
= (struct r600_screen
*)screen
;
219 r600_update_num_contexts(rscreen
, 1);
221 rctx
->context
.winsys
= rscreen
->screen
.winsys
;
222 rctx
->context
.screen
= screen
;
223 rctx
->context
.priv
= priv
;
224 rctx
->context
.destroy
= r600_destroy_context
;
225 rctx
->context
.flush
= r600_flush_from_st
;
227 /* Easy accessing of screen/winsys. */
228 rctx
->screen
= rscreen
;
229 rctx
->ws
= rscreen
->ws
;
230 rctx
->family
= rscreen
->family
;
231 rctx
->chip_class
= rscreen
->chip_class
;
233 rctx
->fences
.bo
= NULL
;
234 rctx
->fences
.data
= NULL
;
235 rctx
->fences
.next_index
= 0;
236 LIST_INITHEAD(&rctx
->fences
.pool
);
237 LIST_INITHEAD(&rctx
->fences
.blocks
);
239 r600_init_blit_functions(rctx
);
240 r600_init_query_functions(rctx
);
241 r600_init_context_resource_functions(rctx
);
242 r600_init_surface_functions(rctx
);
243 rctx
->context
.draw_vbo
= r600_draw_vbo
;
245 rctx
->context
.create_video_decoder
= vl_create_decoder
;
246 rctx
->context
.create_video_buffer
= vl_video_buffer_create
;
248 switch (rctx
->chip_class
) {
251 r600_init_state_functions(rctx
);
252 if (r600_context_init(&rctx
->ctx
, rctx
->screen
)) {
253 r600_destroy_context(&rctx
->context
);
256 r600_init_config(rctx
);
257 rctx
->custom_dsa_flush
= r600_create_db_flush_dsa(rctx
);
261 evergreen_init_state_functions(rctx
);
262 if (evergreen_context_init(&rctx
->ctx
, rctx
->screen
)) {
263 r600_destroy_context(&rctx
->context
);
266 evergreen_init_config(rctx
);
267 rctx
->custom_dsa_flush
= evergreen_create_db_flush_dsa(rctx
);
270 R600_ERR("Unsupported chip class %d.\n", rctx
->chip_class
);
271 r600_destroy_context(&rctx
->context
);
275 rctx
->ctx
.pipe
= &rctx
->context
;
276 rctx
->ctx
.flush
= r600_flush_from_winsys
;
277 rctx
->ws
->cs_set_flush_callback(rctx
->ctx
.cs
, r600_flush_from_winsys
, rctx
);
279 util_slab_create(&rctx
->pool_transfers
,
280 sizeof(struct pipe_transfer
), 64,
281 UTIL_SLAB_SINGLETHREADED
);
283 rctx
->vbuf_mgr
= u_vbuf_create(&rctx
->context
, 1024 * 1024, 256,
284 PIPE_BIND_VERTEX_BUFFER
|
285 PIPE_BIND_INDEX_BUFFER
|
286 PIPE_BIND_CONSTANT_BUFFER
,
287 U_VERTEX_FETCH_DWORD_ALIGNED
);
288 if (!rctx
->vbuf_mgr
) {
289 r600_destroy_context(&rctx
->context
);
292 rctx
->vbuf_mgr
->caps
.format_fixed32
= 0;
294 rctx
->blitter
= util_blitter_create(&rctx
->context
);
295 if (rctx
->blitter
== NULL
) {
296 r600_destroy_context(&rctx
->context
);
300 r600_get_backend_mask(&rctx
->ctx
); /* this emits commands and must be last */
302 return &rctx
->context
;
308 static const char* r600_get_vendor(struct pipe_screen
* pscreen
)
313 static const char *r600_get_family_name(enum radeon_family family
)
316 case CHIP_R600
: return "AMD R600";
317 case CHIP_RV610
: return "AMD RV610";
318 case CHIP_RV630
: return "AMD RV630";
319 case CHIP_RV670
: return "AMD RV670";
320 case CHIP_RV620
: return "AMD RV620";
321 case CHIP_RV635
: return "AMD RV635";
322 case CHIP_RS780
: return "AMD RS780";
323 case CHIP_RS880
: return "AMD RS880";
324 case CHIP_RV770
: return "AMD RV770";
325 case CHIP_RV730
: return "AMD RV730";
326 case CHIP_RV710
: return "AMD RV710";
327 case CHIP_RV740
: return "AMD RV740";
328 case CHIP_CEDAR
: return "AMD CEDAR";
329 case CHIP_REDWOOD
: return "AMD REDWOOD";
330 case CHIP_JUNIPER
: return "AMD JUNIPER";
331 case CHIP_CYPRESS
: return "AMD CYPRESS";
332 case CHIP_HEMLOCK
: return "AMD HEMLOCK";
333 case CHIP_PALM
: return "AMD PALM";
334 case CHIP_SUMO
: return "AMD SUMO";
335 case CHIP_SUMO2
: return "AMD SUMO2";
336 case CHIP_BARTS
: return "AMD BARTS";
337 case CHIP_TURKS
: return "AMD TURKS";
338 case CHIP_CAICOS
: return "AMD CAICOS";
339 case CHIP_CAYMAN
: return "AMD CAYMAN";
340 default: return "AMD unknown";
344 static const char* r600_get_name(struct pipe_screen
* pscreen
)
346 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
348 return r600_get_family_name(rscreen
->family
);
351 static int r600_get_param(struct pipe_screen
* pscreen
, enum pipe_cap param
)
353 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
354 enum radeon_family family
= rscreen
->family
;
357 /* Supported features (boolean caps). */
358 case PIPE_CAP_NPOT_TEXTURES
:
359 case PIPE_CAP_TWO_SIDED_STENCIL
:
361 case PIPE_CAP_DUAL_SOURCE_BLEND
:
362 case PIPE_CAP_ANISOTROPIC_FILTER
:
363 case PIPE_CAP_POINT_SPRITE
:
364 case PIPE_CAP_OCCLUSION_QUERY
:
365 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
366 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
367 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
368 case PIPE_CAP_TEXTURE_SWIZZLE
:
369 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE
:
370 case PIPE_CAP_DEPTH_CLAMP
:
371 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
372 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
373 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
374 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
375 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
377 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
378 case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL
:
379 case PIPE_CAP_PRIMITIVE_RESTART
:
380 case PIPE_CAP_CONDITIONAL_RENDER
:
381 case PIPE_CAP_TEXTURE_BARRIER
:
384 /* Supported except the original R600. */
385 case PIPE_CAP_INDEP_BLEND_ENABLE
:
386 case PIPE_CAP_INDEP_BLEND_FUNC
:
387 /* R600 doesn't support per-MRT blends */
388 return family
== CHIP_R600
? 0 : 1;
390 /* Supported on Evergreen. */
391 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
392 return family
>= CHIP_CEDAR
? 1 : 0;
394 /* Unsupported features. */
395 case PIPE_CAP_STREAM_OUTPUT
:
396 case PIPE_CAP_TGSI_INSTANCEID
:
397 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
398 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
402 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
403 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
404 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
405 if (family
>= CHIP_CEDAR
)
409 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
410 return rscreen
->info
.drm_minor
>= 9 ?
411 (family
>= CHIP_CEDAR
? 16384 : 8192) : 0;
412 case PIPE_CAP_MAX_COMBINED_SAMPLERS
:
415 /* Render targets. */
416 case PIPE_CAP_MAX_RENDER_TARGETS
:
417 /* FIXME some r6xx are buggy and can only do 4 */
420 /* Timer queries, present when the clock frequency is non zero. */
421 case PIPE_CAP_TIMER_QUERY
:
422 return rscreen
->info
.r600_clock_crystal_freq
!= 0;
424 case PIPE_CAP_MIN_TEXEL_OFFSET
:
427 case PIPE_CAP_MAX_TEXEL_OFFSET
:
431 R600_ERR("r600: unknown param %d\n", param
);
436 static float r600_get_paramf(struct pipe_screen
* pscreen
, enum pipe_cap param
)
438 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
439 enum radeon_family family
= rscreen
->family
;
442 case PIPE_CAP_MAX_LINE_WIDTH
:
443 case PIPE_CAP_MAX_LINE_WIDTH_AA
:
444 case PIPE_CAP_MAX_POINT_WIDTH
:
445 case PIPE_CAP_MAX_POINT_WIDTH_AA
:
446 if (family
>= CHIP_CEDAR
)
450 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY
:
452 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS
:
455 R600_ERR("r600: unsupported paramf %d\n", param
);
460 static int r600_get_shader_param(struct pipe_screen
* pscreen
, unsigned shader
, enum pipe_shader_cap param
)
462 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
465 case PIPE_SHADER_FRAGMENT
:
466 case PIPE_SHADER_VERTEX
:
468 case PIPE_SHADER_GEOMETRY
:
469 /* TODO: support and enable geometry programs */
472 /* TODO: support tessellation on Evergreen */
476 /* TODO: all these should be fixed, since r600 surely supports much more! */
478 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
479 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
480 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
481 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
483 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
484 return 8; /* FIXME */
485 case PIPE_SHADER_CAP_MAX_INPUTS
:
486 if(shader
== PIPE_SHADER_FRAGMENT
)
490 case PIPE_SHADER_CAP_MAX_TEMPS
:
491 return 256; /* Max native temporaries. */
492 case PIPE_SHADER_CAP_MAX_ADDRS
:
493 /* FIXME Isn't this equal to TEMPS? */
494 return 1; /* Max native address registers */
495 case PIPE_SHADER_CAP_MAX_CONSTS
:
496 return R600_MAX_CONST_BUFFER_SIZE
;
497 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
498 return R600_MAX_CONST_BUFFERS
;
499 case PIPE_SHADER_CAP_MAX_PREDS
:
500 return 0; /* FIXME */
501 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
503 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
504 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
505 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
506 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
508 case PIPE_SHADER_CAP_SUBROUTINES
:
510 case PIPE_SHADER_CAP_INTEGERS
:
511 if (rscreen
->chip_class
== EVERGREEN
)
514 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
521 static int r600_get_video_param(struct pipe_screen
*screen
,
522 enum pipe_video_profile profile
,
523 enum pipe_video_cap param
)
526 case PIPE_VIDEO_CAP_SUPPORTED
:
527 return vl_profile_supported(screen
, profile
);
528 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
530 case PIPE_VIDEO_CAP_MAX_WIDTH
:
531 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
532 return vl_video_buffer_max_size(screen
);
533 case PIPE_VIDEO_CAP_NUM_BUFFERS_DESIRED
:
534 return vl_num_buffers_desired(screen
, profile
);
540 static void r600_destroy_screen(struct pipe_screen
* pscreen
)
542 struct r600_screen
*rscreen
= (struct r600_screen
*)pscreen
;
547 rscreen
->ws
->destroy(rscreen
->ws
);
549 util_slab_destroy(&rscreen
->pool_buffers
);
550 pipe_mutex_destroy(rscreen
->mutex_num_contexts
);
554 static void r600_fence_reference(struct pipe_screen
*pscreen
,
555 struct pipe_fence_handle
**ptr
,
556 struct pipe_fence_handle
*fence
)
558 struct r600_fence
**oldf
= (struct r600_fence
**)ptr
;
559 struct r600_fence
*newf
= (struct r600_fence
*)fence
;
561 if (pipe_reference(&(*oldf
)->reference
, &newf
->reference
)) {
562 struct r600_pipe_context
*ctx
= (*oldf
)->ctx
;
563 LIST_ADDTAIL(&(*oldf
)->head
, &ctx
->fences
.pool
);
569 static boolean
r600_fence_signalled(struct pipe_screen
*pscreen
,
570 struct pipe_fence_handle
*fence
)
572 struct r600_fence
*rfence
= (struct r600_fence
*)fence
;
573 struct r600_pipe_context
*ctx
= rfence
->ctx
;
575 return ctx
->fences
.data
[rfence
->index
];
578 static boolean
r600_fence_finish(struct pipe_screen
*pscreen
,
579 struct pipe_fence_handle
*fence
,
582 struct r600_fence
*rfence
= (struct r600_fence
*)fence
;
583 struct r600_pipe_context
*ctx
= rfence
->ctx
;
584 int64_t start_time
= 0;
587 if (timeout
!= PIPE_TIMEOUT_INFINITE
) {
588 start_time
= os_time_get();
590 /* Convert to microseconds. */
594 while (ctx
->fences
.data
[rfence
->index
] == 0) {
602 if (timeout
!= PIPE_TIMEOUT_INFINITE
&&
603 os_time_get() - start_time
>= timeout
) {
611 static int r600_interpret_tiling(struct r600_screen
*rscreen
, uint32_t tiling_config
)
613 switch ((tiling_config
& 0xe) >> 1) {
615 rscreen
->tiling_info
.num_channels
= 1;
618 rscreen
->tiling_info
.num_channels
= 2;
621 rscreen
->tiling_info
.num_channels
= 4;
624 rscreen
->tiling_info
.num_channels
= 8;
630 switch ((tiling_config
& 0x30) >> 4) {
632 rscreen
->tiling_info
.num_banks
= 4;
635 rscreen
->tiling_info
.num_banks
= 8;
641 switch ((tiling_config
& 0xc0) >> 6) {
643 rscreen
->tiling_info
.group_bytes
= 256;
646 rscreen
->tiling_info
.group_bytes
= 512;
654 static int evergreen_interpret_tiling(struct r600_screen
*rscreen
, uint32_t tiling_config
)
656 switch (tiling_config
& 0xf) {
658 rscreen
->tiling_info
.num_channels
= 1;
661 rscreen
->tiling_info
.num_channels
= 2;
664 rscreen
->tiling_info
.num_channels
= 4;
667 rscreen
->tiling_info
.num_channels
= 8;
673 switch ((tiling_config
& 0xf0) >> 4) {
675 rscreen
->tiling_info
.num_banks
= 4;
678 rscreen
->tiling_info
.num_banks
= 8;
681 rscreen
->tiling_info
.num_banks
= 16;
687 switch ((tiling_config
& 0xf00) >> 8) {
689 rscreen
->tiling_info
.group_bytes
= 256;
692 rscreen
->tiling_info
.group_bytes
= 512;
700 static int r600_init_tiling(struct r600_screen
*rscreen
)
702 uint32_t tiling_config
= rscreen
->info
.r600_tiling_config
;
704 /* set default group bytes, overridden by tiling info ioctl */
705 if (rscreen
->chip_class
<= R700
) {
706 rscreen
->tiling_info
.group_bytes
= 256;
708 rscreen
->tiling_info
.group_bytes
= 512;
714 if (rscreen
->chip_class
<= R700
) {
715 return r600_interpret_tiling(rscreen
, tiling_config
);
717 return evergreen_interpret_tiling(rscreen
, tiling_config
);
721 static unsigned radeon_family_from_device(unsigned device
)
724 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
725 #include "pci_ids/r600_pci_ids.h"
732 struct pipe_screen
*r600_screen_create(struct radeon_winsys
*ws
)
734 struct r600_screen
*rscreen
= CALLOC_STRUCT(r600_screen
);
735 if (rscreen
== NULL
) {
740 ws
->query_info(ws
, &rscreen
->info
);
742 rscreen
->family
= radeon_family_from_device(rscreen
->info
.pci_id
);
743 if (rscreen
->family
== CHIP_UNKNOWN
) {
744 fprintf(stderr
, "r600: Unknown chipset 0x%04X\n", rscreen
->info
.pci_id
);
750 if (rscreen
->family
== CHIP_CAYMAN
) {
751 rscreen
->chip_class
= CAYMAN
;
752 } else if (rscreen
->family
>= CHIP_CEDAR
) {
753 rscreen
->chip_class
= EVERGREEN
;
754 } else if (rscreen
->family
>= CHIP_RV770
) {
755 rscreen
->chip_class
= R700
;
757 rscreen
->chip_class
= R600
;
760 if (r600_init_tiling(rscreen
)) {
765 rscreen
->screen
.winsys
= (struct pipe_winsys
*)ws
;
766 rscreen
->screen
.destroy
= r600_destroy_screen
;
767 rscreen
->screen
.get_name
= r600_get_name
;
768 rscreen
->screen
.get_vendor
= r600_get_vendor
;
769 rscreen
->screen
.get_param
= r600_get_param
;
770 rscreen
->screen
.get_shader_param
= r600_get_shader_param
;
771 rscreen
->screen
.get_paramf
= r600_get_paramf
;
772 rscreen
->screen
.get_video_param
= r600_get_video_param
;
773 if (rscreen
->chip_class
>= EVERGREEN
) {
774 rscreen
->screen
.is_format_supported
= evergreen_is_format_supported
;
776 rscreen
->screen
.is_format_supported
= r600_is_format_supported
;
778 rscreen
->screen
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
779 rscreen
->screen
.context_create
= r600_create_context
;
780 rscreen
->screen
.fence_reference
= r600_fence_reference
;
781 rscreen
->screen
.fence_signalled
= r600_fence_signalled
;
782 rscreen
->screen
.fence_finish
= r600_fence_finish
;
783 r600_init_screen_resource_functions(&rscreen
->screen
);
785 util_format_s3tc_init();
787 util_slab_create(&rscreen
->pool_buffers
,
788 sizeof(struct r600_resource
), 64,
789 UTIL_SLAB_SINGLETHREADED
);
791 pipe_mutex_init(rscreen
->mutex_num_contexts
);
793 return &rscreen
->screen
;