src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25 #include "r600_isa.h"
  26 #include "evergreen_compute.h"
  27 #include "r600d.h"
  28
  29 #include "sb/sb_public.h"
  30
  31 #include <errno.h>
  32 #include "pipe/p_shader_tokens.h"
  33 #include "util/u_debug.h"
  34 #include "util/u_memory.h"
  35 #include "util/u_simple_shaders.h"
  36 #include "util/u_upload_mgr.h"
  37 #include "util/u_math.h"
  38 #include "vl/vl_decoder.h"
  39 #include "vl/vl_video_buffer.h"
  40 #include "radeon/radeon_video.h"
  41 #include "radeon/radeon_uvd.h"
  42 #include "os/os_time.h"
  43
  44 static const struct debug_named_value r600_debug_options[] = {
  45         /* features */
  46 #if defined(R600_USE_LLVM)
  47         { "llvm", DBG_LLVM, "Enable the LLVM shader compiler" },
  48 #endif
  49         { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
  50
  51         /* shader backend */
  52         { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
  53         { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
  54         { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
  55         { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
  56         { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
  57         { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
  58         { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
  59         { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
  60
  61         DEBUG_NAMED_VALUE_END /* must be last */
  62 };
  63
  64 /*
  65  * pipe_context
  66  */
  67
  68 static void r600_destroy_context(struct pipe_context *context)
  69 {
  70         struct r600_context *rctx = (struct r600_context *)context;
  71
  72         r600_isa_destroy(rctx->isa);
  73
  74         r600_sb_context_destroy(rctx->sb_context);
  75
  76         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
  77         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
  78
  79         if (rctx->dummy_pixel_shader) {
  80                 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
  81         }
  82         if (rctx->custom_dsa_flush) {
  83                 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
  84         }
  85         if (rctx->custom_blend_resolve) {
  86                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
  87         }
  88         if (rctx->custom_blend_decompress) {
  89                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
  90         }
  91         if (rctx->custom_blend_fastclear) {
  92                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
  93         }
  94         util_unreference_framebuffer_state(&rctx->framebuffer.state);
  95
  96         if (rctx->blitter) {
  97                 util_blitter_destroy(rctx->blitter);
  98         }
  99         if (rctx->allocator_fetch_shader) {
 100                 u_suballocator_destroy(rctx->allocator_fetch_shader);
 101         }
 102
 103         r600_release_command_buffer(&rctx->start_cs_cmd);
 104
 105         FREE(rctx->start_compute_cs_cmd.buf);
 106
 107         r600_common_context_cleanup(&rctx->b);
 108         FREE(rctx);
 109 }
 110
 111 static struct pipe_context *r600_create_context(struct pipe_screen *screen,
 112                                                 void *priv, unsigned flags)
 113 {
 114         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 115         struct r600_screen* rscreen = (struct r600_screen *)screen;
 116         struct radeon_winsys *ws = rscreen->b.ws;
 117
 118         if (rctx == NULL)
 119                 return NULL;
 120
 121         rctx->b.b.screen = screen;
 122         rctx->b.b.priv = priv;
 123         rctx->b.b.destroy = r600_destroy_context;
 124         rctx->b.set_atom_dirty = (void *)r600_set_atom_dirty;
 125
 126         if (!r600_common_context_init(&rctx->b, &rscreen->b))
 127                 goto fail;
 128
 129         rctx->screen = rscreen;
 130         rctx->keep_tiling_flags = rscreen->b.info.drm_minor >= 12;
 131
 132         r600_init_blit_functions(rctx);
 133
 134         if (rscreen->b.info.has_uvd) {
 135                 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
 136                 rctx->b.b.create_video_buffer = r600_video_buffer_create;
 137         } else {
 138                 rctx->b.b.create_video_codec = vl_create_decoder;
 139                 rctx->b.b.create_video_buffer = vl_video_buffer_create;
 140         }
 141
 142         r600_init_common_state_functions(rctx);
 143
 144         switch (rctx->b.chip_class) {
 145         case R600:
 146         case R700:
 147                 r600_init_state_functions(rctx);
 148                 r600_init_atom_start_cs(rctx);
 149                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 150                 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
 151                                                                       : r600_create_resolve_blend(rctx);
 152                 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
 153                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
 154                                            rctx->b.family == CHIP_RV620 ||
 155                                            rctx->b.family == CHIP_RS780 ||
 156                                            rctx->b.family == CHIP_RS880 ||
 157                                            rctx->b.family == CHIP_RV710);
 158                 break;
 159         case EVERGREEN:
 160         case CAYMAN:
 161                 evergreen_init_state_functions(rctx);
 162                 evergreen_init_atom_start_cs(rctx);
 163                 evergreen_init_atom_start_compute_cs(rctx);
 164                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 165                 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
 166                 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
 167                 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
 168                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
 169                                            rctx->b.family == CHIP_PALM ||
 170                                            rctx->b.family == CHIP_SUMO ||
 171                                            rctx->b.family == CHIP_SUMO2 ||
 172                                            rctx->b.family == CHIP_CAICOS ||
 173                                            rctx->b.family == CHIP_CAYMAN ||
 174                                            rctx->b.family == CHIP_ARUBA);
 175                 break;
 176         default:
 177                 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
 178                 goto fail;
 179         }
 180
 181         rctx->b.rings.gfx.cs = ws->cs_create(rctx->b.ctx, RING_GFX,
 182                                              r600_context_gfx_flush, rctx,
 183                                              rscreen->b.trace_bo ?
 184                                                      rscreen->b.trace_bo->cs_buf : NULL);
 185         rctx->b.rings.gfx.flush = r600_context_gfx_flush;
 186
 187         rctx->allocator_fetch_shader = u_suballocator_create(&rctx->b.b, 64 * 1024, 256,
 188                                                              0, PIPE_USAGE_DEFAULT, FALSE);
 189         if (!rctx->allocator_fetch_shader)
 190                 goto fail;
 191
 192         rctx->isa = calloc(1, sizeof(struct r600_isa));
 193         if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
 194                 goto fail;
 195
 196         if (rscreen->b.debug_flags & DBG_FORCE_DMA)
 197                 rctx->b.b.resource_copy_region = rctx->b.dma_copy;
 198
 199         rctx->blitter = util_blitter_create(&rctx->b.b);
 200         if (rctx->blitter == NULL)
 201                 goto fail;
 202         util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
 203         rctx->blitter->draw_rectangle = r600_draw_rectangle;
 204
 205         r600_begin_new_cs(rctx);
 206         r600_query_init_backend_mask(&rctx->b); /* this emits commands and must be last */
 207
 208         rctx->dummy_pixel_shader =
 209                 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
 210                                                      TGSI_SEMANTIC_GENERIC,
 211                                                      TGSI_INTERPOLATE_CONSTANT);
 212         rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 213
 214         return &rctx->b.b;
 215
 216 fail:
 217         r600_destroy_context(&rctx->b.b);
 218         return NULL;
 219 }
 220
 221 /*
 222  * pipe_screen
 223  */
 224
 225 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 226 {
 227         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 228         enum radeon_family family = rscreen->b.family;
 229
 230         switch (param) {
 231         /* Supported features (boolean caps). */
 232         case PIPE_CAP_NPOT_TEXTURES:
 233         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 234         case PIPE_CAP_TWO_SIDED_STENCIL:
 235         case PIPE_CAP_ANISOTROPIC_FILTER:
 236         case PIPE_CAP_POINT_SPRITE:
 237         case PIPE_CAP_OCCLUSION_QUERY:
 238         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 239         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 240         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 241         case PIPE_CAP_TEXTURE_SWIZZLE:
 242         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 243         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 244         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 245         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 246         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 247         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 248         case PIPE_CAP_SM3:
 249         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 250         case PIPE_CAP_PRIMITIVE_RESTART:
 251         case PIPE_CAP_CONDITIONAL_RENDER:
 252         case PIPE_CAP_TEXTURE_BARRIER:
 253         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 254         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 255         case PIPE_CAP_TGSI_INSTANCEID:
 256         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 257         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 258         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 259         case PIPE_CAP_USER_INDEX_BUFFERS:
 260         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 261         case PIPE_CAP_START_INSTANCE:
 262         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 263         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 264         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 265         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 266         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 267         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 268         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 269         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 270         case PIPE_CAP_SAMPLE_SHADING:
 271         case PIPE_CAP_CLIP_HALFZ:
 272         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 273         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 274         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 275         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 276         case PIPE_CAP_TGSI_TXQS:
 277                 return 1;
 278
 279         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 280                 return rscreen->b.info.drm_major == 2 && rscreen->b.info.drm_minor >= 43;
 281
 282         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 283                 return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;
 284
 285         case PIPE_CAP_COMPUTE:
 286                 return rscreen->b.chip_class > R700;
 287
 288         case PIPE_CAP_TGSI_TEXCOORD:
 289                 return 0;
 290
 291         case PIPE_CAP_FAKE_SW_MSAA:
 292                 return 0;
 293
 294         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 295                 return MIN2(rscreen->b.info.vram_size, 0xFFFFFFFF);
 296
 297         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 298                 return R600_MAP_BUFFER_ALIGNMENT;
 299
 300         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 301                 return 256;
 302
 303         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 304                 return 1;
 305
 306         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 307                 if (family >= CHIP_CEDAR)
 308                    return 330;
 309                 /* pre-evergreen geom shaders need newer kernel */
 310                 if (rscreen->b.info.drm_minor >= 37)
 311                    return 330;
 312                 return 140;
 313
 314         /* Supported except the original R600. */
 315         case PIPE_CAP_INDEP_BLEND_ENABLE:
 316         case PIPE_CAP_INDEP_BLEND_FUNC:
 317                 /* R600 doesn't support per-MRT blends */
 318                 return family == CHIP_R600 ? 0 : 1;
 319
 320         /* Supported on Evergreen. */
 321         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 322         case PIPE_CAP_CUBE_MAP_ARRAY:
 323         case PIPE_CAP_TEXTURE_GATHER_SM5:
 324         case PIPE_CAP_TEXTURE_QUERY_LOD:
 325         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 326                 return family >= CHIP_CEDAR ? 1 : 0;
 327         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 328                 return family >= CHIP_CEDAR ? 4 : 0;
 329         case PIPE_CAP_DRAW_INDIRECT:
 330                 /* kernel command checker support is also required */
 331                 return family >= CHIP_CEDAR && rscreen->b.info.drm_minor >= 41;
 332
 333         /* Unsupported features. */
 334         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 335         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 336         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 337         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 338         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 339         case PIPE_CAP_USER_VERTEX_BUFFERS:
 340         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 341         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 342         case PIPE_CAP_VERTEXID_NOBASE:
 343         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 344         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 345         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 346                 return 0;
 347
 348         /* Stream output. */
 349         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 350                 return rscreen->b.has_streamout ? 4 : 0;
 351         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 352                 return rscreen->b.has_streamout ? 1 : 0;
 353         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 354         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 355                 return 32*4;
 356
 357         /* Geometry shader output. */
 358         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 359                 return 1024;
 360         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 361                 return 16384;
 362         case PIPE_CAP_MAX_VERTEX_STREAMS:
 363                 return family >= CHIP_CEDAR ? 4 : 1;
 364
 365         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 366                 return 2047;
 367
 368         /* Texturing. */
 369         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 370         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 371                 if (family >= CHIP_CEDAR)
 372                         return 15;
 373                 else
 374                         return 14;
 375         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 376                 /* textures support 8192, but layered rendering supports 2048 */
 377                 return 12;
 378         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 379                 /* textures support 8192, but layered rendering supports 2048 */
 380                 return rscreen->b.info.drm_minor >= 9 ? 2048 : 0;
 381
 382         /* Render targets. */
 383         case PIPE_CAP_MAX_RENDER_TARGETS:
 384                 /* XXX some r6xx are buggy and can only do 4 */
 385                 return 8;
 386
 387         case PIPE_CAP_MAX_VIEWPORTS:
 388                 return R600_MAX_VIEWPORTS;
 389
 390         /* Timer queries, present when the clock frequency is non zero. */
 391         case PIPE_CAP_QUERY_TIME_ELAPSED:
 392                 return rscreen->b.info.r600_clock_crystal_freq != 0;
 393         case PIPE_CAP_QUERY_TIMESTAMP:
 394                 return rscreen->b.info.drm_minor >= 20 &&
 395                        rscreen->b.info.r600_clock_crystal_freq != 0;
 396
 397         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 398         case PIPE_CAP_MIN_TEXEL_OFFSET:
 399                 return -8;
 400
 401         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 402         case PIPE_CAP_MAX_TEXEL_OFFSET:
 403                 return 7;
 404
 405         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 406                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 407         case PIPE_CAP_ENDIANNESS:
 408                 return PIPE_ENDIAN_LITTLE;
 409
 410         case PIPE_CAP_VENDOR_ID:
 411                 return 0x1002;
 412         case PIPE_CAP_DEVICE_ID:
 413                 return rscreen->b.info.pci_id;
 414         case PIPE_CAP_ACCELERATED:
 415                 return 1;
 416         case PIPE_CAP_VIDEO_MEMORY:
 417                 return rscreen->b.info.vram_size >> 20;
 418         case PIPE_CAP_UMA:
 419                 return 0;
 420         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 421                 return rscreen->b.chip_class >= R700;
 422         }
 423         return 0;
 424 }
 425
 426 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 427 {
 428         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 429
 430         switch(shader)
 431         {
 432         case PIPE_SHADER_FRAGMENT:
 433         case PIPE_SHADER_VERTEX:
 434         case PIPE_SHADER_COMPUTE:
 435                 break;
 436         case PIPE_SHADER_GEOMETRY:
 437                 if (rscreen->b.family >= CHIP_CEDAR)
 438                         break;
 439                 /* pre-evergreen geom shaders need newer kernel */
 440                 if (rscreen->b.info.drm_minor >= 37)
 441                         break;
 442                 return 0;
 443         default:
 444                 /* XXX: support tessellation on Evergreen */
 445                 return 0;
 446         }
 447
 448         switch (param) {
 449         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 450         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 451         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 452         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 453                 return 16384;
 454         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 455                 return 32;
 456         case PIPE_SHADER_CAP_MAX_INPUTS:
 457                 return shader == PIPE_SHADER_VERTEX ? 16 : 32;
 458         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 459                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 460         case PIPE_SHADER_CAP_MAX_TEMPS:
 461                 return 256; /* Max native temporaries. */
 462         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 463                 if (shader == PIPE_SHADER_COMPUTE) {
 464                         uint64_t max_const_buffer_size;
 465                         pscreen->get_compute_param(pscreen,
 466                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 467                                 &max_const_buffer_size);
 468                         return max_const_buffer_size;
 469
 470                 } else {
 471                         return R600_MAX_CONST_BUFFER_SIZE;
 472                 }
 473         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 474                 return R600_MAX_USER_CONST_BUFFERS;
 475         case PIPE_SHADER_CAP_MAX_PREDS:
 476                 return 0; /* nothing uses this */
 477         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 478                 return 1;
 479         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 480                 return 1;
 481         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 482         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 483         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 484         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 485                 return 1;
 486         case PIPE_SHADER_CAP_SUBROUTINES:
 487                 return 0;
 488         case PIPE_SHADER_CAP_INTEGERS:
 489         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 490                 return 1;
 491         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 492         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 493                 return 16;
 494         case PIPE_SHADER_CAP_PREFERRED_IR:
 495                 if (shader == PIPE_SHADER_COMPUTE) {
 496 #if HAVE_LLVM < 0x0306
 497                         return PIPE_SHADER_IR_LLVM;
 498 #else
 499                         return PIPE_SHADER_IR_NATIVE;
 500 #endif
 501                 } else {
 502                         return PIPE_SHADER_IR_TGSI;
 503                 }
 504         case PIPE_SHADER_CAP_DOUBLES:
 505                 if (rscreen->b.family == CHIP_CYPRESS ||
 506                         rscreen->b.family == CHIP_CAYMAN || rscreen->b.family == CHIP_ARUBA)
 507                         return 1;
 508                 return 0;
 509         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 510         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 511         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 512                 return 0;
 513         }
 514         return 0;
 515 }
 516
 517 static void r600_destroy_screen(struct pipe_screen* pscreen)
 518 {
 519         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 520
 521         if (rscreen == NULL)
 522                 return;
 523
 524         if (!rscreen->b.ws->unref(rscreen->b.ws))
 525                 return;
 526
 527         if (rscreen->global_pool) {
 528                 compute_memory_pool_delete(rscreen->global_pool);
 529         }
 530
 531         r600_destroy_common_screen(&rscreen->b);
 532 }
 533
 534 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
 535                                                   const struct pipe_resource *templ)
 536 {
 537         if (templ->target == PIPE_BUFFER &&
 538             (templ->bind & PIPE_BIND_GLOBAL))
 539                 return r600_compute_global_buffer_create(screen, templ);
 540
 541         return r600_resource_create_common(screen, templ);
 542 }
 543
 544 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 545 {
 546         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 547
 548         if (rscreen == NULL) {
 549                 return NULL;
 550         }
 551
 552         /* Set functions first. */
 553         rscreen->b.b.context_create = r600_create_context;
 554         rscreen->b.b.destroy = r600_destroy_screen;
 555         rscreen->b.b.get_param = r600_get_param;
 556         rscreen->b.b.get_shader_param = r600_get_shader_param;
 557         rscreen->b.b.resource_create = r600_resource_create;
 558
 559         if (!r600_common_screen_init(&rscreen->b, ws)) {
 560                 FREE(rscreen);
 561                 return NULL;
 562         }
 563
 564         if (rscreen->b.info.chip_class >= EVERGREEN) {
 565                 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
 566         } else {
 567                 rscreen->b.b.is_format_supported = r600_is_format_supported;
 568         }
 569
 570         rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
 571         if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
 572                 rscreen->b.debug_flags |= DBG_COMPUTE;
 573         if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
 574                 rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 575         if (!debug_get_bool_option("R600_HYPERZ", TRUE))
 576                 rscreen->b.debug_flags |= DBG_NO_HYPERZ;
 577         if (debug_get_bool_option("R600_LLVM", FALSE))
 578                 rscreen->b.debug_flags |= DBG_LLVM;
 579
 580         if (rscreen->b.family == CHIP_UNKNOWN) {
 581                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
 582                 FREE(rscreen);
 583                 return NULL;
 584         }
 585
 586         /* Figure out streamout kernel support. */
 587         switch (rscreen->b.chip_class) {
 588         case R600:
 589                 if (rscreen->b.family < CHIP_RS780) {
 590                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 591                 } else {
 592                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
 593                 }
 594                 break;
 595         case R700:
 596                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
 597                 break;
 598         case EVERGREEN:
 599         case CAYMAN:
 600                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 601                 break;
 602         default:
 603                 rscreen->b.has_streamout = FALSE;
 604                 break;
 605         }
 606
 607         /* MSAA support. */
 608         switch (rscreen->b.chip_class) {
 609         case R600:
 610         case R700:
 611                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
 612                 rscreen->has_compressed_msaa_texturing = false;
 613                 break;
 614         case EVERGREEN:
 615                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 616                 rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
 617                 break;
 618         case CAYMAN:
 619                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 620                 rscreen->has_compressed_msaa_texturing = true;
 621                 break;
 622         default:
 623                 rscreen->has_msaa = FALSE;
 624                 rscreen->has_compressed_msaa_texturing = false;
 625         }
 626
 627         rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
 628                               !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
 629
 630         rscreen->global_pool = compute_memory_pool_new(rscreen);
 631
 632         /* Create the auxiliary context. This must be done last. */
 633         rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL, 0);
 634
 635 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
 636         struct pipe_resource templ = {};
 637
 638         templ.width0 = 4;
 639         templ.height0 = 2048;
 640         templ.depth0 = 1;
 641         templ.array_size = 1;
 642         templ.target = PIPE_TEXTURE_2D;
 643         templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
 644         templ.usage = PIPE_USAGE_DEFAULT;
 645
 646         struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
 647         unsigned char *map = ws->buffer_map(res->cs_buf, NULL, PIPE_TRANSFER_WRITE);
 648
 649         memset(map, 0, 256);
 650
 651         r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
 652         r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
 653         r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
 654         r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
 655         r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
 656
 657         ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
 658
 659         int i;
 660         for (i = 0; i < 256; i++) {
 661                 printf("%02X", map[i]);
 662                 if (i % 16 == 15)
 663                         printf("\n");
 664         }
 665 #endif
 666
 667         return &rscreen->b.b;
 668 }