src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include <errno.h>
  25 #include "pipe/p_defines.h"
  26 #include "pipe/p_state.h"
  27 #include "pipe/p_context.h"
  28 #include "tgsi/tgsi_scan.h"
  29 #include "tgsi/tgsi_parse.h"
  30 #include "tgsi/tgsi_util.h"
  31 #include "util/u_blitter.h"
  32 #include "util/u_double_list.h"
  33 #include "util/u_format.h"
  34 #include "util/u_format_s3tc.h"
  35 #include "util/u_transfer.h"
  36 #include "util/u_surface.h"
  37 #include "util/u_pack_color.h"
  38 #include "util/u_memory.h"
  39 #include "util/u_inlines.h"
  40 #include "util/u_upload_mgr.h"
  41 #include "vl/vl_decoder.h"
  42 #include "vl/vl_video_buffer.h"
  43 #include "os/os_time.h"
  44 #include "pipebuffer/pb_buffer.h"
  45 #include "r600.h"
  46 #include "r600d.h"
  47 #include "r600_resource.h"
  48 #include "r600_shader.h"
  49 #include "r600_pipe.h"
  50
  51 /*
  52  * pipe_context
  53  */
  54 static struct r600_fence *r600_create_fence(struct r600_context *rctx)
  55 {
  56         struct r600_screen *rscreen = rctx->screen;
  57         struct r600_fence *fence = NULL;
  58
  59         pipe_mutex_lock(rscreen->fences.mutex);
  60
  61         if (!rscreen->fences.bo) {
  62                 /* Create the shared buffer object */
  63                 rscreen->fences.bo = (struct r600_resource*)
  64                         pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
  65                                            PIPE_USAGE_STAGING, 4096);
  66                 if (!rscreen->fences.bo) {
  67                         R600_ERR("r600: failed to create bo for fence objects\n");
  68                         goto out;
  69                 }
  70                 rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->buf,
  71                                                            rctx->cs,
  72                                                            PIPE_TRANSFER_READ_WRITE);
  73         }
  74
  75         if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
  76                 struct r600_fence *entry;
  77
  78                 /* Try to find a freed fence that has been signalled */
  79                 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
  80                         if (rscreen->fences.data[entry->index] != 0) {
  81                                 LIST_DELINIT(&entry->head);
  82                                 fence = entry;
  83                                 break;
  84                         }
  85                 }
  86         }
  87
  88         if (!fence) {
  89                 /* Allocate a new fence */
  90                 struct r600_fence_block *block;
  91                 unsigned index;
  92
  93                 if ((rscreen->fences.next_index + 1) >= 1024) {
  94                         R600_ERR("r600: too many concurrent fences\n");
  95                         goto out;
  96                 }
  97
  98                 index = rscreen->fences.next_index++;
  99
 100                 if (!(index % FENCE_BLOCK_SIZE)) {
 101                         /* Allocate a new block */
 102                         block = CALLOC_STRUCT(r600_fence_block);
 103                         if (block == NULL)
 104                                 goto out;
 105
 106                         LIST_ADD(&block->head, &rscreen->fences.blocks);
 107                 } else {
 108                         block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
 109                 }
 110
 111                 fence = &block->fences[index % FENCE_BLOCK_SIZE];
 112                 fence->index = index;
 113         }
 114
 115         pipe_reference_init(&fence->reference, 1);
 116
 117         rscreen->fences.data[fence->index] = 0;
 118         r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
 119 out:
 120         pipe_mutex_unlock(rscreen->fences.mutex);
 121         return fence;
 122 }
 123
 124
 125 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 126                 unsigned flags)
 127 {
 128         struct r600_context *rctx = (struct r600_context *)ctx;
 129         struct r600_fence **rfence = (struct r600_fence**)fence;
 130         struct pipe_query *render_cond = NULL;
 131         unsigned render_cond_mode = 0;
 132
 133         if (rfence)
 134                 *rfence = r600_create_fence(rctx);
 135
 136         /* Disable render condition. */
 137         if (rctx->current_render_cond) {
 138                 render_cond = rctx->current_render_cond;
 139                 render_cond_mode = rctx->current_render_cond_mode;
 140                 ctx->render_condition(ctx, NULL, 0);
 141         }
 142
 143         r600_context_flush(rctx, flags);
 144
 145         /* Re-enable render condition. */
 146         if (render_cond) {
 147                 ctx->render_condition(ctx, render_cond, render_cond_mode);
 148         }
 149 }
 150
 151 static void r600_flush_from_st(struct pipe_context *ctx,
 152                                struct pipe_fence_handle **fence)
 153 {
 154         r600_flush(ctx, fence, 0);
 155 }
 156
 157 static void r600_flush_from_winsys(void *ctx, unsigned flags)
 158 {
 159         r600_flush((struct pipe_context*)ctx, NULL, flags);
 160 }
 161
 162 static void r600_update_num_contexts(struct r600_screen *rscreen, int diff)
 163 {
 164         pipe_mutex_lock(rscreen->mutex_num_contexts);
 165         if (diff > 0) {
 166                 rscreen->num_contexts++;
 167
 168                 if (rscreen->num_contexts > 1)
 169                         util_slab_set_thread_safety(&rscreen->pool_buffers,
 170                                                     UTIL_SLAB_MULTITHREADED);
 171         } else {
 172                 rscreen->num_contexts--;
 173
 174                 if (rscreen->num_contexts <= 1)
 175                         util_slab_set_thread_safety(&rscreen->pool_buffers,
 176                                                     UTIL_SLAB_SINGLETHREADED);
 177         }
 178         pipe_mutex_unlock(rscreen->mutex_num_contexts);
 179 }
 180
 181 static void r600_destroy_context(struct pipe_context *context)
 182 {
 183         struct r600_context *rctx = (struct r600_context *)context;
 184
 185         rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
 186         util_unreference_framebuffer_state(&rctx->framebuffer);
 187
 188         r600_context_fini(rctx);
 189
 190         util_blitter_destroy(rctx->blitter);
 191
 192         for (int i = 0; i < R600_PIPE_NSTATES; i++) {
 193                 free(rctx->states[i]);
 194         }
 195
 196         u_vbuf_destroy(rctx->vbuf_mgr);
 197         util_slab_destroy(&rctx->pool_transfers);
 198
 199         r600_update_num_contexts(rctx->screen, -1);
 200
 201         FREE(rctx);
 202 }
 203
 204 static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 205 {
 206         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 207         struct r600_screen* rscreen = (struct r600_screen *)screen;
 208
 209         if (rctx == NULL)
 210                 return NULL;
 211
 212         r600_update_num_contexts(rscreen, 1);
 213
 214         rctx->context.winsys = rscreen->screen.winsys;
 215         rctx->context.screen = screen;
 216         rctx->context.priv = priv;
 217         rctx->context.destroy = r600_destroy_context;
 218         rctx->context.flush = r600_flush_from_st;
 219
 220         /* Easy accessing of screen/winsys. */
 221         rctx->screen = rscreen;
 222         rctx->ws = rscreen->ws;
 223         rctx->family = rscreen->family;
 224         rctx->chip_class = rscreen->chip_class;
 225
 226         r600_init_blit_functions(rctx);
 227         r600_init_query_functions(rctx);
 228         r600_init_context_resource_functions(rctx);
 229         r600_init_surface_functions(rctx);
 230         rctx->context.draw_vbo = r600_draw_vbo;
 231
 232         rctx->context.create_video_decoder = vl_create_decoder;
 233         rctx->context.create_video_buffer = vl_video_buffer_create;
 234
 235         r600_init_common_atoms(rctx);
 236
 237         switch (rctx->chip_class) {
 238         case R600:
 239         case R700:
 240                 r600_init_state_functions(rctx);
 241                 if (r600_context_init(rctx)) {
 242                         r600_destroy_context(&rctx->context);
 243                         return NULL;
 244                 }
 245                 r600_init_config(rctx);
 246                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 247                 break;
 248         case EVERGREEN:
 249         case CAYMAN:
 250                 evergreen_init_state_functions(rctx);
 251                 if (evergreen_context_init(rctx)) {
 252                         r600_destroy_context(&rctx->context);
 253                         return NULL;
 254                 }
 255                 evergreen_init_config(rctx);
 256                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 257                 break;
 258         default:
 259                 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
 260                 r600_destroy_context(&rctx->context);
 261                 return NULL;
 262         }
 263
 264         rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx);
 265
 266         util_slab_create(&rctx->pool_transfers,
 267                          sizeof(struct pipe_transfer), 64,
 268                          UTIL_SLAB_SINGLETHREADED);
 269
 270         rctx->vbuf_mgr = u_vbuf_create(&rctx->context, 1024 * 1024, 256,
 271                                            PIPE_BIND_VERTEX_BUFFER |
 272                                            PIPE_BIND_INDEX_BUFFER |
 273                                            PIPE_BIND_CONSTANT_BUFFER,
 274                                            U_VERTEX_FETCH_DWORD_ALIGNED);
 275         if (!rctx->vbuf_mgr) {
 276                 r600_destroy_context(&rctx->context);
 277                 return NULL;
 278         }
 279         rctx->vbuf_mgr->caps.format_fixed32 = 0;
 280
 281         rctx->blitter = util_blitter_create(&rctx->context);
 282         if (rctx->blitter == NULL) {
 283                 r600_destroy_context(&rctx->context);
 284                 return NULL;
 285         }
 286
 287         LIST_INITHEAD(&rctx->dirty_states);
 288
 289         r600_get_backend_mask(rctx); /* this emits commands and must be last */
 290
 291         return &rctx->context;
 292 }
 293
 294 /*
 295  * pipe_screen
 296  */
 297 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 298 {
 299         return "X.Org";
 300 }
 301
 302 static const char *r600_get_family_name(enum radeon_family family)
 303 {
 304         switch(family) {
 305         case CHIP_R600: return "AMD R600";
 306         case CHIP_RV610: return "AMD RV610";
 307         case CHIP_RV630: return "AMD RV630";
 308         case CHIP_RV670: return "AMD RV670";
 309         case CHIP_RV620: return "AMD RV620";
 310         case CHIP_RV635: return "AMD RV635";
 311         case CHIP_RS780: return "AMD RS780";
 312         case CHIP_RS880: return "AMD RS880";
 313         case CHIP_RV770: return "AMD RV770";
 314         case CHIP_RV730: return "AMD RV730";
 315         case CHIP_RV710: return "AMD RV710";
 316         case CHIP_RV740: return "AMD RV740";
 317         case CHIP_CEDAR: return "AMD CEDAR";
 318         case CHIP_REDWOOD: return "AMD REDWOOD";
 319         case CHIP_JUNIPER: return "AMD JUNIPER";
 320         case CHIP_CYPRESS: return "AMD CYPRESS";
 321         case CHIP_HEMLOCK: return "AMD HEMLOCK";
 322         case CHIP_PALM: return "AMD PALM";
 323         case CHIP_SUMO: return "AMD SUMO";
 324         case CHIP_SUMO2: return "AMD SUMO2";
 325         case CHIP_BARTS: return "AMD BARTS";
 326         case CHIP_TURKS: return "AMD TURKS";
 327         case CHIP_CAICOS: return "AMD CAICOS";
 328         case CHIP_CAYMAN: return "AMD CAYMAN";
 329         default: return "AMD unknown";
 330         }
 331 }
 332
 333 static const char* r600_get_name(struct pipe_screen* pscreen)
 334 {
 335         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 336
 337         return r600_get_family_name(rscreen->family);
 338 }
 339
 340 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 341 {
 342         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 343         enum radeon_family family = rscreen->family;
 344
 345         switch (param) {
 346         /* Supported features (boolean caps). */
 347         case PIPE_CAP_NPOT_TEXTURES:
 348         case PIPE_CAP_TWO_SIDED_STENCIL:
 349         case PIPE_CAP_DUAL_SOURCE_BLEND:
 350         case PIPE_CAP_ANISOTROPIC_FILTER:
 351         case PIPE_CAP_POINT_SPRITE:
 352         case PIPE_CAP_OCCLUSION_QUERY:
 353         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 354         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 355         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 356         case PIPE_CAP_TEXTURE_SWIZZLE:
 357         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 358         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 359         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 360         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 361         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 362         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 363         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 364         case PIPE_CAP_SM3:
 365         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 366         case PIPE_CAP_PRIMITIVE_RESTART:
 367         case PIPE_CAP_CONDITIONAL_RENDER:
 368         case PIPE_CAP_TEXTURE_BARRIER:
 369         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 370                 return 1;
 371
 372         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 373                 return debug_get_bool_option("R600_GLSL130", FALSE) ? 130 : 120;
 374
 375         /* Supported except the original R600. */
 376         case PIPE_CAP_INDEP_BLEND_ENABLE:
 377         case PIPE_CAP_INDEP_BLEND_FUNC:
 378                 /* R600 doesn't support per-MRT blends */
 379                 return family == CHIP_R600 ? 0 : 1;
 380
 381         /* Supported on Evergreen. */
 382         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 383                 return family >= CHIP_CEDAR ? 1 : 0;
 384
 385         /* Unsupported features. */
 386         case PIPE_CAP_TGSI_INSTANCEID:
 387         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 388         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 389         case PIPE_CAP_SCALED_RESOLVE:
 390         case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 391         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 392         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 393         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 394                 return 0;
 395
 396         /* Stream output. */
 397         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 398                 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 4 : 0;
 399         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 400                 return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 1 : 0;
 401         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 402         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 403                 return 16*4;
 404
 405         /* Texturing. */
 406         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 407         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 408         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 409                 if (family >= CHIP_CEDAR)
 410                         return 15;
 411                 else
 412                         return 14;
 413         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 414                 return rscreen->info.drm_minor >= 9 ?
 415                         (family >= CHIP_CEDAR ? 16384 : 8192) : 0;
 416         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 417                 return 32;
 418
 419         /* Render targets. */
 420         case PIPE_CAP_MAX_RENDER_TARGETS:
 421                 /* FIXME some r6xx are buggy and can only do 4 */
 422                 return 8;
 423
 424         /* Timer queries, present when the clock frequency is non zero. */
 425         case PIPE_CAP_TIMER_QUERY:
 426                 return rscreen->info.r600_clock_crystal_freq != 0;
 427
 428         case PIPE_CAP_MIN_TEXEL_OFFSET:
 429                 return -8;
 430
 431         case PIPE_CAP_MAX_TEXEL_OFFSET:
 432                 return 7;
 433         }
 434         return 0;
 435 }
 436
 437 static float r600_get_paramf(struct pipe_screen* pscreen,
 438                              enum pipe_capf param)
 439 {
 440         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 441         enum radeon_family family = rscreen->family;
 442
 443         switch (param) {
 444         case PIPE_CAPF_MAX_LINE_WIDTH:
 445         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 446         case PIPE_CAPF_MAX_POINT_WIDTH:
 447         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 448                 if (family >= CHIP_CEDAR)
 449                         return 16384.0f;
 450                 else
 451                         return 8192.0f;
 452         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 453                 return 16.0f;
 454         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 455                 return 16.0f;
 456         case PIPE_CAPF_GUARD_BAND_LEFT:
 457         case PIPE_CAPF_GUARD_BAND_TOP:
 458         case PIPE_CAPF_GUARD_BAND_RIGHT:
 459         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 460                 return 0.0f;
 461         }
 462         return 0.0f;
 463 }
 464
 465 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 466 {
 467         switch(shader)
 468         {
 469         case PIPE_SHADER_FRAGMENT:
 470         case PIPE_SHADER_VERTEX:
 471                 break;
 472         case PIPE_SHADER_GEOMETRY:
 473                 /* TODO: support and enable geometry programs */
 474                 return 0;
 475         default:
 476                 /* TODO: support tessellation on Evergreen */
 477                 return 0;
 478         }
 479
 480         /* TODO: all these should be fixed, since r600 surely supports much more! */
 481         switch (param) {
 482         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 483         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 484         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 485         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 486                 return 16384;
 487         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 488                 return 8; /* FIXME */
 489         case PIPE_SHADER_CAP_MAX_INPUTS:
 490                 if(shader == PIPE_SHADER_FRAGMENT)
 491                         return 34;
 492                 else
 493                         return 32;
 494         case PIPE_SHADER_CAP_MAX_TEMPS:
 495                 return 256; /* Max native temporaries. */
 496         case PIPE_SHADER_CAP_MAX_ADDRS:
 497                 /* FIXME Isn't this equal to TEMPS? */
 498                 return 1; /* Max native address registers */
 499         case PIPE_SHADER_CAP_MAX_CONSTS:
 500                 return R600_MAX_CONST_BUFFER_SIZE;
 501         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 502                 return R600_MAX_CONST_BUFFERS-1;
 503         case PIPE_SHADER_CAP_MAX_PREDS:
 504                 return 0; /* FIXME */
 505         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 506                 return 1;
 507         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 508         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 509         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 510         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 511                 return 1;
 512         case PIPE_SHADER_CAP_SUBROUTINES:
 513                 return 0;
 514         case PIPE_SHADER_CAP_INTEGERS:
 515                 return 0;
 516         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 517                 return 16;
 518         case PIPE_SHADER_CAP_OUTPUT_READ:
 519                 return 1;
 520         }
 521         return 0;
 522 }
 523
 524 static int r600_get_video_param(struct pipe_screen *screen,
 525                                 enum pipe_video_profile profile,
 526                                 enum pipe_video_cap param)
 527 {
 528         switch (param) {
 529         case PIPE_VIDEO_CAP_SUPPORTED:
 530                 return vl_profile_supported(screen, profile);
 531         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 532                 return 1;
 533         case PIPE_VIDEO_CAP_MAX_WIDTH:
 534         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 535                 return vl_video_buffer_max_size(screen);
 536         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 537                 return PIPE_FORMAT_NV12;
 538         case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
 539                 return false;
 540         case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
 541                 return false;
 542         case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
 543                 return true;
 544         default:
 545                 return 0;
 546         }
 547 }
 548
 549 static void r600_destroy_screen(struct pipe_screen* pscreen)
 550 {
 551         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 552
 553         if (rscreen == NULL)
 554                 return;
 555
 556         if (rscreen->fences.bo) {
 557                 struct r600_fence_block *entry, *tmp;
 558
 559                 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
 560                         LIST_DEL(&entry->head);
 561                         FREE(entry);
 562                 }
 563
 564                 rscreen->ws->buffer_unmap(rscreen->fences.bo->buf);
 565                 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
 566         }
 567         pipe_mutex_destroy(rscreen->fences.mutex);
 568
 569         rscreen->ws->destroy(rscreen->ws);
 570
 571         util_slab_destroy(&rscreen->pool_buffers);
 572         pipe_mutex_destroy(rscreen->mutex_num_contexts);
 573         FREE(rscreen);
 574 }
 575
 576 static void r600_fence_reference(struct pipe_screen *pscreen,
 577                                  struct pipe_fence_handle **ptr,
 578                                  struct pipe_fence_handle *fence)
 579 {
 580         struct r600_fence **oldf = (struct r600_fence**)ptr;
 581         struct r600_fence *newf = (struct r600_fence*)fence;
 582
 583         if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
 584                 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 585                 pipe_mutex_lock(rscreen->fences.mutex);
 586                 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
 587                 pipe_mutex_unlock(rscreen->fences.mutex);
 588         }
 589
 590         *ptr = fence;
 591 }
 592
 593 static boolean r600_fence_signalled(struct pipe_screen *pscreen,
 594                                     struct pipe_fence_handle *fence)
 595 {
 596         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 597         struct r600_fence *rfence = (struct r600_fence*)fence;
 598
 599         return rscreen->fences.data[rfence->index];
 600 }
 601
 602 static boolean r600_fence_finish(struct pipe_screen *pscreen,
 603                                  struct pipe_fence_handle *fence,
 604                                  uint64_t timeout)
 605 {
 606         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 607         struct r600_fence *rfence = (struct r600_fence*)fence;
 608         int64_t start_time = 0;
 609         unsigned spins = 0;
 610
 611         if (timeout != PIPE_TIMEOUT_INFINITE) {
 612                 start_time = os_time_get();
 613
 614                 /* Convert to microseconds. */
 615                 timeout /= 1000;
 616         }
 617
 618         while (rscreen->fences.data[rfence->index] == 0) {
 619                 if (++spins % 256)
 620                         continue;
 621 #ifdef PIPE_OS_UNIX
 622                 sched_yield();
 623 #else
 624                 os_time_sleep(10);
 625 #endif
 626                 if (timeout != PIPE_TIMEOUT_INFINITE &&
 627                     os_time_get() - start_time >= timeout) {
 628                         return FALSE;
 629                 }
 630         }
 631
 632         return TRUE;
 633 }
 634
 635 static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 636 {
 637         switch ((tiling_config & 0xe) >> 1) {
 638         case 0:
 639                 rscreen->tiling_info.num_channels = 1;
 640                 break;
 641         case 1:
 642                 rscreen->tiling_info.num_channels = 2;
 643                 break;
 644         case 2:
 645                 rscreen->tiling_info.num_channels = 4;
 646                 break;
 647         case 3:
 648                 rscreen->tiling_info.num_channels = 8;
 649                 break;
 650         default:
 651                 return -EINVAL;
 652         }
 653
 654         switch ((tiling_config & 0x30) >> 4) {
 655         case 0:
 656                 rscreen->tiling_info.num_banks = 4;
 657                 break;
 658         case 1:
 659                 rscreen->tiling_info.num_banks = 8;
 660                 break;
 661         default:
 662                 return -EINVAL;
 663
 664         }
 665         switch ((tiling_config & 0xc0) >> 6) {
 666         case 0:
 667                 rscreen->tiling_info.group_bytes = 256;
 668                 break;
 669         case 1:
 670                 rscreen->tiling_info.group_bytes = 512;
 671                 break;
 672         default:
 673                 return -EINVAL;
 674         }
 675         return 0;
 676 }
 677
 678 static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
 679 {
 680         switch (tiling_config & 0xf) {
 681         case 0:
 682                 rscreen->tiling_info.num_channels = 1;
 683                 break;
 684         case 1:
 685                 rscreen->tiling_info.num_channels = 2;
 686                 break;
 687         case 2:
 688                 rscreen->tiling_info.num_channels = 4;
 689                 break;
 690         case 3:
 691                 rscreen->tiling_info.num_channels = 8;
 692                 break;
 693         default:
 694                 return -EINVAL;
 695         }
 696
 697         switch ((tiling_config & 0xf0) >> 4) {
 698         case 0:
 699                 rscreen->tiling_info.num_banks = 4;
 700                 break;
 701         case 1:
 702                 rscreen->tiling_info.num_banks = 8;
 703                 break;
 704         case 2:
 705                 rscreen->tiling_info.num_banks = 16;
 706                 break;
 707         default:
 708                 return -EINVAL;
 709         }
 710
 711         switch ((tiling_config & 0xf00) >> 8) {
 712         case 0:
 713                 rscreen->tiling_info.group_bytes = 256;
 714                 break;
 715         case 1:
 716                 rscreen->tiling_info.group_bytes = 512;
 717                 break;
 718         default:
 719                 return -EINVAL;
 720         }
 721         return 0;
 722 }
 723
 724 static int r600_init_tiling(struct r600_screen *rscreen)
 725 {
 726         uint32_t tiling_config = rscreen->info.r600_tiling_config;
 727
 728         /* set default group bytes, overridden by tiling info ioctl */
 729         if (rscreen->chip_class <= R700) {
 730                 rscreen->tiling_info.group_bytes = 256;
 731         } else {
 732                 rscreen->tiling_info.group_bytes = 512;
 733         }
 734
 735         if (!tiling_config)
 736                 return 0;
 737
 738         if (rscreen->chip_class <= R700) {
 739                 return r600_interpret_tiling(rscreen, tiling_config);
 740         } else {
 741                 return evergreen_interpret_tiling(rscreen, tiling_config);
 742         }
 743 }
 744
 745 static unsigned radeon_family_from_device(unsigned device)
 746 {
 747         switch (device) {
 748 #define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
 749 #include "pci_ids/r600_pci_ids.h"
 750 #undef CHIPSET
 751         default:
 752                 return CHIP_UNKNOWN;
 753         }
 754 }
 755
 756 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 757 {
 758         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 759         if (rscreen == NULL) {
 760                 return NULL;
 761         }
 762
 763         rscreen->ws = ws;
 764         ws->query_info(ws, &rscreen->info);
 765
 766         rscreen->family = radeon_family_from_device(rscreen->info.pci_id);
 767         if (rscreen->family == CHIP_UNKNOWN) {
 768                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
 769                 FREE(rscreen);
 770                 return NULL;
 771         }
 772
 773         /* setup class */
 774         if (rscreen->family == CHIP_CAYMAN) {
 775                 rscreen->chip_class = CAYMAN;
 776         } else if (rscreen->family >= CHIP_CEDAR) {
 777                 rscreen->chip_class = EVERGREEN;
 778         } else if (rscreen->family >= CHIP_RV770) {
 779                 rscreen->chip_class = R700;
 780         } else {
 781                 rscreen->chip_class = R600;
 782         }
 783
 784         if (r600_init_tiling(rscreen)) {
 785                 FREE(rscreen);
 786                 return NULL;
 787         }
 788
 789         rscreen->screen.winsys = (struct pipe_winsys*)ws;
 790         rscreen->screen.destroy = r600_destroy_screen;
 791         rscreen->screen.get_name = r600_get_name;
 792         rscreen->screen.get_vendor = r600_get_vendor;
 793         rscreen->screen.get_param = r600_get_param;
 794         rscreen->screen.get_shader_param = r600_get_shader_param;
 795         rscreen->screen.get_paramf = r600_get_paramf;
 796         rscreen->screen.get_video_param = r600_get_video_param;
 797         if (rscreen->chip_class >= EVERGREEN) {
 798                 rscreen->screen.is_format_supported = evergreen_is_format_supported;
 799         } else {
 800                 rscreen->screen.is_format_supported = r600_is_format_supported;
 801         }
 802         rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
 803         rscreen->screen.context_create = r600_create_context;
 804         rscreen->screen.fence_reference = r600_fence_reference;
 805         rscreen->screen.fence_signalled = r600_fence_signalled;
 806         rscreen->screen.fence_finish = r600_fence_finish;
 807         r600_init_screen_resource_functions(&rscreen->screen);
 808
 809         util_format_s3tc_init();
 810
 811         util_slab_create(&rscreen->pool_buffers,
 812                          sizeof(struct r600_resource), 64,
 813                          UTIL_SLAB_SINGLETHREADED);
 814
 815         pipe_mutex_init(rscreen->mutex_num_contexts);
 816
 817         rscreen->fences.bo = NULL;
 818         rscreen->fences.data = NULL;
 819         rscreen->fences.next_index = 0;
 820         LIST_INITHEAD(&rscreen->fences.pool);
 821         LIST_INITHEAD(&rscreen->fences.blocks);
 822         pipe_mutex_init(rscreen->fences.mutex);
 823
 824         return &rscreen->screen;
 825 }