src/gallium/drivers/r600/r600_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_pipe.h"
  24 #include "r600_public.h"
  25 #include "r600_isa.h"
  26 #include "evergreen_compute.h"
  27 #include "r600d.h"
  28
  29 #include "sb/sb_public.h"
  30
  31 #include <errno.h>
  32 #include "pipe/p_shader_tokens.h"
  33 #include "util/u_debug.h"
  34 #include "util/u_memory.h"
  35 #include "util/u_simple_shaders.h"
  36 #include "util/u_upload_mgr.h"
  37 #include "util/u_math.h"
  38 #include "vl/vl_decoder.h"
  39 #include "vl/vl_video_buffer.h"
  40 #include "radeon/radeon_video.h"
  41 #include "radeon/radeon_uvd.h"
  42 #include "os/os_time.h"
  43
  44 static const struct debug_named_value r600_debug_options[] = {
  45         /* features */
  46         { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
  47
  48         /* shader backend */
  49         { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
  50         { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
  51         { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
  52         { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
  53         { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
  54         { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
  55         { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
  56         { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
  57
  58         DEBUG_NAMED_VALUE_END /* must be last */
  59 };
  60
  61 /*
  62  * pipe_context
  63  */
  64
  65 static void r600_destroy_context(struct pipe_context *context)
  66 {
  67         struct r600_context *rctx = (struct r600_context *)context;
  68         unsigned sh;
  69
  70         r600_isa_destroy(rctx->isa);
  71
  72         r600_sb_context_destroy(rctx->sb_context);
  73
  74         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
  75         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
  76
  77         for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
  78                 rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, NULL);
  79                 free(rctx->driver_consts[sh].constants);
  80         }
  81
  82         if (rctx->fixed_func_tcs_shader)
  83                 rctx->b.b.delete_tcs_state(&rctx->b.b, rctx->fixed_func_tcs_shader);
  84
  85         if (rctx->dummy_pixel_shader) {
  86                 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
  87         }
  88         if (rctx->custom_dsa_flush) {
  89                 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
  90         }
  91         if (rctx->custom_blend_resolve) {
  92                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
  93         }
  94         if (rctx->custom_blend_decompress) {
  95                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
  96         }
  97         if (rctx->custom_blend_fastclear) {
  98                 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
  99         }
 100         util_unreference_framebuffer_state(&rctx->framebuffer.state);
 101
 102         if (rctx->blitter) {
 103                 util_blitter_destroy(rctx->blitter);
 104         }
 105         if (rctx->allocator_fetch_shader) {
 106                 u_suballocator_destroy(rctx->allocator_fetch_shader);
 107         }
 108
 109         r600_release_command_buffer(&rctx->start_cs_cmd);
 110
 111         FREE(rctx->start_compute_cs_cmd.buf);
 112
 113         r600_common_context_cleanup(&rctx->b);
 114         FREE(rctx);
 115 }
 116
 117 static struct pipe_context *r600_create_context(struct pipe_screen *screen,
 118                                                 void *priv, unsigned flags)
 119 {
 120         struct r600_context *rctx = CALLOC_STRUCT(r600_context);
 121         struct r600_screen* rscreen = (struct r600_screen *)screen;
 122         struct radeon_winsys *ws = rscreen->b.ws;
 123
 124         if (!rctx)
 125                 return NULL;
 126
 127         rctx->b.b.screen = screen;
 128         rctx->b.b.priv = priv;
 129         rctx->b.b.destroy = r600_destroy_context;
 130         rctx->b.set_atom_dirty = (void *)r600_set_atom_dirty;
 131
 132         if (!r600_common_context_init(&rctx->b, &rscreen->b))
 133                 goto fail;
 134
 135         rctx->screen = rscreen;
 136
 137         r600_init_blit_functions(rctx);
 138
 139         if (rscreen->b.info.has_uvd) {
 140                 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
 141                 rctx->b.b.create_video_buffer = r600_video_buffer_create;
 142         } else {
 143                 rctx->b.b.create_video_codec = vl_create_decoder;
 144                 rctx->b.b.create_video_buffer = vl_video_buffer_create;
 145         }
 146
 147         r600_init_common_state_functions(rctx);
 148
 149         switch (rctx->b.chip_class) {
 150         case R600:
 151         case R700:
 152                 r600_init_state_functions(rctx);
 153                 r600_init_atom_start_cs(rctx);
 154                 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 155                 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
 156                                                                       : r600_create_resolve_blend(rctx);
 157                 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
 158                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
 159                                            rctx->b.family == CHIP_RV620 ||
 160                                            rctx->b.family == CHIP_RS780 ||
 161                                            rctx->b.family == CHIP_RS880 ||
 162                                            rctx->b.family == CHIP_RV710);
 163                 break;
 164         case EVERGREEN:
 165         case CAYMAN:
 166                 evergreen_init_state_functions(rctx);
 167                 evergreen_init_atom_start_cs(rctx);
 168                 evergreen_init_atom_start_compute_cs(rctx);
 169                 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 170                 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
 171                 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
 172                 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
 173                 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
 174                                            rctx->b.family == CHIP_PALM ||
 175                                            rctx->b.family == CHIP_SUMO ||
 176                                            rctx->b.family == CHIP_SUMO2 ||
 177                                            rctx->b.family == CHIP_CAICOS ||
 178                                            rctx->b.family == CHIP_CAYMAN ||
 179                                            rctx->b.family == CHIP_ARUBA);
 180                 break;
 181         default:
 182                 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
 183                 goto fail;
 184         }
 185
 186         rctx->b.gfx.cs = ws->cs_create(rctx->b.ctx, RING_GFX,
 187                                        r600_context_gfx_flush, rctx);
 188         rctx->b.gfx.flush = r600_context_gfx_flush;
 189
 190         rctx->allocator_fetch_shader = u_suballocator_create(&rctx->b.b, 64 * 1024,
 191                                                              0, PIPE_USAGE_DEFAULT, FALSE);
 192         if (!rctx->allocator_fetch_shader)
 193                 goto fail;
 194
 195         rctx->isa = calloc(1, sizeof(struct r600_isa));
 196         if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
 197                 goto fail;
 198
 199         if (rscreen->b.debug_flags & DBG_FORCE_DMA)
 200                 rctx->b.b.resource_copy_region = rctx->b.dma_copy;
 201
 202         rctx->blitter = util_blitter_create(&rctx->b.b);
 203         if (rctx->blitter == NULL)
 204                 goto fail;
 205         util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
 206         rctx->blitter->draw_rectangle = r600_draw_rectangle;
 207
 208         r600_begin_new_cs(rctx);
 209         r600_query_init_backend_mask(&rctx->b); /* this emits commands and must be last */
 210
 211         rctx->dummy_pixel_shader =
 212                 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
 213                                                      TGSI_SEMANTIC_GENERIC,
 214                                                      TGSI_INTERPOLATE_CONSTANT);
 215         rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
 216
 217         return &rctx->b.b;
 218
 219 fail:
 220         r600_destroy_context(&rctx->b.b);
 221         return NULL;
 222 }
 223
 224 /*
 225  * pipe_screen
 226  */
 227
 228 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 229 {
 230         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 231         enum radeon_family family = rscreen->b.family;
 232
 233         switch (param) {
 234         /* Supported features (boolean caps). */
 235         case PIPE_CAP_NPOT_TEXTURES:
 236         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 237         case PIPE_CAP_TWO_SIDED_STENCIL:
 238         case PIPE_CAP_ANISOTROPIC_FILTER:
 239         case PIPE_CAP_POINT_SPRITE:
 240         case PIPE_CAP_OCCLUSION_QUERY:
 241         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 242         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 243         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 244         case PIPE_CAP_TEXTURE_SWIZZLE:
 245         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 246         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 247         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 248         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 249         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 250         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 251         case PIPE_CAP_SM3:
 252         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 253         case PIPE_CAP_PRIMITIVE_RESTART:
 254         case PIPE_CAP_CONDITIONAL_RENDER:
 255         case PIPE_CAP_TEXTURE_BARRIER:
 256         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 257         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 258         case PIPE_CAP_TGSI_INSTANCEID:
 259         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 260         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 261         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 262         case PIPE_CAP_USER_INDEX_BUFFERS:
 263         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 264         case PIPE_CAP_START_INSTANCE:
 265         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 266         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 267         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 268         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 269         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 270         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 271         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 272         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 273         case PIPE_CAP_SAMPLE_SHADING:
 274         case PIPE_CAP_CLIP_HALFZ:
 275         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 276         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 277         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 278         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 279         case PIPE_CAP_TGSI_TXQS:
 280         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 281         case PIPE_CAP_INVALIDATE_BUFFER:
 282         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 283         case PIPE_CAP_QUERY_MEMORY_INFO:
 284         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 285         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 286                 return 1;
 287
 288         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 289                 return rscreen->b.info.drm_major == 2 && rscreen->b.info.drm_minor >= 43;
 290
 291         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 292                 return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;
 293
 294         case PIPE_CAP_COMPUTE:
 295                 return rscreen->b.chip_class > R700;
 296
 297         case PIPE_CAP_TGSI_TEXCOORD:
 298                 return 0;
 299
 300         case PIPE_CAP_FAKE_SW_MSAA:
 301                 return 0;
 302
 303         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 304                 return MIN2(rscreen->b.info.vram_size, 0xFFFFFFFF);
 305
 306         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 307                 return R600_MAP_BUFFER_ALIGNMENT;
 308
 309         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 310                 return 256;
 311
 312         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 313                 return 1;
 314
 315         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 316                 if (family >= CHIP_CEDAR)
 317                    return 410;
 318                 /* pre-evergreen geom shaders need newer kernel */
 319                 if (rscreen->b.info.drm_minor >= 37)
 320                    return 330;
 321                 return 140;
 322
 323         /* Supported except the original R600. */
 324         case PIPE_CAP_INDEP_BLEND_ENABLE:
 325         case PIPE_CAP_INDEP_BLEND_FUNC:
 326                 /* R600 doesn't support per-MRT blends */
 327                 return family == CHIP_R600 ? 0 : 1;
 328
 329         /* Supported on Evergreen. */
 330         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 331         case PIPE_CAP_CUBE_MAP_ARRAY:
 332         case PIPE_CAP_TEXTURE_GATHER_SM5:
 333         case PIPE_CAP_TEXTURE_QUERY_LOD:
 334         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 335         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 336                 return family >= CHIP_CEDAR ? 1 : 0;
 337         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 338                 return family >= CHIP_CEDAR ? 4 : 0;
 339         case PIPE_CAP_DRAW_INDIRECT:
 340                 /* kernel command checker support is also required */
 341                 return family >= CHIP_CEDAR && rscreen->b.info.drm_minor >= 41;
 342
 343         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 344                 return family >= CHIP_CEDAR ? 0 : 1;
 345
 346         /* Unsupported features. */
 347         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 348         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 349         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 350         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 351         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 352         case PIPE_CAP_USER_VERTEX_BUFFERS:
 353         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 354         case PIPE_CAP_VERTEXID_NOBASE:
 355         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 356         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 357         case PIPE_CAP_SHAREABLE_SHADERS:
 358         case PIPE_CAP_CLEAR_TEXTURE:
 359         case PIPE_CAP_DRAW_PARAMETERS:
 360         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 361         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 362         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 363         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 364         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 365         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 366         case PIPE_CAP_GENERATE_MIPMAP:
 367         case PIPE_CAP_STRING_MARKER:
 368         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 369         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 370         case PIPE_CAP_CULL_DISTANCE:
 371         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 372         case PIPE_CAP_TGSI_VOTE:
 373         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 374                 return 0;
 375
 376         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 377                 if (family >= CHIP_CEDAR)
 378                         return 30;
 379                 else
 380                         return 0;
 381         /* Stream output. */
 382         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 383                 return rscreen->b.has_streamout ? 4 : 0;
 384         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 385                 return rscreen->b.has_streamout ? 1 : 0;
 386         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 387         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 388                 return 32*4;
 389
 390         /* Geometry shader output. */
 391         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 392                 return 1024;
 393         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 394                 return 16384;
 395         case PIPE_CAP_MAX_VERTEX_STREAMS:
 396                 return family >= CHIP_CEDAR ? 4 : 1;
 397
 398         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 399                 return 2047;
 400
 401         /* Texturing. */
 402         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 403         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 404                 if (family >= CHIP_CEDAR)
 405                         return 15;
 406                 else
 407                         return 14;
 408         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 409                 /* textures support 8192, but layered rendering supports 2048 */
 410                 return 12;
 411         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 412                 /* textures support 8192, but layered rendering supports 2048 */
 413                 return 2048;
 414
 415         /* Render targets. */
 416         case PIPE_CAP_MAX_RENDER_TARGETS:
 417                 /* XXX some r6xx are buggy and can only do 4 */
 418                 return 8;
 419
 420         case PIPE_CAP_MAX_VIEWPORTS:
 421                 return R600_MAX_VIEWPORTS;
 422
 423         /* Timer queries, present when the clock frequency is non zero. */
 424         case PIPE_CAP_QUERY_TIME_ELAPSED:
 425                 return rscreen->b.info.clock_crystal_freq != 0;
 426         case PIPE_CAP_QUERY_TIMESTAMP:
 427                 return rscreen->b.info.drm_minor >= 20 &&
 428                        rscreen->b.info.clock_crystal_freq != 0;
 429
 430         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 431         case PIPE_CAP_MIN_TEXEL_OFFSET:
 432                 return -8;
 433
 434         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 435         case PIPE_CAP_MAX_TEXEL_OFFSET:
 436                 return 7;
 437
 438         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 439                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 440         case PIPE_CAP_ENDIANNESS:
 441                 return PIPE_ENDIAN_LITTLE;
 442
 443         case PIPE_CAP_VENDOR_ID:
 444                 return ATI_VENDOR_ID;
 445         case PIPE_CAP_DEVICE_ID:
 446                 return rscreen->b.info.pci_id;
 447         case PIPE_CAP_ACCELERATED:
 448                 return 1;
 449         case PIPE_CAP_VIDEO_MEMORY:
 450                 return rscreen->b.info.vram_size >> 20;
 451         case PIPE_CAP_UMA:
 452                 return 0;
 453         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 454                 return rscreen->b.chip_class >= R700;
 455         case PIPE_CAP_PCI_GROUP:
 456                 return rscreen->b.info.pci_domain;
 457         case PIPE_CAP_PCI_BUS:
 458                 return rscreen->b.info.pci_bus;
 459         case PIPE_CAP_PCI_DEVICE:
 460                 return rscreen->b.info.pci_dev;
 461         case PIPE_CAP_PCI_FUNCTION:
 462                 return rscreen->b.info.pci_func;
 463         }
 464         return 0;
 465 }
 466
 467 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 468 {
 469         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 470
 471         switch(shader)
 472         {
 473         case PIPE_SHADER_FRAGMENT:
 474         case PIPE_SHADER_VERTEX:
 475         case PIPE_SHADER_COMPUTE:
 476                 break;
 477         case PIPE_SHADER_GEOMETRY:
 478                 if (rscreen->b.family >= CHIP_CEDAR)
 479                         break;
 480                 /* pre-evergreen geom shaders need newer kernel */
 481                 if (rscreen->b.info.drm_minor >= 37)
 482                         break;
 483                 return 0;
 484         case PIPE_SHADER_TESS_CTRL:
 485         case PIPE_SHADER_TESS_EVAL:
 486                 if (rscreen->b.family >= CHIP_CEDAR)
 487                         break;
 488         default:
 489                 return 0;
 490         }
 491
 492         switch (param) {
 493         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 494         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 495         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 496         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 497                 return 16384;
 498         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 499                 return 32;
 500         case PIPE_SHADER_CAP_MAX_INPUTS:
 501                 return shader == PIPE_SHADER_VERTEX ? 16 : 32;
 502         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 503                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 504         case PIPE_SHADER_CAP_MAX_TEMPS:
 505                 return 256; /* Max native temporaries. */
 506         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 507                 if (shader == PIPE_SHADER_COMPUTE) {
 508                         uint64_t max_const_buffer_size;
 509                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 510                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 511                                 &max_const_buffer_size);
 512                         return max_const_buffer_size;
 513
 514                 } else {
 515                         return R600_MAX_CONST_BUFFER_SIZE;
 516                 }
 517         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 518                 return R600_MAX_USER_CONST_BUFFERS;
 519         case PIPE_SHADER_CAP_MAX_PREDS:
 520                 return 0; /* nothing uses this */
 521         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 522                 return 1;
 523         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 524                 return 1;
 525         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 526         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 527         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 528         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 529                 return 1;
 530         case PIPE_SHADER_CAP_SUBROUTINES:
 531                 return 0;
 532         case PIPE_SHADER_CAP_INTEGERS:
 533         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 534                 return 1;
 535         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 536         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 537                 return 16;
 538         case PIPE_SHADER_CAP_PREFERRED_IR:
 539                 if (shader == PIPE_SHADER_COMPUTE) {
 540                         return PIPE_SHADER_IR_NATIVE;
 541                 } else {
 542                         return PIPE_SHADER_IR_TGSI;
 543                 }
 544         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 545                 return 0;
 546         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 547         case PIPE_SHADER_CAP_DOUBLES:
 548                 if (rscreen->b.family == CHIP_ARUBA ||
 549                     rscreen->b.family == CHIP_CAYMAN ||
 550                     rscreen->b.family == CHIP_CYPRESS ||
 551                     rscreen->b.family == CHIP_HEMLOCK)
 552                         return 1;
 553                 return 0;
 554         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 555         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 556         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 557         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 558                 return 0;
 559         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 560                 /* due to a bug in the shader compiler, some loops hang
 561                  * if they are not unrolled, see:
 562                  *    https://bugs.freedesktop.org/show_bug.cgi?id=86720
 563                  */
 564                 return 255;
 565         }
 566         return 0;
 567 }
 568
 569 static void r600_destroy_screen(struct pipe_screen* pscreen)
 570 {
 571         struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 572
 573         if (!rscreen)
 574                 return;
 575
 576         if (!rscreen->b.ws->unref(rscreen->b.ws))
 577                 return;
 578
 579         if (rscreen->global_pool) {
 580                 compute_memory_pool_delete(rscreen->global_pool);
 581         }
 582
 583         r600_destroy_common_screen(&rscreen->b);
 584 }
 585
 586 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
 587                                                   const struct pipe_resource *templ)
 588 {
 589         if (templ->target == PIPE_BUFFER &&
 590             (templ->bind & PIPE_BIND_GLOBAL))
 591                 return r600_compute_global_buffer_create(screen, templ);
 592
 593         return r600_resource_create_common(screen, templ);
 594 }
 595
 596 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 597 {
 598         struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
 599
 600         if (!rscreen) {
 601                 return NULL;
 602         }
 603
 604         /* Set functions first. */
 605         rscreen->b.b.context_create = r600_create_context;
 606         rscreen->b.b.destroy = r600_destroy_screen;
 607         rscreen->b.b.get_param = r600_get_param;
 608         rscreen->b.b.get_shader_param = r600_get_shader_param;
 609         rscreen->b.b.resource_create = r600_resource_create;
 610
 611         if (!r600_common_screen_init(&rscreen->b, ws)) {
 612                 FREE(rscreen);
 613                 return NULL;
 614         }
 615
 616         if (rscreen->b.info.chip_class >= EVERGREEN) {
 617                 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
 618         } else {
 619                 rscreen->b.b.is_format_supported = r600_is_format_supported;
 620         }
 621
 622         rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
 623         if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
 624                 rscreen->b.debug_flags |= DBG_COMPUTE;
 625         if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
 626                 rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS | DBG_TCS | DBG_TES;
 627         if (!debug_get_bool_option("R600_HYPERZ", TRUE))
 628                 rscreen->b.debug_flags |= DBG_NO_HYPERZ;
 629
 630         if (rscreen->b.family == CHIP_UNKNOWN) {
 631                 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
 632                 FREE(rscreen);
 633                 return NULL;
 634         }
 635
 636         /* Figure out streamout kernel support. */
 637         switch (rscreen->b.chip_class) {
 638         case R600:
 639                 if (rscreen->b.family < CHIP_RS780) {
 640                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 641                 } else {
 642                         rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
 643                 }
 644                 break;
 645         case R700:
 646                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
 647                 break;
 648         case EVERGREEN:
 649         case CAYMAN:
 650                 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
 651                 break;
 652         default:
 653                 rscreen->b.has_streamout = FALSE;
 654                 break;
 655         }
 656
 657         /* MSAA support. */
 658         switch (rscreen->b.chip_class) {
 659         case R600:
 660         case R700:
 661                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
 662                 rscreen->has_compressed_msaa_texturing = false;
 663                 break;
 664         case EVERGREEN:
 665                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 666                 rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
 667                 break;
 668         case CAYMAN:
 669                 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
 670                 rscreen->has_compressed_msaa_texturing = true;
 671                 break;
 672         default:
 673                 rscreen->has_msaa = FALSE;
 674                 rscreen->has_compressed_msaa_texturing = false;
 675         }
 676
 677         rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
 678                               !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
 679
 680         rscreen->global_pool = compute_memory_pool_new(rscreen);
 681
 682         /* Create the auxiliary context. This must be done last. */
 683         rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL, 0);
 684
 685 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
 686         struct pipe_resource templ = {};
 687
 688         templ.width0 = 4;
 689         templ.height0 = 2048;
 690         templ.depth0 = 1;
 691         templ.array_size = 1;
 692         templ.target = PIPE_TEXTURE_2D;
 693         templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
 694         templ.usage = PIPE_USAGE_DEFAULT;
 695
 696         struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
 697         unsigned char *map = ws->buffer_map(res->buf, NULL, PIPE_TRANSFER_WRITE);
 698
 699         memset(map, 0, 256);
 700
 701         r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
 702         r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
 703         r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
 704         r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
 705         r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
 706
 707         ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
 708
 709         int i;
 710         for (i = 0; i < 256; i++) {
 711                 printf("%02X", map[i]);
 712                 if (i % 16 == 15)
 713                         printf("\n");
 714         }
 715 #endif
 716
 717         if (rscreen->b.debug_flags & DBG_TEST_DMA)
 718                 r600_test_dma(&rscreen->b);
 719
 720         return &rscreen->b.b;
 721 }