2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "util/u_slab.h"
31 #include "r600_llvm.h"
32 #include "r600_public.h"
33 #include "r600_shader.h"
34 #include "r600_resource.h"
35 #include "evergreen_compute.h"
37 #define R600_MAX_CONST_BUFFERS 2
38 #define R600_MAX_CONST_BUFFER_SIZE 4096
40 #ifdef PIPE_ARCH_BIG_ENDIAN
41 #define R600_BIG_ENDIAN 1
43 #define R600_BIG_ENDIAN 0
46 enum r600_atom_flags
{
47 /* When set, atoms are added at the beginning of the dirty list
48 * instead of the end. */
52 /* This encapsulates a state or an operation which can emitted into the GPU
53 * command stream. It's not limited to states only, it can be used for anything
54 * that wants to write commands into the CS (e.g. cache flushes). */
56 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
);
59 enum r600_atom_flags flags
;
62 struct list_head head
;
65 /* This is an atom containing GPU commands that never change.
66 * This is supposed to be copied directly into the CS. */
67 struct r600_command_buffer
{
68 struct r600_atom atom
;
74 struct r600_surface_sync_cmd
{
75 struct r600_atom atom
;
76 unsigned flush_flags
; /* CP_COHER_CNTL */
79 struct r600_db_misc_state
{
80 struct r600_atom atom
;
81 bool occlusion_query_enabled
;
82 bool flush_depthstencil_through_cb
;
83 bool copy_depth
, copy_stencil
;
87 struct r600_cb_misc_state
{
88 struct r600_atom atom
;
89 unsigned cb_color_control
; /* this comes from blend state */
90 unsigned blend_colormask
; /* 8*4 bits for 8 RGBA colorbuffers */
92 unsigned nr_ps_color_outputs
;
97 struct r600_alphatest_state
{
98 struct r600_atom atom
;
99 unsigned sx_alpha_test_control
; /* this comes from dsa state */
100 unsigned sx_alpha_ref
; /* this comes from dsa state */
102 bool cb0_export_16bpc
; /* from set_framebuffer_state */
105 struct r600_cs_shader_state
{
106 struct r600_atom atom
;
107 struct r600_pipe_compute
*shader
;
110 struct r600_sample_mask
{
111 struct r600_atom atom
;
112 uint16_t sample_mask
; /* there are only 8 bits on EG, 16 bits on Cayman */
115 enum r600_pipe_state_id
{
116 R600_PIPE_STATE_BLEND
= 0,
117 R600_PIPE_STATE_BLEND_COLOR
,
118 R600_PIPE_STATE_CONFIG
,
119 R600_PIPE_STATE_SEAMLESS_CUBEMAP
,
120 R600_PIPE_STATE_CLIP
,
121 R600_PIPE_STATE_SCISSOR
,
122 R600_PIPE_STATE_VIEWPORT
,
123 R600_PIPE_STATE_RASTERIZER
,
125 R600_PIPE_STATE_FRAMEBUFFER
,
127 R600_PIPE_STATE_STENCIL_REF
,
128 R600_PIPE_STATE_PS_SHADER
,
129 R600_PIPE_STATE_VS_SHADER
,
130 R600_PIPE_STATE_CONSTANT
,
131 R600_PIPE_STATE_SAMPLER
,
132 R600_PIPE_STATE_RESOURCE
,
133 R600_PIPE_STATE_POLYGON_OFFSET
,
134 R600_PIPE_STATE_FETCH_SHADER
,
139 struct compute_memory_pool
;
140 void compute_memory_pool_delete(struct compute_memory_pool
* pool
);
141 struct compute_memory_pool
* compute_memory_pool_new(
142 struct r600_screen
*rscreen
);
144 struct r600_pipe_fences
{
145 struct r600_resource
*bo
;
148 /* linked list of preallocated blocks */
149 struct list_head blocks
;
150 /* linked list of freed fences */
151 struct list_head pool
;
156 struct pipe_screen screen
;
157 struct radeon_winsys
*ws
;
159 enum chip_class chip_class
;
160 struct radeon_info info
;
162 struct r600_tiling_info tiling_info
;
163 struct r600_pipe_fences fences
;
165 /*for compute global memory binding, we allocate stuff here, instead of
167 * XXX: Not sure if this is the best place for global_pool. Also,
168 * it's not thread safe, so it won't work with multiple contexts. */
169 struct compute_memory_pool
*global_pool
;
172 struct r600_pipe_sampler_view
{
173 struct pipe_sampler_view base
;
174 struct r600_resource
*tex_resource
;
175 uint32_t tex_resource_words
[8];
178 struct r600_pipe_rasterizer
{
179 struct r600_pipe_state rstate
;
182 unsigned sprite_coord_enable
;
183 unsigned clip_plane_enable
;
184 unsigned pa_sc_line_stipple
;
185 unsigned pa_cl_clip_cntl
;
189 bool multisample_enable
;
192 struct r600_pipe_blend
{
193 struct r600_pipe_state rstate
;
194 unsigned cb_target_mask
;
195 unsigned cb_color_control
;
200 struct r600_pipe_dsa
{
201 struct r600_pipe_state rstate
;
205 unsigned sx_alpha_test_control
;
208 struct r600_vertex_element
211 struct pipe_vertex_element elements
[PIPE_MAX_ATTRIBS
];
212 struct r600_resource
*fetch_shader
;
214 struct r600_pipe_state rstate
;
217 struct r600_pipe_shader
;
219 struct r600_pipe_shader_selector
{
220 struct r600_pipe_shader
*current
;
222 struct tgsi_token
*tokens
;
223 struct pipe_stream_output_info so
;
225 unsigned num_shaders
;
227 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
230 unsigned nr_ps_max_color_exports
;
233 struct r600_pipe_shader
{
234 struct r600_pipe_shader_selector
*selector
;
235 struct r600_pipe_shader
*next_variant
;
236 struct r600_shader shader
;
237 struct r600_pipe_state rstate
;
238 struct r600_resource
*bo
;
239 struct r600_resource
*bo_fetch
;
240 struct r600_vertex_element vertex_elements
;
241 unsigned sprite_coord_enable
;
243 unsigned pa_cl_vs_out_cntl
;
244 unsigned nr_ps_color_outputs
;
246 unsigned db_shader_control
;
247 unsigned ps_depth_export
;
250 struct r600_pipe_sampler_state
{
251 uint32_t tex_sampler_words
[3];
252 uint32_t border_color
[4];
253 bool border_color_use
;
254 bool seamless_cube_map
;
257 /* needed for blitter save */
258 #define NUM_TEX_UNITS 16
260 struct r600_seamless_cube_map
{
261 struct r600_atom atom
;
265 struct r600_samplerview_state
{
266 struct r600_atom atom
;
267 struct r600_pipe_sampler_view
*views
[NUM_TEX_UNITS
];
268 uint32_t enabled_mask
;
270 uint32_t compressed_depthtex_mask
; /* which textures are depth */
271 uint32_t compressed_colortex_mask
;
274 struct r600_textures_info
{
275 struct r600_samplerview_state views
;
276 struct r600_atom atom_sampler
;
277 struct r600_pipe_sampler_state
*samplers
[NUM_TEX_UNITS
];
279 bool is_array_sampler
[NUM_TEX_UNITS
];
283 struct pipe_reference reference
;
284 unsigned index
; /* in the shared bo */
285 struct r600_resource
*sleep_bo
;
286 struct list_head head
;
289 #define FENCE_BLOCK_SIZE 16
291 struct r600_fence_block
{
292 struct r600_fence fences
[FENCE_BLOCK_SIZE
];
293 struct list_head head
;
296 #define R600_CONSTANT_ARRAY_SIZE 256
297 #define R600_RESOURCE_ARRAY_SIZE 160
299 struct r600_stencil_ref
306 struct r600_constbuf_state
308 struct r600_atom atom
;
309 struct pipe_constant_buffer cb
[PIPE_MAX_CONSTANT_BUFFERS
];
310 uint32_t enabled_mask
;
314 struct r600_vertexbuf_state
316 struct r600_atom atom
;
317 struct pipe_vertex_buffer vb
[PIPE_MAX_ATTRIBS
];
318 uint32_t enabled_mask
; /* non-NULL buffers */
322 struct r600_context
{
323 struct pipe_context context
;
324 struct blitter_context
*blitter
;
325 enum radeon_family family
;
326 enum chip_class chip_class
;
327 boolean has_vertex_cache
;
328 unsigned r6xx_num_clause_temp_gprs
;
329 void *custom_dsa_flush
;
330 void *custom_blend_resolve
;
331 void *custom_blend_decompress
;
333 struct r600_screen
*screen
;
334 struct radeon_winsys
*ws
;
335 struct r600_pipe_state
*states
[R600_PIPE_NSTATES
];
336 struct r600_vertex_element
*vertex_elements
;
337 struct pipe_framebuffer_state framebuffer
;
338 unsigned compressed_cb_mask
;
339 unsigned compute_cb_target_mask
;
340 unsigned db_shader_control
;
341 unsigned pa_sc_line_stipple
;
342 unsigned pa_cl_clip_cntl
;
343 /* for saving when using blitter */
344 struct pipe_stencil_ref stencil_ref
;
345 struct pipe_viewport_state viewport
;
346 struct pipe_clip_state clip
;
347 struct r600_pipe_shader_selector
*ps_shader
;
348 struct r600_pipe_shader_selector
*vs_shader
;
349 struct r600_pipe_rasterizer
*rasterizer
;
350 struct r600_pipe_state vgt
;
351 struct r600_pipe_state spi
;
352 struct pipe_query
*current_render_cond
;
353 unsigned current_render_cond_mode
;
354 struct pipe_query
*saved_render_cond
;
355 unsigned saved_render_cond_mode
;
356 /* shader information */
359 unsigned sprite_coord_enable
;
361 boolean export_16bpc
;
364 bool multisample_enable
;
367 struct u_upload_mgr
*uploader
;
368 struct util_slab_mempool pool_transfers
;
370 unsigned default_ps_gprs
, default_vs_gprs
;
372 /* States based on r600_atom. */
373 struct list_head dirty_states
;
374 struct r600_command_buffer start_cs_cmd
; /* invariant state mostly */
375 /** Compute specific registers initializations. The start_cs_cmd atom
376 * must be emitted before start_compute_cs_cmd. */
377 struct r600_command_buffer start_compute_cs_cmd
;
378 struct r600_surface_sync_cmd surface_sync_cmd
;
379 struct r600_atom r6xx_flush_and_inv_cmd
;
380 struct r600_alphatest_state alphatest_state
;
381 struct r600_cb_misc_state cb_misc_state
;
382 struct r600_db_misc_state db_misc_state
;
383 /** Vertex buffers for fetch shaders */
384 struct r600_vertexbuf_state vertex_buffer_state
;
385 /** Vertex buffers for compute shaders */
386 struct r600_vertexbuf_state cs_vertex_buffer_state
;
387 struct r600_constbuf_state vs_constbuf_state
;
388 struct r600_constbuf_state ps_constbuf_state
;
389 struct r600_textures_info vs_samplers
;
390 struct r600_textures_info ps_samplers
;
391 struct r600_seamless_cube_map seamless_cube_map
;
392 struct r600_cs_shader_state cs_shader_state
;
393 struct r600_sample_mask sample_mask
;
395 /* current external blend state (from state tracker) */
396 struct r600_pipe_blend
*blend
;
397 /* state with disabled blending - used internally with blend_override */
398 struct r600_pipe_blend
*no_blend
;
400 /* 1 - override current blend state with no_blend, 0 - use external state */
401 unsigned blend_override
;
403 struct radeon_winsys_cs
*cs
;
405 struct r600_range
*range
;
407 struct r600_block
**blocks
;
408 struct list_head dirty
;
409 struct list_head enable_list
;
410 unsigned pm4_dirty_cdwords
;
411 unsigned ctx_pm4_ndwords
;
413 /* The list of active queries. Only one query of each type can be active. */
414 int num_occlusion_queries
;
416 /* Manage queries in two separate groups:
417 * The timer ones and the others (streamout, occlusion).
419 * We do this because we should only suspend non-timer queries for u_blitter,
420 * and later if the non-timer queries are suspended, the context flush should
421 * only suspend and resume the timer queries. */
422 struct list_head active_timer_queries
;
423 unsigned num_cs_dw_timer_queries_suspend
;
424 struct list_head active_nontimer_queries
;
425 unsigned num_cs_dw_nontimer_queries_suspend
;
427 unsigned num_cs_dw_streamout_end
;
429 unsigned backend_mask
;
430 unsigned max_db
; /* for OQ */
432 boolean predicate_drawing
;
434 unsigned num_so_targets
;
435 struct r600_so_target
*so_targets
[PIPE_MAX_SO_BUFFERS
];
436 boolean streamout_start
;
437 unsigned streamout_append_bitmask
;
439 /* There is no scissor enable bit on r6xx, so we must use a workaround.
440 * These track the current scissor state. */
442 struct pipe_scissor_state scissor_state
;
444 /* With rasterizer discard, there doesn't have to be a pixel shader.
445 * In that case, we bind this one: */
446 void *dummy_pixel_shader
;
448 boolean dual_src_blend
;
451 struct pipe_index_buffer index_buffer
;
454 static INLINE
void r600_emit_atom(struct r600_context
*rctx
, struct r600_atom
*atom
)
456 atom
->emit(rctx
, atom
);
458 if (atom
->head
.next
&& atom
->head
.prev
)
459 LIST_DELINIT(&atom
->head
);
462 static INLINE
void r600_atom_dirty(struct r600_context
*rctx
, struct r600_atom
*state
)
465 if (state
->flags
& EMIT_EARLY
) {
466 LIST_ADD(&state
->head
, &rctx
->dirty_states
);
468 LIST_ADDTAIL(&state
->head
, &rctx
->dirty_states
);
474 /* evergreen_state.c */
475 void evergreen_init_common_regs(struct r600_command_buffer
*cb
,
476 enum chip_class ctx_chip_class
,
477 enum radeon_family ctx_family
,
480 void evergreen_init_state_functions(struct r600_context
*rctx
);
481 void evergreen_init_atom_start_cs(struct r600_context
*rctx
);
482 void evergreen_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
483 void evergreen_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
484 void evergreen_fetch_shader(struct pipe_context
*ctx
, struct r600_vertex_element
*ve
);
485 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
);
486 void *evergreen_create_resolve_blend(struct r600_context
*rctx
);
487 void *evergreen_create_decompress_blend(struct r600_context
*rctx
);
488 void evergreen_polygon_offset_update(struct r600_context
*rctx
);
489 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
490 enum pipe_format format
,
491 enum pipe_texture_target target
,
492 unsigned sample_count
,
494 void evergreen_init_color_surface(struct r600_context
*rctx
,
495 struct r600_surface
*surf
);
496 void evergreen_update_dual_export_state(struct r600_context
* rctx
);
499 void r600_copy_buffer(struct pipe_context
*ctx
, struct
500 pipe_resource
*dst
, unsigned dstx
,
501 struct pipe_resource
*src
, const struct pipe_box
*src_box
);
502 void r600_init_blit_functions(struct r600_context
*rctx
);
503 void r600_blit_decompress_depth(struct pipe_context
*ctx
,
504 struct r600_texture
*texture
,
505 struct r600_texture
*staging
,
506 unsigned first_level
, unsigned last_level
,
507 unsigned first_layer
, unsigned last_layer
,
508 unsigned first_sample
, unsigned last_sample
);
509 void r600_decompress_depth_textures(struct r600_context
*rctx
,
510 struct r600_samplerview_state
*textures
);
511 void r600_decompress_color_textures(struct r600_context
*rctx
,
512 struct r600_samplerview_state
*textures
);
515 bool r600_init_resource(struct r600_screen
*rscreen
,
516 struct r600_resource
*res
,
517 unsigned size
, unsigned alignment
,
518 unsigned bind
, unsigned usage
);
519 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
520 const struct pipe_resource
*templ
);
523 void r600_flush(struct pipe_context
*ctx
, struct pipe_fence_handle
**fence
,
527 void r600_init_query_functions(struct r600_context
*rctx
);
528 void r600_suspend_nontimer_queries(struct r600_context
*ctx
);
529 void r600_resume_nontimer_queries(struct r600_context
*ctx
);
530 void r600_suspend_timer_queries(struct r600_context
*ctx
);
531 void r600_resume_timer_queries(struct r600_context
*ctx
);
533 /* r600_resource.c */
534 void r600_init_context_resource_functions(struct r600_context
*r600
);
537 int r600_pipe_shader_create(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
539 int r600_compute_shader_create(struct pipe_context
* ctx
,
540 LLVMModuleRef mod
, struct r600_bytecode
* bytecode
);
542 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
545 void r600_set_scissor_state(struct r600_context
*rctx
,
546 const struct pipe_scissor_state
*state
);
547 void r600_init_state_functions(struct r600_context
*rctx
);
548 void r600_init_atom_start_cs(struct r600_context
*rctx
);
549 void r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
550 void r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
551 void r600_fetch_shader(struct pipe_context
*ctx
, struct r600_vertex_element
*ve
);
552 void *r600_create_db_flush_dsa(struct r600_context
*rctx
);
553 void *r600_create_resolve_blend(struct r600_context
*rctx
);
554 void *r600_create_decompress_blend(struct r600_context
*rctx
);
555 void r600_polygon_offset_update(struct r600_context
*rctx
);
556 void r600_adjust_gprs(struct r600_context
*rctx
);
557 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
558 enum pipe_format format
,
559 enum pipe_texture_target target
,
560 unsigned sample_count
,
562 void r600_update_dual_export_state(struct r600_context
* rctx
);
565 void r600_init_screen_texture_functions(struct pipe_screen
*screen
);
566 void r600_init_surface_functions(struct r600_context
*r600
);
567 uint32_t r600_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
568 const unsigned char *swizzle_view
,
569 uint32_t *word4_p
, uint32_t *yuv_format_p
);
570 unsigned r600_texture_get_offset(struct r600_texture
*rtex
,
571 unsigned level
, unsigned layer
);
573 /* r600_translate.c */
574 void r600_translate_index_buffer(struct r600_context
*r600
,
575 struct pipe_index_buffer
*ib
,
578 /* r600_state_common.c */
579 void r600_init_atom(struct r600_atom
*atom
,
580 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
581 unsigned num_dw
, enum r600_atom_flags flags
);
582 void r600_init_common_atoms(struct r600_context
*rctx
);
583 unsigned r600_get_cb_flush_flags(struct r600_context
*rctx
);
584 void r600_texture_barrier(struct pipe_context
*ctx
);
585 void r600_set_index_buffer(struct pipe_context
*ctx
,
586 const struct pipe_index_buffer
*ib
);
587 void r600_vertex_buffers_dirty(struct r600_context
*rctx
);
588 void r600_set_vertex_buffers(struct pipe_context
*ctx
, unsigned count
,
589 const struct pipe_vertex_buffer
*input
);
590 void r600_sampler_views_dirty(struct r600_context
*rctx
,
591 struct r600_samplerview_state
*state
);
592 void r600_set_sampler_views(struct pipe_context
*pipe
,
596 struct pipe_sampler_view
**views
);
597 void r600_bind_vs_samplers(struct pipe_context
*ctx
, unsigned count
, void **states
);
598 void r600_bind_ps_samplers(struct pipe_context
*ctx
, unsigned count
, void **states
);
599 void *r600_create_vertex_elements(struct pipe_context
*ctx
,
601 const struct pipe_vertex_element
*elements
);
602 void r600_delete_vertex_element(struct pipe_context
*ctx
, void *state
);
603 void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
);
604 void r600_set_blend_color(struct pipe_context
*ctx
,
605 const struct pipe_blend_color
*state
);
606 void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
);
607 void r600_set_max_scissor(struct r600_context
*rctx
);
608 void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
);
609 void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
);
610 void r600_sampler_view_destroy(struct pipe_context
*ctx
,
611 struct pipe_sampler_view
*state
);
612 void r600_delete_sampler(struct pipe_context
*ctx
, void *state
);
613 void r600_delete_state(struct pipe_context
*ctx
, void *state
);
614 void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
);
615 void *r600_create_shader_state_ps(struct pipe_context
*ctx
,
616 const struct pipe_shader_state
*state
);
617 void *r600_create_shader_state_vs(struct pipe_context
*ctx
,
618 const struct pipe_shader_state
*state
);
619 void r600_bind_ps_shader(struct pipe_context
*ctx
, void *state
);
620 void r600_bind_vs_shader(struct pipe_context
*ctx
, void *state
);
621 void r600_delete_ps_shader(struct pipe_context
*ctx
, void *state
);
622 void r600_delete_vs_shader(struct pipe_context
*ctx
, void *state
);
623 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
);
624 void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
625 struct pipe_constant_buffer
*cb
);
626 struct pipe_stream_output_target
*
627 r600_create_so_target(struct pipe_context
*ctx
,
628 struct pipe_resource
*buffer
,
629 unsigned buffer_offset
,
630 unsigned buffer_size
);
631 void r600_so_target_destroy(struct pipe_context
*ctx
,
632 struct pipe_stream_output_target
*target
);
633 void r600_set_so_targets(struct pipe_context
*ctx
,
634 unsigned num_targets
,
635 struct pipe_stream_output_target
**targets
,
636 unsigned append_bitmask
);
637 void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
);
638 void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
639 const struct pipe_stencil_ref
*state
);
640 void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
);
641 uint32_t r600_translate_stencil_op(int s_op
);
642 uint32_t r600_translate_fill(uint32_t func
);
643 unsigned r600_tex_wrap(unsigned wrap
);
644 unsigned r600_tex_filter(unsigned filter
);
645 unsigned r600_tex_mipfilter(unsigned filter
);
646 unsigned r600_tex_compare(unsigned compare
);
649 * Helpers for building command buffers
652 #define PKT3_SET_CONFIG_REG 0x68
653 #define PKT3_SET_CONTEXT_REG 0x69
654 #define PKT3_SET_CTL_CONST 0x6F
655 #define PKT3_SET_LOOP_CONST 0x6C
657 #define R600_CONFIG_REG_OFFSET 0x08000
658 #define R600_CONTEXT_REG_OFFSET 0x28000
659 #define R600_CTL_CONST_OFFSET 0x3CFF0
660 #define R600_LOOP_CONST_OFFSET 0X0003E200
661 #define EG_LOOP_CONST_OFFSET 0x0003A200
663 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
664 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
665 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
666 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
667 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
669 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
671 /*Evergreen Compute packet3*/
672 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
674 static INLINE
void r600_store_value(struct r600_command_buffer
*cb
, unsigned value
)
676 cb
->buf
[cb
->atom
.num_dw
++] = value
;
679 static INLINE
void r600_store_config_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
681 assert(reg
< R600_CONTEXT_REG_OFFSET
);
682 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
683 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
684 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
688 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
691 static INLINE
void r600_store_context_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
693 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
694 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
695 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0) | cb
->pkt_flags
;
696 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
700 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
703 static INLINE
void r600_store_ctl_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
705 assert(reg
>= R600_CTL_CONST_OFFSET
);
706 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
707 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0) | cb
->pkt_flags
;
708 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
711 static INLINE
void r600_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
713 assert(reg
>= R600_LOOP_CONST_OFFSET
);
714 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
715 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0);
716 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_LOOP_CONST_OFFSET
) >> 2;
720 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
723 static INLINE
void eg_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
725 assert(reg
>= EG_LOOP_CONST_OFFSET
);
726 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
727 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0) | cb
->pkt_flags
;
728 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- EG_LOOP_CONST_OFFSET
) >> 2;
731 static INLINE
void r600_store_config_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
733 r600_store_config_reg_seq(cb
, reg
, 1);
734 r600_store_value(cb
, value
);
737 static INLINE
void r600_store_context_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
739 r600_store_context_reg_seq(cb
, reg
, 1);
740 r600_store_value(cb
, value
);
743 static INLINE
void r600_store_ctl_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
745 r600_store_ctl_const_seq(cb
, reg
, 1);
746 r600_store_value(cb
, value
);
749 static INLINE
void r600_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
751 r600_store_loop_const_seq(cb
, reg
, 1);
752 r600_store_value(cb
, value
);
755 static INLINE
void eg_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
757 eg_store_loop_const_seq(cb
, reg
, 1);
758 r600_store_value(cb
, value
);
761 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
, enum r600_atom_flags flags
);
762 void r600_release_command_buffer(struct r600_command_buffer
*cb
);
765 * Helpers for emitting state into a command stream directly.
768 static INLINE
unsigned r600_context_bo_reloc(struct r600_context
*ctx
, struct r600_resource
*rbo
,
769 enum radeon_bo_usage usage
)
772 return ctx
->ws
->cs_add_reloc(ctx
->cs
, rbo
->cs_buf
, usage
, rbo
->domains
) * 4;
775 static INLINE
void r600_write_value(struct radeon_winsys_cs
*cs
, unsigned value
)
777 cs
->buf
[cs
->cdw
++] = value
;
780 static INLINE
void r600_write_array(struct radeon_winsys_cs
*cs
, unsigned num
, unsigned *ptr
)
782 assert(cs
->cdw
+num
<= RADEON_MAX_CMDBUF_DWORDS
);
783 memcpy(&cs
->buf
[cs
->cdw
], ptr
, num
* sizeof(ptr
[0]));
787 static INLINE
void r600_write_config_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
789 assert(reg
< R600_CONTEXT_REG_OFFSET
);
790 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
791 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
792 cs
->buf
[cs
->cdw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
795 static INLINE
void r600_write_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
797 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
798 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
799 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0);
800 cs
->buf
[cs
->cdw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
803 static INLINE
void r600_write_compute_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
805 r600_write_context_reg_seq(cs
, reg
, num
);
806 /* Set the compute bit on the packet header */
807 cs
->buf
[cs
->cdw
- 2] |= RADEON_CP_PACKET3_COMPUTE_MODE
;
810 static INLINE
void r600_write_ctl_const_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
812 assert(reg
>= R600_CTL_CONST_OFFSET
);
813 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
814 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0);
815 cs
->buf
[cs
->cdw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
818 static INLINE
void r600_write_config_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
820 r600_write_config_reg_seq(cs
, reg
, 1);
821 r600_write_value(cs
, value
);
824 static INLINE
void r600_write_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
826 r600_write_context_reg_seq(cs
, reg
, 1);
827 r600_write_value(cs
, value
);
830 static INLINE
void r600_write_compute_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
832 r600_write_compute_context_reg_seq(cs
, reg
, 1);
833 r600_write_value(cs
, value
);
836 static INLINE
void r600_write_ctl_const(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
838 r600_write_ctl_const_seq(cs
, reg
, 1);
839 r600_write_value(cs
, value
);
845 static INLINE
uint32_t S_FIXED(float value
, uint32_t frac_bits
)
847 return value
* (1 << frac_bits
);
849 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
851 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
853 if (filter
<= 1) return 0;
854 if (filter
<= 2) return 1;
855 if (filter
<= 4) return 2;
856 if (filter
<= 8) return 3;
860 /* 12.4 fixed-point */
861 static INLINE
unsigned r600_pack_float_12p4(float x
)
864 x
>= 4096 ? 0xffff : x
* 16;
867 static INLINE
uint64_t r600_resource_va(struct pipe_screen
*screen
, struct pipe_resource
*resource
)
869 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
870 struct r600_resource
*rresource
= (struct r600_resource
*)resource
;
872 return rscreen
->ws
->buffer_get_virtual_address(rresource
->cs_buf
);