2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "util/u_slab.h"
31 #include "r600_llvm.h"
32 #include "r600_public.h"
33 #include "r600_shader.h"
34 #include "r600_resource.h"
35 #include "evergreen_compute.h"
37 #define R600_MAX_CONST_BUFFERS 2
38 #define R600_MAX_CONST_BUFFER_SIZE 4096
40 #ifdef PIPE_ARCH_BIG_ENDIAN
41 #define R600_BIG_ENDIAN 1
43 #define R600_BIG_ENDIAN 0
46 enum r600_atom_flags
{
47 /* When set, atoms are added at the beginning of the dirty list
48 * instead of the end. */
52 /* This encapsulates a state or an operation which can emitted into the GPU
53 * command stream. It's not limited to states only, it can be used for anything
54 * that wants to write commands into the CS (e.g. cache flushes). */
56 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
);
59 enum r600_atom_flags flags
;
62 struct list_head head
;
65 /* This is an atom containing GPU commands that never change.
66 * This is supposed to be copied directly into the CS. */
67 struct r600_command_buffer
{
68 struct r600_atom atom
;
74 struct r600_surface_sync_cmd
{
75 struct r600_atom atom
;
76 unsigned flush_flags
; /* CP_COHER_CNTL */
79 struct r600_db_misc_state
{
80 struct r600_atom atom
;
81 bool occlusion_query_enabled
;
82 bool flush_depthstencil_through_cb
;
85 struct r600_cb_misc_state
{
86 struct r600_atom atom
;
87 unsigned cb_color_control
; /* this comes from blend state */
88 unsigned blend_colormask
; /* 8*4 bits for 8 RGBA colorbuffers */
90 unsigned nr_ps_color_outputs
;
95 enum r600_pipe_state_id
{
96 R600_PIPE_STATE_BLEND
= 0,
97 R600_PIPE_STATE_BLEND_COLOR
,
98 R600_PIPE_STATE_CONFIG
,
99 R600_PIPE_STATE_SEAMLESS_CUBEMAP
,
100 R600_PIPE_STATE_CLIP
,
101 R600_PIPE_STATE_SCISSOR
,
102 R600_PIPE_STATE_VIEWPORT
,
103 R600_PIPE_STATE_RASTERIZER
,
105 R600_PIPE_STATE_FRAMEBUFFER
,
107 R600_PIPE_STATE_STENCIL_REF
,
108 R600_PIPE_STATE_PS_SHADER
,
109 R600_PIPE_STATE_VS_SHADER
,
110 R600_PIPE_STATE_CONSTANT
,
111 R600_PIPE_STATE_SAMPLER
,
112 R600_PIPE_STATE_RESOURCE
,
113 R600_PIPE_STATE_POLYGON_OFFSET
,
114 R600_PIPE_STATE_FETCH_SHADER
,
119 struct compute_memory_pool
;
120 void compute_memory_pool_delete(struct compute_memory_pool
* pool
);
121 struct compute_memory_pool
* compute_memory_pool_new(
122 struct r600_screen
*rscreen
);
124 struct r600_pipe_fences
{
125 struct r600_resource
*bo
;
128 /* linked list of preallocated blocks */
129 struct list_head blocks
;
130 /* linked list of freed fences */
131 struct list_head pool
;
136 struct pipe_screen screen
;
137 struct radeon_winsys
*ws
;
139 enum chip_class chip_class
;
140 struct radeon_info info
;
142 struct r600_tiling_info tiling_info
;
143 struct r600_pipe_fences fences
;
145 bool use_surface_alloc
;
147 /*for compute global memory binding, we allocate stuff here, instead of
149 * XXX: Not sure if this is the best place for global_pool. Also,
150 * it's not thread safe, so it won't work with multiple contexts. */
151 struct compute_memory_pool
*global_pool
;
154 struct r600_pipe_sampler_view
{
155 struct pipe_sampler_view base
;
156 struct r600_pipe_resource_state state
;
159 struct r600_pipe_rasterizer
{
160 struct r600_pipe_state rstate
;
163 unsigned sprite_coord_enable
;
164 unsigned clip_plane_enable
;
165 unsigned pa_sc_line_stipple
;
166 unsigned pa_cl_clip_cntl
;
172 struct r600_pipe_blend
{
173 struct r600_pipe_state rstate
;
174 unsigned cb_target_mask
;
175 unsigned cb_color_control
;
179 struct r600_pipe_dsa
{
180 struct r600_pipe_state rstate
;
184 unsigned sx_alpha_test_control
;
187 struct r600_vertex_element
190 struct pipe_vertex_element elements
[PIPE_MAX_ATTRIBS
];
191 struct r600_resource
*fetch_shader
;
193 struct r600_pipe_state rstate
;
196 struct r600_pipe_shader
;
198 struct r600_pipe_shader_selector
{
199 struct r600_pipe_shader
*current
;
201 struct tgsi_token
*tokens
;
202 struct pipe_stream_output_info so
;
204 unsigned num_shaders
;
206 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
209 unsigned nr_ps_max_color_exports
;
212 struct r600_pipe_shader
{
213 struct r600_pipe_shader_selector
*selector
;
214 struct r600_pipe_shader
*next_variant
;
215 struct r600_shader shader
;
216 struct r600_pipe_state rstate
;
217 struct r600_resource
*bo
;
218 struct r600_resource
*bo_fetch
;
219 struct r600_vertex_element vertex_elements
;
220 unsigned sprite_coord_enable
;
222 unsigned pa_cl_vs_out_cntl
;
223 unsigned nr_ps_color_outputs
;
225 unsigned db_shader_control
;
226 unsigned ps_depth_export
;
229 struct r600_pipe_sampler_state
{
230 struct r600_pipe_state rstate
;
231 boolean seamless_cube_map
;
234 /* needed for blitter save */
235 #define NUM_TEX_UNITS 16
237 struct r600_textures_info
{
238 struct r600_pipe_sampler_view
*views
[NUM_TEX_UNITS
];
239 struct r600_pipe_sampler_state
*samplers
[NUM_TEX_UNITS
];
241 uint32_t depth_texture_mask
; /* which textures are depth */
244 bool is_array_sampler
[NUM_TEX_UNITS
];
248 struct pipe_reference reference
;
249 unsigned index
; /* in the shared bo */
250 struct r600_resource
*sleep_bo
;
251 struct list_head head
;
254 #define FENCE_BLOCK_SIZE 16
256 struct r600_fence_block
{
257 struct r600_fence fences
[FENCE_BLOCK_SIZE
];
258 struct list_head head
;
261 #define R600_CONSTANT_ARRAY_SIZE 256
262 #define R600_RESOURCE_ARRAY_SIZE 160
264 struct r600_stencil_ref
271 struct r600_constbuf_state
273 struct r600_atom atom
;
274 struct pipe_constant_buffer cb
[PIPE_MAX_CONSTANT_BUFFERS
];
275 uint32_t enabled_mask
;
279 struct r600_vertexbuf_state
281 struct r600_atom atom
;
282 struct pipe_vertex_buffer vb
[PIPE_MAX_ATTRIBS
];
283 uint32_t enabled_mask
; /* non-NULL buffers */
287 struct r600_context
{
288 struct pipe_context context
;
289 struct blitter_context
*blitter
;
290 enum radeon_family family
;
291 enum chip_class chip_class
;
292 boolean has_vertex_cache
;
293 unsigned r6xx_num_clause_temp_gprs
;
294 void *custom_dsa_flush
;
295 struct r600_screen
*screen
;
296 struct radeon_winsys
*ws
;
297 struct r600_pipe_state
*states
[R600_PIPE_NSTATES
];
298 struct r600_vertex_element
*vertex_elements
;
299 struct pipe_framebuffer_state framebuffer
;
300 unsigned compute_cb_target_mask
;
301 unsigned sx_alpha_test_control
;
302 unsigned db_shader_control
;
303 unsigned pa_sc_line_stipple
;
304 unsigned pa_cl_clip_cntl
;
305 /* for saving when using blitter */
306 struct pipe_stencil_ref stencil_ref
;
307 struct pipe_viewport_state viewport
;
308 struct pipe_clip_state clip
;
309 struct r600_pipe_shader_selector
*ps_shader
;
310 struct r600_pipe_shader_selector
*vs_shader
;
311 struct r600_pipe_compute
*cs_shader
;
312 struct r600_pipe_rasterizer
*rasterizer
;
313 struct r600_pipe_state vgt
;
314 struct r600_pipe_state spi
;
315 struct pipe_query
*current_render_cond
;
316 unsigned current_render_cond_mode
;
317 struct pipe_query
*saved_render_cond
;
318 unsigned saved_render_cond_mode
;
319 /* shader information */
322 unsigned sprite_coord_enable
;
324 boolean export_16bpc
;
326 boolean alpha_ref_dirty
;
328 struct r600_textures_info vs_samplers
;
329 struct r600_textures_info ps_samplers
;
331 struct u_upload_mgr
*uploader
;
332 struct util_slab_mempool pool_transfers
;
334 unsigned default_ps_gprs
, default_vs_gprs
;
336 /* States based on r600_atom. */
337 struct list_head dirty_states
;
338 struct r600_command_buffer start_cs_cmd
; /* invariant state mostly */
339 /** Compute specific registers initializations. The start_cs_cmd atom
340 * must be emitted before start_compute_cs_cmd. */
341 struct r600_command_buffer start_compute_cs_cmd
;
342 struct r600_surface_sync_cmd surface_sync_cmd
;
343 struct r600_atom r6xx_flush_and_inv_cmd
;
344 struct r600_cb_misc_state cb_misc_state
;
345 struct r600_db_misc_state db_misc_state
;
346 /** Vertex buffers for fetch shaders */
347 struct r600_vertexbuf_state vertex_buffer_state
;
348 /** Vertex buffers for compute shaders */
349 struct r600_vertexbuf_state cs_vertex_buffer_state
;
350 struct r600_constbuf_state vs_constbuf_state
;
351 struct r600_constbuf_state ps_constbuf_state
;
353 struct radeon_winsys_cs
*cs
;
355 struct r600_range
*range
;
357 struct r600_block
**blocks
;
358 struct list_head dirty
;
359 struct list_head resource_dirty
;
360 struct list_head enable_list
;
361 unsigned pm4_dirty_cdwords
;
362 unsigned ctx_pm4_ndwords
;
364 /* The list of active queries. Only one query of each type can be active. */
365 int num_occlusion_queries
;
367 /* Manage queries in two separate groups:
368 * The timer ones and the others (streamout, occlusion).
370 * We do this because we should only suspend non-timer queries for u_blitter,
371 * and later if the non-timer queries are suspended, the context flush should
372 * only suspend and resume the timer queries. */
373 struct list_head active_timer_queries
;
374 unsigned num_cs_dw_timer_queries_suspend
;
375 struct list_head active_nontimer_queries
;
376 unsigned num_cs_dw_nontimer_queries_suspend
;
378 unsigned num_cs_dw_streamout_end
;
380 unsigned backend_mask
;
381 unsigned max_db
; /* for OQ */
383 boolean predicate_drawing
;
384 struct r600_range ps_resources
;
385 struct r600_range vs_resources
;
386 int num_ps_resources
, num_vs_resources
;
388 unsigned num_so_targets
;
389 struct r600_so_target
*so_targets
[PIPE_MAX_SO_BUFFERS
];
390 boolean streamout_start
;
391 unsigned streamout_append_bitmask
;
393 /* There is no scissor enable bit on r6xx, so we must use a workaround.
394 * These track the current scissor state. */
396 struct pipe_scissor_state scissor_state
;
398 /* With rasterizer discard, there doesn't have to be a pixel shader.
399 * In that case, we bind this one: */
400 void *dummy_pixel_shader
;
402 boolean dual_src_blend
;
405 struct pipe_index_buffer index_buffer
;
408 static INLINE
void r600_emit_atom(struct r600_context
*rctx
, struct r600_atom
*atom
)
410 atom
->emit(rctx
, atom
);
412 if (atom
->head
.next
&& atom
->head
.prev
)
413 LIST_DELINIT(&atom
->head
);
416 static INLINE
void r600_atom_dirty(struct r600_context
*rctx
, struct r600_atom
*state
)
419 if (state
->flags
& EMIT_EARLY
) {
420 LIST_ADD(&state
->head
, &rctx
->dirty_states
);
422 LIST_ADDTAIL(&state
->head
, &rctx
->dirty_states
);
428 /* evergreen_state.c */
429 void evergreen_init_state_functions(struct r600_context
*rctx
);
430 void evergreen_init_atom_start_cs(struct r600_context
*rctx
);
431 void evergreen_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
432 void evergreen_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
433 void evergreen_fetch_shader(struct pipe_context
*ctx
, struct r600_vertex_element
*ve
);
434 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
);
435 void evergreen_polygon_offset_update(struct r600_context
*rctx
);
436 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
437 enum pipe_format format
,
438 enum pipe_texture_target target
,
439 unsigned sample_count
,
441 void evergreen_cb(struct r600_context
*rctx
, struct r600_pipe_state
*rstate
,
442 const struct pipe_framebuffer_state
*state
, int cb
);
445 void evergreen_update_dual_export_state(struct r600_context
* rctx
);
448 void r600_init_blit_functions(struct r600_context
*rctx
);
449 void r600_blit_uncompress_depth(struct pipe_context
*ctx
,
450 struct r600_resource_texture
*texture
,
451 struct r600_resource_texture
*staging
,
452 unsigned first_level
, unsigned last_level
,
453 unsigned first_layer
, unsigned last_layer
);
454 void r600_flush_depth_textures(struct r600_context
*rctx
,
455 struct r600_textures_info
*textures
);
457 bool r600_init_resource(struct r600_screen
*rscreen
,
458 struct r600_resource
*res
,
459 unsigned size
, unsigned alignment
,
460 unsigned bind
, unsigned usage
);
461 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
462 const struct pipe_resource
*templ
);
465 void r600_flush(struct pipe_context
*ctx
, struct pipe_fence_handle
**fence
,
469 void r600_init_query_functions(struct r600_context
*rctx
);
470 void r600_suspend_nontimer_queries(struct r600_context
*ctx
);
471 void r600_resume_nontimer_queries(struct r600_context
*ctx
);
472 void r600_suspend_timer_queries(struct r600_context
*ctx
);
473 void r600_resume_timer_queries(struct r600_context
*ctx
);
475 /* r600_resource.c */
476 void r600_init_context_resource_functions(struct r600_context
*r600
);
479 int r600_pipe_shader_create(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
481 int r600_compute_shader_create(struct pipe_context
* ctx
,
482 LLVMModuleRef mod
, struct r600_bytecode
* bytecode
);
484 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
487 void r600_set_scissor_state(struct r600_context
*rctx
,
488 const struct pipe_scissor_state
*state
);
489 void r600_update_sampler_states(struct r600_context
*rctx
);
490 void r600_init_state_functions(struct r600_context
*rctx
);
491 void r600_init_atom_start_cs(struct r600_context
*rctx
);
492 void r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
493 void r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
494 void r600_fetch_shader(struct pipe_context
*ctx
, struct r600_vertex_element
*ve
);
495 void *r600_create_db_flush_dsa(struct r600_context
*rctx
);
496 void r600_polygon_offset_update(struct r600_context
*rctx
);
497 void r600_adjust_gprs(struct r600_context
*rctx
);
498 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
499 enum pipe_format format
,
500 enum pipe_texture_target target
,
501 unsigned sample_count
,
503 void r600_update_dual_export_state(struct r600_context
* rctx
);
506 void r600_init_screen_texture_functions(struct pipe_screen
*screen
);
507 void r600_init_surface_functions(struct r600_context
*r600
);
508 uint32_t r600_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
509 const unsigned char *swizzle_view
,
510 uint32_t *word4_p
, uint32_t *yuv_format_p
);
511 unsigned r600_texture_get_offset(struct r600_resource_texture
*rtex
,
512 unsigned level
, unsigned layer
);
514 /* r600_translate.c */
515 void r600_translate_index_buffer(struct r600_context
*r600
,
516 struct pipe_index_buffer
*ib
,
519 /* r600_state_common.c */
520 void r600_init_atom(struct r600_atom
*atom
,
521 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
522 unsigned num_dw
, enum r600_atom_flags flags
);
523 void r600_init_common_atoms(struct r600_context
*rctx
);
524 unsigned r600_get_cb_flush_flags(struct r600_context
*rctx
);
525 void r600_texture_barrier(struct pipe_context
*ctx
);
526 void r600_set_index_buffer(struct pipe_context
*ctx
,
527 const struct pipe_index_buffer
*ib
);
528 void r600_vertex_buffers_dirty(struct r600_context
*rctx
);
529 void r600_set_vertex_buffers(struct pipe_context
*ctx
, unsigned count
,
530 const struct pipe_vertex_buffer
*input
);
531 void r600_set_sampler_views(struct r600_context
*rctx
,
532 struct r600_textures_info
*dst
,
534 struct pipe_sampler_view
**views
,
535 void (*set_resource
)(struct r600_context
*, struct r600_pipe_resource_state
*, unsigned));
536 void *r600_create_vertex_elements(struct pipe_context
*ctx
,
538 const struct pipe_vertex_element
*elements
);
539 void r600_delete_vertex_element(struct pipe_context
*ctx
, void *state
);
540 void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
);
541 void r600_set_blend_color(struct pipe_context
*ctx
,
542 const struct pipe_blend_color
*state
);
543 void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
);
544 void r600_set_max_scissor(struct r600_context
*rctx
);
545 void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
);
546 void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
);
547 void r600_sampler_view_destroy(struct pipe_context
*ctx
,
548 struct pipe_sampler_view
*state
);
549 void r600_delete_state(struct pipe_context
*ctx
, void *state
);
550 void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
);
551 void *r600_create_shader_state_ps(struct pipe_context
*ctx
,
552 const struct pipe_shader_state
*state
);
553 void *r600_create_shader_state_vs(struct pipe_context
*ctx
,
554 const struct pipe_shader_state
*state
);
555 void r600_bind_ps_shader(struct pipe_context
*ctx
, void *state
);
556 void r600_bind_vs_shader(struct pipe_context
*ctx
, void *state
);
557 void r600_delete_ps_shader(struct pipe_context
*ctx
, void *state
);
558 void r600_delete_vs_shader(struct pipe_context
*ctx
, void *state
);
559 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
);
560 void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
561 struct pipe_constant_buffer
*cb
);
562 struct pipe_stream_output_target
*
563 r600_create_so_target(struct pipe_context
*ctx
,
564 struct pipe_resource
*buffer
,
565 unsigned buffer_offset
,
566 unsigned buffer_size
);
567 void r600_so_target_destroy(struct pipe_context
*ctx
,
568 struct pipe_stream_output_target
*target
);
569 void r600_set_so_targets(struct pipe_context
*ctx
,
570 unsigned num_targets
,
571 struct pipe_stream_output_target
**targets
,
572 unsigned append_bitmask
);
573 void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
574 const struct pipe_stencil_ref
*state
);
575 void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
);
576 uint32_t r600_translate_stencil_op(int s_op
);
577 uint32_t r600_translate_fill(uint32_t func
);
578 unsigned r600_tex_wrap(unsigned wrap
);
579 unsigned r600_tex_filter(unsigned filter
);
580 unsigned r600_tex_mipfilter(unsigned filter
);
581 unsigned r600_tex_compare(unsigned compare
);
584 * Helpers for building command buffers
587 #define PKT3_SET_CONFIG_REG 0x68
588 #define PKT3_SET_CONTEXT_REG 0x69
589 #define PKT3_SET_CTL_CONST 0x6F
590 #define PKT3_SET_LOOP_CONST 0x6C
592 #define R600_CONFIG_REG_OFFSET 0x08000
593 #define R600_CONTEXT_REG_OFFSET 0x28000
594 #define R600_CTL_CONST_OFFSET 0x3CFF0
595 #define R600_LOOP_CONST_OFFSET 0X0003E200
596 #define EG_LOOP_CONST_OFFSET 0x0003A200
598 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
599 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
600 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
601 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
602 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
604 static INLINE
void r600_store_value(struct r600_command_buffer
*cb
, unsigned value
)
606 cb
->buf
[cb
->atom
.num_dw
++] = value
;
609 static INLINE
void r600_store_config_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
611 assert(reg
< R600_CONTEXT_REG_OFFSET
);
612 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
613 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
614 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
618 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
621 static INLINE
void r600_store_context_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
623 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
624 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
625 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0) | cb
->pkt_flags
;
626 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
630 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
633 static INLINE
void r600_store_ctl_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
635 assert(reg
>= R600_CTL_CONST_OFFSET
);
636 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
637 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0) | cb
->pkt_flags
;
638 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
641 static INLINE
void r600_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
643 assert(reg
>= R600_LOOP_CONST_OFFSET
);
644 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
645 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0);
646 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_LOOP_CONST_OFFSET
) >> 2;
650 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
653 static INLINE
void eg_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
655 assert(reg
>= EG_LOOP_CONST_OFFSET
);
656 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
657 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0) | cb
->pkt_flags
;
658 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- EG_LOOP_CONST_OFFSET
) >> 2;
661 static INLINE
void r600_store_config_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
663 r600_store_config_reg_seq(cb
, reg
, 1);
664 r600_store_value(cb
, value
);
667 static INLINE
void r600_store_context_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
669 r600_store_context_reg_seq(cb
, reg
, 1);
670 r600_store_value(cb
, value
);
673 static INLINE
void r600_store_ctl_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
675 r600_store_ctl_const_seq(cb
, reg
, 1);
676 r600_store_value(cb
, value
);
679 static INLINE
void r600_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
681 r600_store_loop_const_seq(cb
, reg
, 1);
682 r600_store_value(cb
, value
);
685 static INLINE
void eg_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
687 eg_store_loop_const_seq(cb
, reg
, 1);
688 r600_store_value(cb
, value
);
691 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
, enum r600_atom_flags flags
);
692 void r600_release_command_buffer(struct r600_command_buffer
*cb
);
695 * Helpers for emitting state into a command stream directly.
698 static INLINE
unsigned r600_context_bo_reloc(struct r600_context
*ctx
, struct r600_resource
*rbo
,
699 enum radeon_bo_usage usage
)
702 return ctx
->ws
->cs_add_reloc(ctx
->cs
, rbo
->cs_buf
, usage
, rbo
->domains
) * 4;
705 static INLINE
void r600_write_value(struct radeon_winsys_cs
*cs
, unsigned value
)
707 cs
->buf
[cs
->cdw
++] = value
;
710 static INLINE
void r600_write_config_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
712 assert(reg
< R600_CONTEXT_REG_OFFSET
);
713 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
714 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
715 cs
->buf
[cs
->cdw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
718 static INLINE
void r600_write_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
720 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
721 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
722 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0);
723 cs
->buf
[cs
->cdw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
726 static INLINE
void r600_write_ctl_const_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
728 assert(reg
>= R600_CTL_CONST_OFFSET
);
729 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
730 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0);
731 cs
->buf
[cs
->cdw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
734 static INLINE
void r600_write_config_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
736 r600_write_config_reg_seq(cs
, reg
, 1);
737 r600_write_value(cs
, value
);
740 static INLINE
void r600_write_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
742 r600_write_context_reg_seq(cs
, reg
, 1);
743 r600_write_value(cs
, value
);
746 static INLINE
void r600_write_ctl_const(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
748 r600_write_ctl_const_seq(cs
, reg
, 1);
749 r600_write_value(cs
, value
);
755 static INLINE
uint32_t S_FIXED(float value
, uint32_t frac_bits
)
757 return value
* (1 << frac_bits
);
759 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
761 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
763 if (filter
<= 1) return 0;
764 if (filter
<= 2) return 1;
765 if (filter
<= 4) return 2;
766 if (filter
<= 8) return 3;
770 /* 12.4 fixed-point */
771 static INLINE
unsigned r600_pack_float_12p4(float x
)
774 x
>= 4096 ? 0xffff : x
* 16;
777 static INLINE
uint64_t r600_resource_va(struct pipe_screen
*screen
, struct pipe_resource
*resource
)
779 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
780 struct r600_resource
*rresource
= (struct r600_resource
*)resource
;
782 return rscreen
->ws
->buffer_get_virtual_address(rresource
->cs_buf
);