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r600: fork and import gallium/radeon
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "r600_pipe_common.h"
30 #include "r600_cs.h"
31 #include "r600_public.h"
32 #include "pipe/p_defines.h"
33
34 #include "util/u_suballoc.h"
35 #include "util/list.h"
36 #include "util/u_transfer.h"
37 #include "util/u_memory.h"
38
39 #include "tgsi/tgsi_scan.h"
40
41 #define R600_NUM_ATOMS 52
42
43 /* read caches */
44 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
45 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
46 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
47 /* read-write caches */
48 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
49 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
50 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
51 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
52 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
53 /* engine synchronization */
54 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
55 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
56 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
57
58 /* the number of CS dwords for flushing and drawing */
59 #define R600_MAX_FLUSH_CS_DWORDS 18
60 #define R600_MAX_DRAW_CS_DWORDS 58
61 #define R600_MAX_PFP_SYNC_ME_DWORDS 16
62
63 #define R600_MAX_USER_CONST_BUFFERS 13
64 #define R600_MAX_DRIVER_CONST_BUFFERS 3
65 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
66
67 /* start driver buffers after user buffers */
68 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
69 #define R600_UCP_SIZE (4*4*8)
70 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
71
72 #define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
73 /*
74 * Note GS doesn't use a constant buffer binding, just a resource index,
75 * so it's fine to have it exist at index 16.
76 */
77 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
78 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
79 * of 16 const buffers.
80 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
81 *
82 * In order to support d3d 11 mandated minimum of 15 user const buffers
83 * we'd have to squash all use cases into one driver buffer.
84 */
85 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
86
87 /* HW stages */
88 #define R600_HW_STAGE_PS 0
89 #define R600_HW_STAGE_VS 1
90 #define R600_HW_STAGE_GS 2
91 #define R600_HW_STAGE_ES 3
92 #define EG_HW_STAGE_LS 4
93 #define EG_HW_STAGE_HS 5
94
95 #define R600_NUM_HW_STAGES 4
96 #define EG_NUM_HW_STAGES 6
97
98 struct r600_context;
99 struct r600_bytecode;
100 union r600_shader_key;
101
102 /* This is an atom containing GPU commands that never change.
103 * This is supposed to be copied directly into the CS. */
104 struct r600_command_buffer {
105 uint32_t *buf;
106 unsigned num_dw;
107 unsigned max_num_dw;
108 unsigned pkt_flags;
109 };
110
111 struct r600_db_state {
112 struct r600_atom atom;
113 struct r600_surface *rsurf;
114 };
115
116 struct r600_db_misc_state {
117 struct r600_atom atom;
118 bool occlusion_queries_disabled;
119 bool flush_depthstencil_through_cb;
120 bool flush_depth_inplace;
121 bool flush_stencil_inplace;
122 bool copy_depth, copy_stencil;
123 unsigned copy_sample;
124 unsigned log_samples;
125 unsigned db_shader_control;
126 bool htile_clear;
127 uint8_t ps_conservative_z;
128 };
129
130 struct r600_cb_misc_state {
131 struct r600_atom atom;
132 unsigned cb_color_control; /* this comes from blend state */
133 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
134 unsigned nr_cbufs;
135 unsigned nr_ps_color_outputs;
136 bool multiwrite;
137 bool dual_src_blend;
138 };
139
140 struct r600_clip_misc_state {
141 struct r600_atom atom;
142 unsigned pa_cl_clip_cntl; /* from rasterizer */
143 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
144 unsigned clip_plane_enable; /* from rasterizer */
145 unsigned clip_dist_write; /* from vertex shader */
146 boolean clip_disable; /* from vertex shader */
147 boolean vs_out_viewport; /* from vertex shader */
148 };
149
150 struct r600_alphatest_state {
151 struct r600_atom atom;
152 unsigned sx_alpha_test_control; /* this comes from dsa state */
153 unsigned sx_alpha_ref; /* this comes from dsa state */
154 bool bypass;
155 bool cb0_export_16bpc; /* from set_framebuffer_state */
156 };
157
158 struct r600_vgt_state {
159 struct r600_atom atom;
160 uint32_t vgt_multi_prim_ib_reset_en;
161 uint32_t vgt_multi_prim_ib_reset_indx;
162 uint32_t vgt_indx_offset;
163 bool last_draw_was_indirect;
164 };
165
166 struct r600_blend_color {
167 struct r600_atom atom;
168 struct pipe_blend_color state;
169 };
170
171 struct r600_clip_state {
172 struct r600_atom atom;
173 struct pipe_clip_state state;
174 };
175
176 struct r600_cs_shader_state {
177 struct r600_atom atom;
178 unsigned kernel_index;
179 unsigned pc;
180 struct r600_pipe_compute *shader;
181 };
182
183 struct r600_framebuffer {
184 struct r600_atom atom;
185 struct pipe_framebuffer_state state;
186 unsigned compressed_cb_mask;
187 unsigned nr_samples;
188 bool export_16bpc;
189 bool cb0_is_integer;
190 bool is_msaa_resolve;
191 bool dual_src_blend;
192 bool do_update_surf_dirtiness;
193 };
194
195 struct r600_sample_mask {
196 struct r600_atom atom;
197 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
198 };
199
200 struct r600_config_state {
201 struct r600_atom atom;
202 unsigned sq_gpr_resource_mgmt_1;
203 unsigned sq_gpr_resource_mgmt_2;
204 unsigned sq_gpr_resource_mgmt_3;
205 bool dyn_gpr_enabled;
206 };
207
208 struct r600_stencil_ref
209 {
210 ubyte ref_value[2];
211 ubyte valuemask[2];
212 ubyte writemask[2];
213 };
214
215 struct r600_stencil_ref_state {
216 struct r600_atom atom;
217 struct r600_stencil_ref state;
218 struct pipe_stencil_ref pipe_state;
219 };
220
221 struct r600_shader_stages_state {
222 struct r600_atom atom;
223 unsigned geom_enable;
224 };
225
226 struct r600_gs_rings_state {
227 struct r600_atom atom;
228 unsigned enable;
229 struct pipe_constant_buffer esgs_ring;
230 struct pipe_constant_buffer gsvs_ring;
231 };
232
233 /* This must start from 16. */
234 /* features */
235 #define DBG_NO_CP_DMA (1 << 30)
236 /* shader backend */
237 #define DBG_NO_SB (1 << 21)
238 #define DBG_SB_CS (1 << 22)
239 #define DBG_SB_DRY_RUN (1 << 23)
240 #define DBG_SB_STAT (1 << 24)
241 #define DBG_SB_DUMP (1 << 25)
242 #define DBG_SB_NO_FALLBACK (1 << 26)
243 #define DBG_SB_DISASM (1 << 27)
244 #define DBG_SB_SAFEMATH (1 << 28)
245
246 struct r600_screen {
247 struct r600_common_screen b;
248 bool has_msaa;
249 bool has_compressed_msaa_texturing;
250
251 /*for compute global memory binding, we allocate stuff here, instead of
252 * buffers.
253 * XXX: Not sure if this is the best place for global_pool. Also,
254 * it's not thread safe, so it won't work with multiple contexts. */
255 struct compute_memory_pool *global_pool;
256 };
257
258 struct r600_pipe_sampler_view {
259 struct pipe_sampler_view base;
260 struct list_head list;
261 struct r600_resource *tex_resource;
262 uint32_t tex_resource_words[8];
263 bool skip_mip_address_reloc;
264 bool is_stencil_sampler;
265 };
266
267 struct r600_rasterizer_state {
268 struct r600_command_buffer buffer;
269 boolean flatshade;
270 boolean two_side;
271 unsigned sprite_coord_enable;
272 unsigned clip_plane_enable;
273 unsigned pa_sc_line_stipple;
274 unsigned pa_cl_clip_cntl;
275 unsigned pa_su_sc_mode_cntl;
276 float offset_units;
277 float offset_scale;
278 bool offset_enable;
279 bool offset_units_unscaled;
280 bool scissor_enable;
281 bool multisample_enable;
282 bool clip_halfz;
283 bool rasterizer_discard;
284 };
285
286 struct r600_poly_offset_state {
287 struct r600_atom atom;
288 enum pipe_format zs_format;
289 float offset_units;
290 float offset_scale;
291 bool offset_units_unscaled;
292 };
293
294 struct r600_blend_state {
295 struct r600_command_buffer buffer;
296 struct r600_command_buffer buffer_no_blend;
297 unsigned cb_target_mask;
298 unsigned cb_color_control;
299 unsigned cb_color_control_no_blend;
300 bool dual_src_blend;
301 bool alpha_to_one;
302 };
303
304 struct r600_dsa_state {
305 struct r600_command_buffer buffer;
306 unsigned alpha_ref;
307 ubyte valuemask[2];
308 ubyte writemask[2];
309 unsigned zwritemask;
310 unsigned sx_alpha_test_control;
311 };
312
313 struct r600_pipe_shader;
314
315 struct r600_pipe_shader_selector {
316 struct r600_pipe_shader *current;
317
318 struct tgsi_token *tokens;
319 struct pipe_stream_output_info so;
320 struct tgsi_shader_info info;
321
322 unsigned num_shaders;
323
324 enum pipe_shader_type type;
325
326 /* geometry shader properties */
327 enum pipe_prim_type gs_output_prim;
328 unsigned gs_max_out_vertices;
329 unsigned gs_num_invocations;
330
331 /* TCS/VS */
332 uint64_t lds_patch_outputs_written_mask;
333 uint64_t lds_outputs_written_mask;
334 unsigned nr_ps_max_color_exports;
335 };
336
337 struct r600_pipe_sampler_state {
338 uint32_t tex_sampler_words[3];
339 union pipe_color_union border_color;
340 bool border_color_use;
341 bool seamless_cube_map;
342 };
343
344 /* needed for blitter save */
345 #define NUM_TEX_UNITS 16
346
347 struct r600_seamless_cube_map {
348 struct r600_atom atom;
349 bool enabled;
350 };
351
352 struct r600_samplerview_state {
353 struct r600_atom atom;
354 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
355 uint32_t enabled_mask;
356 uint32_t dirty_mask;
357 uint32_t compressed_depthtex_mask; /* which textures are depth */
358 uint32_t compressed_colortex_mask;
359 boolean dirty_buffer_constants;
360 };
361
362 struct r600_sampler_states {
363 struct r600_atom atom;
364 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
365 uint32_t enabled_mask;
366 uint32_t dirty_mask;
367 uint32_t has_bordercolor_mask; /* which states contain the border color */
368 };
369
370 struct r600_textures_info {
371 struct r600_samplerview_state views;
372 struct r600_sampler_states states;
373 bool is_array_sampler[NUM_TEX_UNITS];
374 };
375
376 struct r600_shader_driver_constants_info {
377 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
378 uint32_t *constants;
379 uint32_t alloc_size;
380 bool vs_ucp_dirty;
381 bool texture_const_dirty;
382 bool ps_sample_pos_dirty;
383 };
384
385 struct r600_constbuf_state
386 {
387 struct r600_atom atom;
388 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
389 uint32_t enabled_mask;
390 uint32_t dirty_mask;
391 };
392
393 struct r600_vertexbuf_state
394 {
395 struct r600_atom atom;
396 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
397 uint32_t enabled_mask; /* non-NULL buffers */
398 uint32_t dirty_mask;
399 };
400
401 /* CSO (constant state object, in other words, immutable state). */
402 struct r600_cso_state
403 {
404 struct r600_atom atom;
405 void *cso; /* e.g. r600_blend_state */
406 struct r600_command_buffer *cb;
407 };
408
409 struct r600_fetch_shader {
410 struct r600_resource *buffer;
411 unsigned offset;
412 };
413
414 struct r600_shader_state {
415 struct r600_atom atom;
416 struct r600_pipe_shader *shader;
417 };
418
419 struct r600_context {
420 struct r600_common_context b;
421 struct r600_screen *screen;
422 struct blitter_context *blitter;
423 struct u_suballocator *allocator_fetch_shader;
424
425 /* Hardware info. */
426 boolean has_vertex_cache;
427 unsigned default_gprs[EG_NUM_HW_STAGES];
428 unsigned current_gprs[EG_NUM_HW_STAGES];
429 unsigned r6xx_num_clause_temp_gprs;
430
431 /* Miscellaneous state objects. */
432 void *custom_dsa_flush;
433 void *custom_blend_resolve;
434 void *custom_blend_decompress;
435 void *custom_blend_fastclear;
436 /* With rasterizer discard, there doesn't have to be a pixel shader.
437 * In that case, we bind this one: */
438 void *dummy_pixel_shader;
439 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
440 * bug where valid CMASK and FMASK are required to be present to avoid
441 * a hardlock in certain operations but aren't actually used
442 * for anything useful. */
443 struct r600_resource *dummy_fmask;
444 struct r600_resource *dummy_cmask;
445
446 /* State binding slots are here. */
447 struct r600_atom *atoms[R600_NUM_ATOMS];
448 /* Dirty atom bitmask for fast tests */
449 uint64_t dirty_atoms;
450 /* States for CS initialization. */
451 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
452 /** Compute specific registers initializations. The start_cs_cmd atom
453 * must be emitted before start_compute_cs_cmd. */
454 struct r600_command_buffer start_compute_cs_cmd;
455 /* Register states. */
456 struct r600_alphatest_state alphatest_state;
457 struct r600_cso_state blend_state;
458 struct r600_blend_color blend_color;
459 struct r600_cb_misc_state cb_misc_state;
460 struct r600_clip_misc_state clip_misc_state;
461 struct r600_clip_state clip_state;
462 struct r600_db_misc_state db_misc_state;
463 struct r600_db_state db_state;
464 struct r600_cso_state dsa_state;
465 struct r600_framebuffer framebuffer;
466 struct r600_poly_offset_state poly_offset_state;
467 struct r600_cso_state rasterizer_state;
468 struct r600_sample_mask sample_mask;
469 struct r600_seamless_cube_map seamless_cube_map;
470 struct r600_config_state config_state;
471 struct r600_stencil_ref_state stencil_ref;
472 struct r600_vgt_state vgt_state;
473 /* Shaders and shader resources. */
474 struct r600_cso_state vertex_fetch_shader;
475 struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES];
476 struct r600_cs_shader_state cs_shader_state;
477 struct r600_shader_stages_state shader_stages;
478 struct r600_gs_rings_state gs_rings;
479 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
480 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
481
482 struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES];
483
484 /** Vertex buffers for fetch shaders */
485 struct r600_vertexbuf_state vertex_buffer_state;
486 /** Vertex buffers for compute shaders */
487 struct r600_vertexbuf_state cs_vertex_buffer_state;
488
489 /* Additional context states. */
490 unsigned compute_cb_target_mask;
491 struct r600_pipe_shader_selector *ps_shader;
492 struct r600_pipe_shader_selector *vs_shader;
493 struct r600_pipe_shader_selector *gs_shader;
494
495 struct r600_pipe_shader_selector *tcs_shader;
496 struct r600_pipe_shader_selector *tes_shader;
497
498 struct r600_pipe_shader_selector *fixed_func_tcs_shader;
499
500 struct r600_rasterizer_state *rasterizer;
501 bool alpha_to_one;
502 bool force_blend_disable;
503 boolean dual_src_blend;
504 unsigned zwritemask;
505 int ps_iter_samples;
506
507 /* The list of all texture buffer objects in this context.
508 * This list is walked when a buffer is invalidated/reallocated and
509 * the GPU addresses are updated. */
510 struct list_head texture_buffers;
511
512 /* Last draw state (-1 = unset). */
513 enum pipe_prim_type last_primitive_type; /* Last primitive type used in draw_vbo. */
514 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
515 enum pipe_prim_type last_rast_prim;
516 unsigned last_start_instance;
517
518 void *sb_context;
519 struct r600_isa *isa;
520 float sample_positions[4 * 16];
521 float tess_state[8];
522 bool tess_state_dirty;
523 struct r600_pipe_shader_selector *last_ls;
524 struct r600_pipe_shader_selector *last_tcs;
525 unsigned last_num_tcs_input_cp;
526 unsigned lds_alloc;
527
528 /* Debug state. */
529 bool is_debug;
530 struct radeon_saved_cs last_gfx;
531 struct r600_resource *last_trace_buf;
532 struct r600_resource *trace_buf;
533 unsigned trace_id;
534 };
535
536 static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
537 struct r600_command_buffer *cb)
538 {
539 assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw);
540 memcpy(cs->current.buf + cs->current.cdw, cb->buf, 4 * cb->num_dw);
541 cs->current.cdw += cb->num_dw;
542 }
543
544 static inline void r600_set_atom_dirty(struct r600_context *rctx,
545 struct r600_atom *atom,
546 bool dirty)
547 {
548 uint64_t mask;
549
550 assert(atom->id != 0);
551 assert(atom->id < sizeof(mask) * 8);
552 mask = 1ull << atom->id;
553 if (dirty)
554 rctx->dirty_atoms |= mask;
555 else
556 rctx->dirty_atoms &= ~mask;
557 }
558
559 static inline void r600_mark_atom_dirty(struct r600_context *rctx,
560 struct r600_atom *atom)
561 {
562 r600_set_atom_dirty(rctx, atom, true);
563 }
564
565 static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
566 {
567 atom->emit(&rctx->b, atom);
568 r600_set_atom_dirty(rctx, atom, false);
569 }
570
571 static inline void r600_set_cso_state(struct r600_context *rctx,
572 struct r600_cso_state *state, void *cso)
573 {
574 state->cso = cso;
575 r600_set_atom_dirty(rctx, &state->atom, cso != NULL);
576 }
577
578 static inline void r600_set_cso_state_with_cb(struct r600_context *rctx,
579 struct r600_cso_state *state, void *cso,
580 struct r600_command_buffer *cb)
581 {
582 state->cb = cb;
583 state->atom.num_dw = cb ? cb->num_dw : 0;
584 r600_set_cso_state(rctx, state, cso);
585 }
586
587 /* compute_memory_pool.c */
588 struct compute_memory_pool;
589 void compute_memory_pool_delete(struct compute_memory_pool* pool);
590 struct compute_memory_pool* compute_memory_pool_new(
591 struct r600_screen *rscreen);
592
593 /* evergreen_state.c */
594 struct pipe_sampler_view *
595 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
596 struct pipe_resource *texture,
597 const struct pipe_sampler_view *state,
598 unsigned width0, unsigned height0,
599 unsigned force_level);
600 void evergreen_init_common_regs(struct r600_context *ctx,
601 struct r600_command_buffer *cb,
602 enum chip_class ctx_chip_class,
603 enum radeon_family ctx_family,
604 int ctx_drm_minor);
605 void cayman_init_common_regs(struct r600_command_buffer *cb,
606 enum chip_class ctx_chip_class,
607 enum radeon_family ctx_family,
608 int ctx_drm_minor);
609
610 void evergreen_init_state_functions(struct r600_context *rctx);
611 void evergreen_init_atom_start_cs(struct r600_context *rctx);
612 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
613 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
614 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
615 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
616 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
617 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
618 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
619 void *evergreen_create_resolve_blend(struct r600_context *rctx);
620 void *evergreen_create_decompress_blend(struct r600_context *rctx);
621 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
622 boolean evergreen_is_format_supported(struct pipe_screen *screen,
623 enum pipe_format format,
624 enum pipe_texture_target target,
625 unsigned sample_count,
626 unsigned usage);
627 void evergreen_init_color_surface(struct r600_context *rctx,
628 struct r600_surface *surf);
629 void evergreen_init_color_surface_rat(struct r600_context *rctx,
630 struct r600_surface *surf);
631 void evergreen_update_db_shader_control(struct r600_context * rctx);
632 bool evergreen_adjust_gprs(struct r600_context *rctx);
633 /* r600_blit.c */
634 void r600_init_blit_functions(struct r600_context *rctx);
635 void r600_decompress_depth_textures(struct r600_context *rctx,
636 struct r600_samplerview_state *textures);
637 void r600_decompress_color_textures(struct r600_context *rctx,
638 struct r600_samplerview_state *textures);
639 void r600_resource_copy_region(struct pipe_context *ctx,
640 struct pipe_resource *dst,
641 unsigned dst_level,
642 unsigned dstx, unsigned dsty, unsigned dstz,
643 struct pipe_resource *src,
644 unsigned src_level,
645 const struct pipe_box *src_box);
646
647 /* r600_shader.c */
648 int r600_pipe_shader_create(struct pipe_context *ctx,
649 struct r600_pipe_shader *shader,
650 union r600_shader_key key);
651
652 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
653
654 /* r600_state.c */
655 struct pipe_sampler_view *
656 r600_create_sampler_view_custom(struct pipe_context *ctx,
657 struct pipe_resource *texture,
658 const struct pipe_sampler_view *state,
659 unsigned width_first_level, unsigned height_first_level);
660 void r600_init_state_functions(struct r600_context *rctx);
661 void r600_init_atom_start_cs(struct r600_context *rctx);
662 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
663 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
664 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
665 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
666 void *r600_create_db_flush_dsa(struct r600_context *rctx);
667 void *r600_create_resolve_blend(struct r600_context *rctx);
668 void *r700_create_resolve_blend(struct r600_context *rctx);
669 void *r600_create_decompress_blend(struct r600_context *rctx);
670 bool r600_adjust_gprs(struct r600_context *rctx);
671 boolean r600_is_format_supported(struct pipe_screen *screen,
672 enum pipe_format format,
673 enum pipe_texture_target target,
674 unsigned sample_count,
675 unsigned usage);
676 void r600_update_db_shader_control(struct r600_context * rctx);
677
678 /* r600_hw_context.c */
679 void r600_context_gfx_flush(void *context, unsigned flags,
680 struct pipe_fence_handle **fence);
681 void r600_begin_new_cs(struct r600_context *ctx);
682 void r600_flush_emit(struct r600_context *ctx);
683 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
684 void r600_emit_pfp_sync_me(struct r600_context *rctx);
685 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
686 struct pipe_resource *dst, uint64_t dst_offset,
687 struct pipe_resource *src, uint64_t src_offset,
688 unsigned size);
689 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
690 struct pipe_resource *dst, uint64_t offset,
691 unsigned size, uint32_t clear_value,
692 enum r600_coherency coher);
693 void r600_dma_copy_buffer(struct r600_context *rctx,
694 struct pipe_resource *dst,
695 struct pipe_resource *src,
696 uint64_t dst_offset,
697 uint64_t src_offset,
698 uint64_t size);
699
700 /*
701 * evergreen_hw_context.c
702 */
703 void evergreen_dma_copy_buffer(struct r600_context *rctx,
704 struct pipe_resource *dst,
705 struct pipe_resource *src,
706 uint64_t dst_offset,
707 uint64_t src_offset,
708 uint64_t size);
709 void evergreen_setup_tess_constants(struct r600_context *rctx,
710 const struct pipe_draw_info *info,
711 unsigned *num_patches);
712 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
713 const struct pipe_draw_info *info,
714 unsigned num_patches);
715 void evergreen_set_ls_hs_config(struct r600_context *rctx,
716 struct radeon_winsys_cs *cs,
717 uint32_t ls_hs_config);
718 void evergreen_set_lds_alloc(struct r600_context *rctx,
719 struct radeon_winsys_cs *cs,
720 uint32_t lds_alloc);
721
722 /* r600_state_common.c */
723 void r600_init_common_state_functions(struct r600_context *rctx);
724 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
725 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
726 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
727 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
728 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
729 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
730 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
731 void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
732 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
733 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
734 unsigned num_dw);
735 void r600_vertex_buffers_dirty(struct r600_context *rctx);
736 void r600_sampler_views_dirty(struct r600_context *rctx,
737 struct r600_samplerview_state *state);
738 void r600_sampler_states_dirty(struct r600_context *rctx,
739 struct r600_sampler_states *state);
740 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
741 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
742 uint32_t r600_translate_stencil_op(int s_op);
743 uint32_t r600_translate_fill(uint32_t func);
744 unsigned r600_tex_wrap(unsigned wrap);
745 unsigned r600_tex_mipfilter(unsigned filter);
746 unsigned r600_tex_compare(unsigned compare);
747 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
748 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
749 const unsigned char *swizzle_view,
750 boolean vtx);
751 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
752 const unsigned char *swizzle_view,
753 uint32_t *word4_p, uint32_t *yuv_format_p,
754 bool do_endian_swap);
755 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format,
756 bool do_endian_swap);
757 uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap);
758
759 /* r600_uvd.c */
760 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
761 const struct pipe_video_codec *decoder);
762
763 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
764 const struct pipe_video_buffer *tmpl);
765
766 /*
767 * Helpers for building command buffers
768 */
769
770 #define PKT3_SET_CONFIG_REG 0x68
771 #define PKT3_SET_CONTEXT_REG 0x69
772 #define PKT3_SET_CTL_CONST 0x6F
773 #define PKT3_SET_LOOP_CONST 0x6C
774
775 #define R600_CONFIG_REG_OFFSET 0x08000
776 #define R600_CONTEXT_REG_OFFSET 0x28000
777 #define R600_CTL_CONST_OFFSET 0x3CFF0
778 #define R600_LOOP_CONST_OFFSET 0X0003E200
779 #define EG_LOOP_CONST_OFFSET 0x0003A200
780
781 #define PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30)
782 #define PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16)
783 #define PKT3_IT_OPCODE_S(x) (((unsigned)(x) & 0xFF) << 8)
784 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
785 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
786
787 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
788
789 /*Evergreen Compute packet3*/
790 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
791
792 static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value)
793 {
794 cb->buf[cb->num_dw++] = value;
795 }
796
797 static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
798 {
799 assert(cb->num_dw+num <= cb->max_num_dw);
800 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
801 cb->num_dw += num;
802 }
803
804 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
805 {
806 assert(reg < R600_CONTEXT_REG_OFFSET);
807 assert(cb->num_dw+2+num <= cb->max_num_dw);
808 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
809 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
810 }
811
812 /**
813 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
814 * shaders.
815 */
816 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
817 {
818 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
819 assert(cb->num_dw+2+num <= cb->max_num_dw);
820 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
821 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
822 }
823
824 /**
825 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
826 * shaders.
827 */
828 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
829 {
830 assert(reg >= R600_CTL_CONST_OFFSET);
831 assert(cb->num_dw+2+num <= cb->max_num_dw);
832 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
833 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
834 }
835
836 static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
837 {
838 assert(reg >= R600_LOOP_CONST_OFFSET);
839 assert(cb->num_dw+2+num <= cb->max_num_dw);
840 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
841 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
842 }
843
844 /**
845 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
846 * shaders.
847 */
848 static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
849 {
850 assert(reg >= EG_LOOP_CONST_OFFSET);
851 assert(cb->num_dw+2+num <= cb->max_num_dw);
852 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
853 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
854 }
855
856 static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
857 {
858 r600_store_config_reg_seq(cb, reg, 1);
859 r600_store_value(cb, value);
860 }
861
862 static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
863 {
864 r600_store_context_reg_seq(cb, reg, 1);
865 r600_store_value(cb, value);
866 }
867
868 static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
869 {
870 r600_store_ctl_const_seq(cb, reg, 1);
871 r600_store_value(cb, value);
872 }
873
874 static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
875 {
876 r600_store_loop_const_seq(cb, reg, 1);
877 r600_store_value(cb, value);
878 }
879
880 static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
881 {
882 eg_store_loop_const_seq(cb, reg, 1);
883 r600_store_value(cb, value);
884 }
885
886 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
887 void r600_release_command_buffer(struct r600_command_buffer *cb);
888
889 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
890 {
891 radeon_set_context_reg_seq(cs, reg, num);
892 /* Set the compute bit on the packet header */
893 cs->current.buf[cs->current.cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
894 }
895
896 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
897 {
898 assert(reg >= R600_CTL_CONST_OFFSET);
899 assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
900 radeon_emit(cs, PKT3(PKT3_SET_CTL_CONST, num, 0));
901 radeon_emit(cs, (reg - R600_CTL_CONST_OFFSET) >> 2);
902 }
903
904 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
905 {
906 radeon_compute_set_context_reg_seq(cs, reg, 1);
907 radeon_emit(cs, value);
908 }
909
910 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
911 {
912 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
913 radeon_compute_set_context_reg(cs, reg, value);
914 } else {
915 radeon_set_context_reg(cs, reg, value);
916 }
917 }
918
919 static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
920 {
921 radeon_set_ctl_const_seq(cs, reg, 1);
922 radeon_emit(cs, value);
923 }
924
925 /*
926 * common helpers
927 */
928
929 /* 12.4 fixed-point */
930 static inline unsigned r600_pack_float_12p4(float x)
931 {
932 return x <= 0 ? 0 :
933 x >= 4096 ? 0xffff : x * 16;
934 }
935
936 static inline unsigned r600_get_flush_flags(enum r600_coherency coher)
937 {
938 switch (coher) {
939 default:
940 case R600_COHERENCY_NONE:
941 return 0;
942 case R600_COHERENCY_SHADER:
943 return R600_CONTEXT_INV_CONST_CACHE |
944 R600_CONTEXT_INV_VERTEX_CACHE |
945 R600_CONTEXT_INV_TEX_CACHE |
946 R600_CONTEXT_STREAMOUT_FLUSH;
947 case R600_COHERENCY_CB_META:
948 return R600_CONTEXT_FLUSH_AND_INV_CB |
949 R600_CONTEXT_FLUSH_AND_INV_CB_META;
950 }
951 }
952
953 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
954 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
955 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
956
957 unsigned r600_conv_prim_to_gs_out(unsigned mode);
958
959 void eg_trace_emit(struct r600_context *rctx);
960 void eg_dump_debug_state(struct pipe_context *ctx, FILE *f,
961 unsigned flags);
962 #endif