2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "../radeon/r600_pipe_common.h"
30 #include "../radeon/r600_cs.h"
32 #include "r600_llvm.h"
33 #include "r600_public.h"
34 #include "r600_resource.h"
36 #include "util/u_blitter.h"
37 #include "util/u_slab.h"
38 #include "util/u_suballoc.h"
39 #include "util/u_double_list.h"
40 #include "util/u_transfer.h"
42 #define R600_NUM_ATOMS 41
44 /* the number of CS dwords for flushing and drawing */
45 #define R600_MAX_FLUSH_CS_DWORDS 16
46 #define R600_MAX_DRAW_CS_DWORDS 34
47 #define R600_TRACE_CS_DWORDS 7
49 #define R600_MAX_USER_CONST_BUFFERS 13
50 #define R600_MAX_DRIVER_CONST_BUFFERS 3
51 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
53 /* start driver buffers after user buffers */
54 #define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
55 #define R600_TXQ_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
56 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
58 #define R600_MAX_CONST_BUFFER_SIZE 4096
60 #ifdef PIPE_ARCH_BIG_ENDIAN
61 #define R600_BIG_ENDIAN 1
63 #define R600_BIG_ENDIAN 0
66 #define R600_MAP_BUFFER_ALIGNMENT 64
68 #define R600_ERR(fmt, args...) \
69 fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
71 #define R600_QUERY_DRAW_CALLS (PIPE_QUERY_DRIVER_SPECIFIC + 0)
72 #define R600_QUERY_REQUESTED_VRAM (PIPE_QUERY_DRIVER_SPECIFIC + 1)
73 #define R600_QUERY_REQUESTED_GTT (PIPE_QUERY_DRIVER_SPECIFIC + 2)
74 #define R600_QUERY_BUFFER_WAIT_TIME (PIPE_QUERY_DRIVER_SPECIFIC + 3)
78 struct r600_shader_key
;
80 /* This is an atom containing GPU commands that never change.
81 * This is supposed to be copied directly into the CS. */
82 struct r600_command_buffer
{
89 struct r600_db_state
{
90 struct r600_atom atom
;
91 struct r600_surface
*rsurf
;
94 struct r600_db_misc_state
{
95 struct r600_atom atom
;
96 bool occlusion_query_enabled
;
97 bool flush_depthstencil_through_cb
;
98 bool flush_depthstencil_in_place
;
99 bool copy_depth
, copy_stencil
;
100 unsigned copy_sample
;
101 unsigned log_samples
;
102 unsigned db_shader_control
;
106 struct r600_cb_misc_state
{
107 struct r600_atom atom
;
108 unsigned cb_color_control
; /* this comes from blend state */
109 unsigned blend_colormask
; /* 8*4 bits for 8 RGBA colorbuffers */
111 unsigned nr_ps_color_outputs
;
116 struct r600_clip_misc_state
{
117 struct r600_atom atom
;
118 unsigned pa_cl_clip_cntl
; /* from rasterizer */
119 unsigned pa_cl_vs_out_cntl
; /* from vertex shader */
120 unsigned clip_plane_enable
; /* from rasterizer */
121 unsigned clip_dist_write
; /* from vertex shader */
124 struct r600_alphatest_state
{
125 struct r600_atom atom
;
126 unsigned sx_alpha_test_control
; /* this comes from dsa state */
127 unsigned sx_alpha_ref
; /* this comes from dsa state */
129 bool cb0_export_16bpc
; /* from set_framebuffer_state */
132 struct r600_vgt_state
{
133 struct r600_atom atom
;
134 uint32_t vgt_multi_prim_ib_reset_en
;
135 uint32_t vgt_multi_prim_ib_reset_indx
;
136 uint32_t vgt_indx_offset
;
139 struct r600_blend_color
{
140 struct r600_atom atom
;
141 struct pipe_blend_color state
;
144 struct r600_clip_state
{
145 struct r600_atom atom
;
146 struct pipe_clip_state state
;
149 struct r600_cs_shader_state
{
150 struct r600_atom atom
;
151 unsigned kernel_index
;
152 struct r600_pipe_compute
*shader
;
155 struct r600_framebuffer
{
156 struct r600_atom atom
;
157 struct pipe_framebuffer_state state
;
158 unsigned compressed_cb_mask
;
162 bool is_msaa_resolve
;
165 struct r600_sample_mask
{
166 struct r600_atom atom
;
167 uint16_t sample_mask
; /* there are only 8 bits on EG, 16 bits on Cayman */
170 struct r600_config_state
{
171 struct r600_atom atom
;
172 unsigned sq_gpr_resource_mgmt_1
;
175 struct r600_stencil_ref
182 struct r600_stencil_ref_state
{
183 struct r600_atom atom
;
184 struct r600_stencil_ref state
;
185 struct pipe_stencil_ref pipe_state
;
188 struct r600_viewport_state
{
189 struct r600_atom atom
;
190 struct pipe_viewport_state state
;
193 struct r600_pipe_fences
{
194 struct r600_resource
*bo
;
197 /* linked list of preallocated blocks */
198 struct list_head blocks
;
199 /* linked list of freed fences */
200 struct list_head pool
;
204 typedef boolean (*r600g_dma_blit_t
)(struct pipe_context
*ctx
,
205 struct pipe_resource
*dst
,
207 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
208 struct pipe_resource
*src
,
210 const struct pipe_box
*src_box
);
213 #define DBG_TEX_DEPTH (1 << 0)
214 #define DBG_COMPUTE (1 << 1)
215 #define DBG_VM (1 << 2)
216 #define DBG_TRACE_CS (1 << 3)
218 #define DBG_FS (1 << 8)
219 #define DBG_VS (1 << 9)
220 #define DBG_GS (1 << 10)
221 #define DBG_PS (1 << 11)
222 #define DBG_CS (1 << 12)
224 #define DBG_NO_HYPERZ (1 << 16)
225 #define DBG_NO_LLVM (1 << 17)
226 #define DBG_NO_CP_DMA (1 << 18)
227 #define DBG_NO_ASYNC_DMA (1 << 19)
228 #define DBG_NO_DISCARD_RANGE (1 << 20)
230 #define DBG_NO_SB (1 << 21)
231 #define DBG_SB_CS (1 << 22)
232 #define DBG_SB_DRY_RUN (1 << 23)
233 #define DBG_SB_STAT (1 << 24)
234 #define DBG_SB_DUMP (1 << 25)
235 #define DBG_SB_NO_FALLBACK (1 << 26)
236 #define DBG_SB_DISASM (1 << 27)
237 #define DBG_SB_SAFEMATH (1 << 28)
239 struct r600_tiling_info
{
240 unsigned num_channels
;
242 unsigned group_bytes
;
246 struct r600_common_screen b
;
247 unsigned debug_flags
;
251 bool has_compressed_msaa_texturing
;
252 struct r600_tiling_info tiling_info
;
253 struct r600_pipe_fences fences
;
255 /*for compute global memory binding, we allocate stuff here, instead of
257 * XXX: Not sure if this is the best place for global_pool. Also,
258 * it's not thread safe, so it won't work with multiple contexts. */
259 struct compute_memory_pool
*global_pool
;
260 struct r600_resource
*trace_bo
;
263 r600g_dma_blit_t dma_blit
;
265 /* Auxiliary context. Mainly used to initialize resources.
266 * It must be locked prior to using and flushed before unlocking. */
267 struct pipe_context
*aux_context
;
268 pipe_mutex aux_context_lock
;
271 struct r600_pipe_sampler_view
{
272 struct pipe_sampler_view base
;
273 struct r600_resource
*tex_resource
;
274 uint32_t tex_resource_words
[8];
275 bool skip_mip_address_reloc
;
278 struct r600_rasterizer_state
{
279 struct r600_command_buffer buffer
;
282 unsigned sprite_coord_enable
;
283 unsigned clip_plane_enable
;
284 unsigned pa_sc_line_stipple
;
285 unsigned pa_cl_clip_cntl
;
290 bool multisample_enable
;
293 struct r600_poly_offset_state
{
294 struct r600_atom atom
;
295 enum pipe_format zs_format
;
300 struct r600_blend_state
{
301 struct r600_command_buffer buffer
;
302 struct r600_command_buffer buffer_no_blend
;
303 unsigned cb_target_mask
;
304 unsigned cb_color_control
;
305 unsigned cb_color_control_no_blend
;
310 struct r600_dsa_state
{
311 struct r600_command_buffer buffer
;
316 unsigned sx_alpha_test_control
;
319 struct r600_pipe_shader
;
321 struct r600_pipe_shader_selector
{
322 struct r600_pipe_shader
*current
;
324 struct tgsi_token
*tokens
;
325 struct pipe_stream_output_info so
;
327 unsigned num_shaders
;
329 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
332 unsigned nr_ps_max_color_exports
;
335 struct r600_pipe_sampler_state
{
336 uint32_t tex_sampler_words
[3];
337 union pipe_color_union border_color
;
338 bool border_color_use
;
339 bool seamless_cube_map
;
342 /* needed for blitter save */
343 #define NUM_TEX_UNITS 16
345 struct r600_seamless_cube_map
{
346 struct r600_atom atom
;
350 struct r600_samplerview_state
{
351 struct r600_atom atom
;
352 struct r600_pipe_sampler_view
*views
[NUM_TEX_UNITS
];
353 uint32_t enabled_mask
;
355 uint32_t compressed_depthtex_mask
; /* which textures are depth */
356 uint32_t compressed_colortex_mask
;
357 boolean dirty_txq_constants
;
358 boolean dirty_buffer_constants
;
361 struct r600_sampler_states
{
362 struct r600_atom atom
;
363 struct r600_pipe_sampler_state
*states
[NUM_TEX_UNITS
];
364 uint32_t enabled_mask
;
366 uint32_t has_bordercolor_mask
; /* which states contain the border color */
369 struct r600_textures_info
{
370 struct r600_samplerview_state views
;
371 struct r600_sampler_states states
;
372 bool is_array_sampler
[NUM_TEX_UNITS
];
374 /* cube array txq workaround */
375 uint32_t *txq_constants
;
376 /* buffer related workarounds */
377 uint32_t *buffer_constants
;
381 struct pipe_reference reference
;
382 unsigned index
; /* in the shared bo */
383 struct r600_resource
*sleep_bo
;
384 struct list_head head
;
387 #define FENCE_BLOCK_SIZE 16
389 struct r600_fence_block
{
390 struct r600_fence fences
[FENCE_BLOCK_SIZE
];
391 struct list_head head
;
394 struct r600_constbuf_state
396 struct r600_atom atom
;
397 struct pipe_constant_buffer cb
[PIPE_MAX_CONSTANT_BUFFERS
];
398 uint32_t enabled_mask
;
402 struct r600_vertexbuf_state
404 struct r600_atom atom
;
405 struct pipe_vertex_buffer vb
[PIPE_MAX_ATTRIBS
];
406 uint32_t enabled_mask
; /* non-NULL buffers */
410 /* CSO (constant state object, in other words, immutable state). */
411 struct r600_cso_state
413 struct r600_atom atom
;
414 void *cso
; /* e.g. r600_blend_state */
415 struct r600_command_buffer
*cb
;
418 struct r600_scissor_state
420 struct r600_atom atom
;
421 struct pipe_scissor_state scissor
;
422 bool enable
; /* r6xx only */
425 struct r600_fetch_shader
{
426 struct r600_resource
*buffer
;
430 struct r600_shader_state
{
431 struct r600_atom atom
;
432 struct r600_pipe_shader_selector
*shader
;
435 struct r600_query_buffer
{
436 /* The buffer where query results are stored. */
437 struct r600_resource
*buf
;
438 /* Offset of the next free result after current query data */
439 unsigned results_end
;
440 /* If a query buffer is full, a new buffer is created and the old one
441 * is put in here. When we calculate the result, we sum up the samples
442 * from all buffers. */
443 struct r600_query_buffer
*previous
;
447 /* The query buffer and how many results are in it. */
448 struct r600_query_buffer buffer
;
449 /* The type of query */
451 /* Size of the result in memory for both begin_query and end_query,
452 * this can be one or two numbers, or it could even be a size of a structure. */
453 unsigned result_size
;
454 /* The number of dwords for begin_query or end_query. */
456 /* linked list of queries */
457 struct list_head list
;
458 /* for custom non-GPU queries */
459 uint64_t begin_result
;
463 struct r600_context
{
464 struct r600_common_context b
;
465 struct r600_screen
*screen
;
466 struct blitter_context
*blitter
;
467 struct u_upload_mgr
*uploader
;
468 struct u_suballocator
*allocator_fetch_shader
;
469 struct util_slab_mempool pool_transfers
;
470 unsigned initial_gfx_cs_size
;
473 boolean has_vertex_cache
;
474 boolean keep_tiling_flags
;
475 unsigned default_ps_gprs
, default_vs_gprs
;
476 unsigned r6xx_num_clause_temp_gprs
;
477 unsigned backend_mask
;
478 unsigned max_db
; /* for OQ */
480 /* Miscellaneous state objects. */
481 void *custom_dsa_flush
;
482 void *custom_blend_resolve
;
483 void *custom_blend_decompress
;
484 /* With rasterizer discard, there doesn't have to be a pixel shader.
485 * In that case, we bind this one: */
486 void *dummy_pixel_shader
;
487 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
488 * bug where valid CMASK and FMASK are required to be present to avoid
489 * a hardlock in certain operations but aren't actually used
490 * for anything useful. */
491 struct r600_resource
*dummy_fmask
;
492 struct r600_resource
*dummy_cmask
;
494 /* State binding slots are here. */
495 struct r600_atom
*atoms
[R600_NUM_ATOMS
];
496 /* States for CS initialization. */
497 struct r600_command_buffer start_cs_cmd
; /* invariant state mostly */
498 /** Compute specific registers initializations. The start_cs_cmd atom
499 * must be emitted before start_compute_cs_cmd. */
500 struct r600_command_buffer start_compute_cs_cmd
;
501 /* Register states. */
502 struct r600_alphatest_state alphatest_state
;
503 struct r600_cso_state blend_state
;
504 struct r600_blend_color blend_color
;
505 struct r600_cb_misc_state cb_misc_state
;
506 struct r600_clip_misc_state clip_misc_state
;
507 struct r600_clip_state clip_state
;
508 struct r600_db_misc_state db_misc_state
;
509 struct r600_db_state db_state
;
510 struct r600_cso_state dsa_state
;
511 struct r600_framebuffer framebuffer
;
512 struct r600_poly_offset_state poly_offset_state
;
513 struct r600_cso_state rasterizer_state
;
514 struct r600_sample_mask sample_mask
;
515 struct r600_scissor_state scissor
;
516 struct r600_seamless_cube_map seamless_cube_map
;
517 struct r600_config_state config_state
;
518 struct r600_stencil_ref_state stencil_ref
;
519 struct r600_vgt_state vgt_state
;
520 struct r600_viewport_state viewport
;
521 /* Shaders and shader resources. */
522 struct r600_cso_state vertex_fetch_shader
;
523 struct r600_shader_state vertex_shader
;
524 struct r600_shader_state pixel_shader
;
525 struct r600_cs_shader_state cs_shader_state
;
526 struct r600_constbuf_state constbuf_state
[PIPE_SHADER_TYPES
];
527 struct r600_textures_info samplers
[PIPE_SHADER_TYPES
];
528 /** Vertex buffers for fetch shaders */
529 struct r600_vertexbuf_state vertex_buffer_state
;
530 /** Vertex buffers for compute shaders */
531 struct r600_vertexbuf_state cs_vertex_buffer_state
;
533 /* Additional context states. */
534 unsigned compute_cb_target_mask
;
535 struct r600_pipe_shader_selector
*ps_shader
;
536 struct r600_pipe_shader_selector
*vs_shader
;
537 struct r600_rasterizer_state
*rasterizer
;
539 bool force_blend_disable
;
540 boolean dual_src_blend
;
544 struct pipe_index_buffer index_buffer
;
546 /* Last draw state (-1 = unset). */
547 int last_primitive_type
; /* Last primitive type used in draw_vbo. */
548 int last_start_instance
;
551 /* The list of active queries. Only one query of each type can be active. */
552 int num_occlusion_queries
;
553 int num_pipelinestat_queries
;
554 /* Keep track of non-timer queries, because they should be suspended
555 * during context flushing.
556 * The timer queries (TIME_ELAPSED) shouldn't be suspended. */
557 struct list_head active_nontimer_queries
;
558 unsigned num_cs_dw_nontimer_queries_suspend
;
559 /* If queries have been suspended. */
560 bool nontimer_queries_suspended
;
561 unsigned num_draw_calls
;
563 /* Render condition. */
564 struct pipe_query
*current_render_cond
;
565 unsigned current_render_cond_mode
;
566 boolean current_render_cond_cond
;
567 boolean predicate_drawing
;
570 struct r600_isa
*isa
;
573 static INLINE
void r600_emit_command_buffer(struct radeon_winsys_cs
*cs
,
574 struct r600_command_buffer
*cb
)
576 assert(cs
->cdw
+ cb
->num_dw
<= RADEON_MAX_CMDBUF_DWORDS
);
577 memcpy(cs
->buf
+ cs
->cdw
, cb
->buf
, 4 * cb
->num_dw
);
578 cs
->cdw
+= cb
->num_dw
;
581 void r600_trace_emit(struct r600_context
*rctx
);
583 static INLINE
void r600_emit_atom(struct r600_context
*rctx
, struct r600_atom
*atom
)
585 atom
->emit(&rctx
->b
, atom
);
587 if (rctx
->screen
->trace_bo
) {
588 r600_trace_emit(rctx
);
592 static INLINE
void r600_set_cso_state(struct r600_cso_state
*state
, void *cso
)
595 state
->atom
.dirty
= cso
!= NULL
;
598 static INLINE
void r600_set_cso_state_with_cb(struct r600_cso_state
*state
, void *cso
,
599 struct r600_command_buffer
*cb
)
602 state
->atom
.num_dw
= cb
->num_dw
;
603 r600_set_cso_state(state
, cso
);
606 /* compute_memory_pool.c */
607 struct compute_memory_pool
;
608 void compute_memory_pool_delete(struct compute_memory_pool
* pool
);
609 struct compute_memory_pool
* compute_memory_pool_new(
610 struct r600_screen
*rscreen
);
612 /* evergreen_state.c */
613 struct pipe_sampler_view
*
614 evergreen_create_sampler_view_custom(struct pipe_context
*ctx
,
615 struct pipe_resource
*texture
,
616 const struct pipe_sampler_view
*state
,
617 unsigned width0
, unsigned height0
);
618 void evergreen_init_common_regs(struct r600_command_buffer
*cb
,
619 enum chip_class ctx_chip_class
,
620 enum radeon_family ctx_family
,
622 void cayman_init_common_regs(struct r600_command_buffer
*cb
,
623 enum chip_class ctx_chip_class
,
624 enum radeon_family ctx_family
,
627 void evergreen_init_state_functions(struct r600_context
*rctx
);
628 void evergreen_init_atom_start_cs(struct r600_context
*rctx
);
629 void evergreen_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
630 void evergreen_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
631 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
);
632 void *evergreen_create_resolve_blend(struct r600_context
*rctx
);
633 void *evergreen_create_decompress_blend(struct r600_context
*rctx
);
634 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
635 enum pipe_format format
,
636 enum pipe_texture_target target
,
637 unsigned sample_count
,
639 void evergreen_init_color_surface(struct r600_context
*rctx
,
640 struct r600_surface
*surf
);
641 void evergreen_init_color_surface_rat(struct r600_context
*rctx
,
642 struct r600_surface
*surf
);
643 void evergreen_update_db_shader_control(struct r600_context
* rctx
);
646 void r600_copy_buffer(struct pipe_context
*ctx
, struct pipe_resource
*dst
, unsigned dstx
,
647 struct pipe_resource
*src
, const struct pipe_box
*src_box
);
648 void r600_screen_clear_buffer(struct r600_screen
*rscreen
, struct pipe_resource
*dst
,
649 unsigned offset
, unsigned size
, unsigned char value
);
650 void r600_init_blit_functions(struct r600_context
*rctx
);
651 void r600_blit_decompress_depth(struct pipe_context
*ctx
,
652 struct r600_texture
*texture
,
653 struct r600_texture
*staging
,
654 unsigned first_level
, unsigned last_level
,
655 unsigned first_layer
, unsigned last_layer
,
656 unsigned first_sample
, unsigned last_sample
);
657 void r600_decompress_depth_textures(struct r600_context
*rctx
,
658 struct r600_samplerview_state
*textures
);
659 void r600_decompress_color_textures(struct r600_context
*rctx
,
660 struct r600_samplerview_state
*textures
);
663 bool r600_init_resource(struct r600_screen
*rscreen
,
664 struct r600_resource
*res
,
665 unsigned size
, unsigned alignment
,
666 bool use_reusable_pool
, unsigned usage
);
667 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
668 const struct pipe_resource
*templ
,
672 boolean
r600_rings_is_buffer_referenced(struct r600_context
*ctx
,
673 struct radeon_winsys_cs_handle
*buf
,
674 enum radeon_bo_usage usage
);
675 void *r600_buffer_mmap_sync_with_rings(struct r600_context
*ctx
,
676 struct r600_resource
*resource
,
678 const char * r600_llvm_gpu_string(enum radeon_family family
);
682 void r600_init_query_functions(struct r600_context
*rctx
);
683 void r600_suspend_nontimer_queries(struct r600_context
*ctx
);
684 void r600_resume_nontimer_queries(struct r600_context
*ctx
);
686 /* r600_resource.c */
687 void r600_init_context_resource_functions(struct r600_context
*r600
);
690 int r600_pipe_shader_create(struct pipe_context
*ctx
,
691 struct r600_pipe_shader
*shader
,
692 struct r600_shader_key key
);
694 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
697 struct pipe_sampler_view
*
698 r600_create_sampler_view_custom(struct pipe_context
*ctx
,
699 struct pipe_resource
*texture
,
700 const struct pipe_sampler_view
*state
,
701 unsigned width_first_level
, unsigned height_first_level
);
702 void r600_init_state_functions(struct r600_context
*rctx
);
703 void r600_init_atom_start_cs(struct r600_context
*rctx
);
704 void r600_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
705 void r600_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
706 void *r600_create_db_flush_dsa(struct r600_context
*rctx
);
707 void *r600_create_resolve_blend(struct r600_context
*rctx
);
708 void *r700_create_resolve_blend(struct r600_context
*rctx
);
709 void *r600_create_decompress_blend(struct r600_context
*rctx
);
710 bool r600_adjust_gprs(struct r600_context
*rctx
);
711 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
712 enum pipe_format format
,
713 enum pipe_texture_target target
,
714 unsigned sample_count
,
716 void r600_update_db_shader_control(struct r600_context
* rctx
);
719 void r600_init_screen_texture_functions(struct pipe_screen
*screen
);
720 void r600_init_surface_functions(struct r600_context
*r600
);
721 uint32_t r600_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
722 const unsigned char *swizzle_view
,
723 uint32_t *word4_p
, uint32_t *yuv_format_p
);
724 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
725 struct pipe_resource
*texture
,
726 const struct pipe_surface
*templ
,
727 unsigned width
, unsigned height
);
729 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
730 const unsigned char *swizzle_view
,
733 /* r600_hw_context.c */
734 void r600_get_backend_mask(struct r600_context
*ctx
);
735 void r600_context_flush(struct r600_context
*ctx
, unsigned flags
);
736 void r600_begin_new_cs(struct r600_context
*ctx
);
737 void r600_context_emit_fence(struct r600_context
*ctx
, struct r600_resource
*fence
,
738 unsigned offset
, unsigned value
);
739 void r600_flush_emit(struct r600_context
*ctx
);
740 void r600_need_cs_space(struct r600_context
*ctx
, unsigned num_dw
, boolean count_draw_in
);
741 void r600_need_dma_space(struct r600_context
*ctx
, unsigned num_dw
);
742 void r600_cp_dma_copy_buffer(struct r600_context
*rctx
,
743 struct pipe_resource
*dst
, uint64_t dst_offset
,
744 struct pipe_resource
*src
, uint64_t src_offset
,
746 void evergreen_cp_dma_clear_buffer(struct r600_context
*rctx
,
747 struct pipe_resource
*dst
, uint64_t offset
,
748 unsigned size
, uint32_t clear_value
);
749 void r600_dma_copy(struct r600_context
*rctx
,
750 struct pipe_resource
*dst
,
751 struct pipe_resource
*src
,
755 boolean
r600_dma_blit(struct pipe_context
*ctx
,
756 struct pipe_resource
*dst
,
758 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
759 struct pipe_resource
*src
,
761 const struct pipe_box
*src_box
);
762 void r600_flag_resource_cache_flush(struct r600_context
*rctx
,
763 struct pipe_resource
*res
);
766 * evergreen_hw_context.c
768 void evergreen_dma_copy(struct r600_context
*rctx
,
769 struct pipe_resource
*dst
,
770 struct pipe_resource
*src
,
774 boolean
evergreen_dma_blit(struct pipe_context
*ctx
,
775 struct pipe_resource
*dst
,
777 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
778 struct pipe_resource
*src
,
780 const struct pipe_box
*src_box
);
782 /* r600_state_common.c */
783 void r600_init_common_state_functions(struct r600_context
*rctx
);
784 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
785 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
786 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
);
787 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
788 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
789 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
);
790 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
791 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
);
792 void r600_init_atom(struct r600_context
*rctx
, struct r600_atom
*atom
, unsigned id
,
793 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
795 void r600_vertex_buffers_dirty(struct r600_context
*rctx
);
796 void r600_sampler_views_dirty(struct r600_context
*rctx
,
797 struct r600_samplerview_state
*state
);
798 void r600_sampler_states_dirty(struct r600_context
*rctx
,
799 struct r600_sampler_states
*state
);
800 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
);
801 void r600_draw_rectangle(struct blitter_context
*blitter
,
802 int x1
, int y1
, int x2
, int y2
, float depth
,
803 enum blitter_attrib_type type
, const union pipe_color_union
*attrib
);
804 uint32_t r600_translate_stencil_op(int s_op
);
805 uint32_t r600_translate_fill(uint32_t func
);
806 unsigned r600_tex_wrap(unsigned wrap
);
807 unsigned r600_tex_filter(unsigned filter
);
808 unsigned r600_tex_mipfilter(unsigned filter
);
809 unsigned r600_tex_compare(unsigned compare
);
810 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
);
813 struct pipe_video_codec
*r600_uvd_create_decoder(struct pipe_context
*context
,
814 const struct pipe_video_codec
*decoder
);
816 struct pipe_video_buffer
*r600_video_buffer_create(struct pipe_context
*pipe
,
817 const struct pipe_video_buffer
*tmpl
);
819 int r600_uvd_get_video_param(struct pipe_screen
*screen
,
820 enum pipe_video_profile profile
,
821 enum pipe_video_entrypoint entrypoint
,
822 enum pipe_video_cap param
);
825 * Helpers for building command buffers
828 #define PKT3_SET_CONFIG_REG 0x68
829 #define PKT3_SET_CONTEXT_REG 0x69
830 #define PKT3_SET_CTL_CONST 0x6F
831 #define PKT3_SET_LOOP_CONST 0x6C
833 #define R600_CONFIG_REG_OFFSET 0x08000
834 #define R600_CONTEXT_REG_OFFSET 0x28000
835 #define R600_CTL_CONST_OFFSET 0x3CFF0
836 #define R600_LOOP_CONST_OFFSET 0X0003E200
837 #define EG_LOOP_CONST_OFFSET 0x0003A200
839 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
840 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
841 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
842 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
843 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
845 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
847 /*Evergreen Compute packet3*/
848 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
850 static INLINE
void r600_store_value(struct r600_command_buffer
*cb
, unsigned value
)
852 cb
->buf
[cb
->num_dw
++] = value
;
855 static INLINE
void r600_store_array(struct r600_command_buffer
*cb
, unsigned num
, unsigned *ptr
)
857 assert(cb
->num_dw
+num
<= cb
->max_num_dw
);
858 memcpy(&cb
->buf
[cb
->num_dw
], ptr
, num
* sizeof(ptr
[0]));
862 static INLINE
void r600_store_config_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
864 assert(reg
< R600_CONTEXT_REG_OFFSET
);
865 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
866 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
867 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
871 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
874 static INLINE
void r600_store_context_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
876 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
877 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
878 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0) | cb
->pkt_flags
;
879 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
883 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
886 static INLINE
void r600_store_ctl_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
888 assert(reg
>= R600_CTL_CONST_OFFSET
);
889 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
890 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0) | cb
->pkt_flags
;
891 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
894 static INLINE
void r600_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
896 assert(reg
>= R600_LOOP_CONST_OFFSET
);
897 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
898 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0);
899 cb
->buf
[cb
->num_dw
++] = (reg
- R600_LOOP_CONST_OFFSET
) >> 2;
903 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
906 static INLINE
void eg_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
908 assert(reg
>= EG_LOOP_CONST_OFFSET
);
909 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
910 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0) | cb
->pkt_flags
;
911 cb
->buf
[cb
->num_dw
++] = (reg
- EG_LOOP_CONST_OFFSET
) >> 2;
914 static INLINE
void r600_store_config_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
916 r600_store_config_reg_seq(cb
, reg
, 1);
917 r600_store_value(cb
, value
);
920 static INLINE
void r600_store_context_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
922 r600_store_context_reg_seq(cb
, reg
, 1);
923 r600_store_value(cb
, value
);
926 static INLINE
void r600_store_ctl_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
928 r600_store_ctl_const_seq(cb
, reg
, 1);
929 r600_store_value(cb
, value
);
932 static INLINE
void r600_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
934 r600_store_loop_const_seq(cb
, reg
, 1);
935 r600_store_value(cb
, value
);
938 static INLINE
void eg_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
940 eg_store_loop_const_seq(cb
, reg
, 1);
941 r600_store_value(cb
, value
);
944 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
);
945 void r600_release_command_buffer(struct r600_command_buffer
*cb
);
947 static INLINE
void r600_write_compute_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
949 r600_write_context_reg_seq(cs
, reg
, num
);
950 /* Set the compute bit on the packet header */
951 cs
->buf
[cs
->cdw
- 2] |= RADEON_CP_PACKET3_COMPUTE_MODE
;
954 static INLINE
void r600_write_ctl_const_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
956 assert(reg
>= R600_CTL_CONST_OFFSET
);
957 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
958 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0);
959 cs
->buf
[cs
->cdw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
962 static INLINE
void r600_write_compute_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
964 r600_write_compute_context_reg_seq(cs
, reg
, 1);
965 radeon_emit(cs
, value
);
968 static INLINE
void r600_write_context_reg_flag(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
, unsigned flag
)
970 if (flag
& RADEON_CP_PACKET3_COMPUTE_MODE
) {
971 r600_write_compute_context_reg(cs
, reg
, value
);
973 r600_write_context_reg(cs
, reg
, value
);
977 static INLINE
void r600_write_ctl_const(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
979 r600_write_ctl_const_seq(cs
, reg
, 1);
980 radeon_emit(cs
, value
);
986 static INLINE
uint32_t S_FIXED(float value
, uint32_t frac_bits
)
988 return value
* (1 << frac_bits
);
990 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
992 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
994 if (filter
<= 1) return 0;
995 if (filter
<= 2) return 1;
996 if (filter
<= 4) return 2;
997 if (filter
<= 8) return 3;
1001 /* 12.4 fixed-point */
1002 static INLINE
unsigned r600_pack_float_12p4(float x
)
1005 x
>= 4096 ? 0xffff : x
* 16;