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2df168f01b53b53ef33ea510202f4bd9543e46bf
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "radeon/r600_pipe_common.h"
30 #include "radeon/r600_cs.h"
31
32 #include "r600_llvm.h"
33 #include "r600_public.h"
34
35 #include "util/u_suballoc.h"
36 #include "util/u_double_list.h"
37 #include "util/u_transfer.h"
38
39 #define R600_NUM_ATOMS 73
40
41 /* the number of CS dwords for flushing and drawing */
42 #define R600_MAX_FLUSH_CS_DWORDS 16
43 #define R600_MAX_DRAW_CS_DWORDS 40
44 #define R600_TRACE_CS_DWORDS 7
45
46 #define R600_MAX_USER_CONST_BUFFERS 13
47 #define R600_MAX_DRIVER_CONST_BUFFERS 4
48 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
49
50 /* start driver buffers after user buffers */
51 #define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
52 #define R600_TXQ_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
53 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
54 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 3)
55
56 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
57
58 #ifdef PIPE_ARCH_BIG_ENDIAN
59 #define R600_BIG_ENDIAN 1
60 #else
61 #define R600_BIG_ENDIAN 0
62 #endif
63
64 struct r600_context;
65 struct r600_bytecode;
66 struct r600_shader_key;
67
68 /* This is an atom containing GPU commands that never change.
69 * This is supposed to be copied directly into the CS. */
70 struct r600_command_buffer {
71 uint32_t *buf;
72 unsigned num_dw;
73 unsigned max_num_dw;
74 unsigned pkt_flags;
75 };
76
77 struct r600_db_state {
78 struct r600_atom atom;
79 struct r600_surface *rsurf;
80 };
81
82 struct r600_db_misc_state {
83 struct r600_atom atom;
84 bool occlusion_query_enabled;
85 bool flush_depthstencil_through_cb;
86 bool flush_depthstencil_in_place;
87 bool copy_depth, copy_stencil;
88 unsigned copy_sample;
89 unsigned log_samples;
90 unsigned db_shader_control;
91 bool htile_clear;
92 };
93
94 struct r600_cb_misc_state {
95 struct r600_atom atom;
96 unsigned cb_color_control; /* this comes from blend state */
97 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
98 unsigned nr_cbufs;
99 unsigned nr_ps_color_outputs;
100 bool multiwrite;
101 bool dual_src_blend;
102 };
103
104 struct r600_clip_misc_state {
105 struct r600_atom atom;
106 unsigned pa_cl_clip_cntl; /* from rasterizer */
107 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
108 unsigned clip_plane_enable; /* from rasterizer */
109 unsigned clip_dist_write; /* from vertex shader */
110 boolean clip_disable; /* from vertex shader */
111 };
112
113 struct r600_alphatest_state {
114 struct r600_atom atom;
115 unsigned sx_alpha_test_control; /* this comes from dsa state */
116 unsigned sx_alpha_ref; /* this comes from dsa state */
117 bool bypass;
118 bool cb0_export_16bpc; /* from set_framebuffer_state */
119 };
120
121 struct r600_vgt_state {
122 struct r600_atom atom;
123 uint32_t vgt_multi_prim_ib_reset_en;
124 uint32_t vgt_multi_prim_ib_reset_indx;
125 uint32_t vgt_indx_offset;
126 };
127
128 struct r600_blend_color {
129 struct r600_atom atom;
130 struct pipe_blend_color state;
131 };
132
133 struct r600_clip_state {
134 struct r600_atom atom;
135 struct pipe_clip_state state;
136 };
137
138 struct r600_cs_shader_state {
139 struct r600_atom atom;
140 unsigned kernel_index;
141 struct r600_pipe_compute *shader;
142 };
143
144 struct r600_framebuffer {
145 struct r600_atom atom;
146 struct pipe_framebuffer_state state;
147 unsigned compressed_cb_mask;
148 unsigned nr_samples;
149 bool export_16bpc;
150 bool cb0_is_integer;
151 bool is_msaa_resolve;
152 };
153
154 struct r600_sample_mask {
155 struct r600_atom atom;
156 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
157 };
158
159 struct r600_config_state {
160 struct r600_atom atom;
161 unsigned sq_gpr_resource_mgmt_1;
162 unsigned sq_gpr_resource_mgmt_2;
163 };
164
165 struct r600_stencil_ref
166 {
167 ubyte ref_value[2];
168 ubyte valuemask[2];
169 ubyte writemask[2];
170 };
171
172 struct r600_stencil_ref_state {
173 struct r600_atom atom;
174 struct r600_stencil_ref state;
175 struct pipe_stencil_ref pipe_state;
176 };
177
178 struct r600_viewport_state {
179 struct r600_atom atom;
180 struct pipe_viewport_state state;
181 int idx;
182 };
183
184 struct r600_shader_stages_state {
185 struct r600_atom atom;
186 unsigned geom_enable;
187 };
188
189 struct r600_gs_rings_state {
190 struct r600_atom atom;
191 unsigned enable;
192 struct pipe_constant_buffer esgs_ring;
193 struct pipe_constant_buffer gsvs_ring;
194 };
195
196 /* This must start from 16. */
197 /* features */
198 #define DBG_LLVM (1 << 29)
199 #define DBG_NO_CP_DMA (1 << 30)
200 /* shader backend */
201 #define DBG_NO_SB (1 << 21)
202 #define DBG_SB_CS (1 << 22)
203 #define DBG_SB_DRY_RUN (1 << 23)
204 #define DBG_SB_STAT (1 << 24)
205 #define DBG_SB_DUMP (1 << 25)
206 #define DBG_SB_NO_FALLBACK (1 << 26)
207 #define DBG_SB_DISASM (1 << 27)
208 #define DBG_SB_SAFEMATH (1 << 28)
209
210 struct r600_screen {
211 struct r600_common_screen b;
212 bool has_msaa;
213 bool has_compressed_msaa_texturing;
214
215 /*for compute global memory binding, we allocate stuff here, instead of
216 * buffers.
217 * XXX: Not sure if this is the best place for global_pool. Also,
218 * it's not thread safe, so it won't work with multiple contexts. */
219 struct compute_memory_pool *global_pool;
220 };
221
222 struct r600_pipe_sampler_view {
223 struct pipe_sampler_view base;
224 struct list_head list;
225 struct r600_resource *tex_resource;
226 uint32_t tex_resource_words[8];
227 bool skip_mip_address_reloc;
228 };
229
230 struct r600_rasterizer_state {
231 struct r600_command_buffer buffer;
232 boolean flatshade;
233 boolean two_side;
234 unsigned sprite_coord_enable;
235 unsigned clip_plane_enable;
236 unsigned pa_sc_line_stipple;
237 unsigned pa_cl_clip_cntl;
238 unsigned pa_su_sc_mode_cntl;
239 float offset_units;
240 float offset_scale;
241 bool offset_enable;
242 bool scissor_enable;
243 bool multisample_enable;
244 };
245
246 struct r600_poly_offset_state {
247 struct r600_atom atom;
248 enum pipe_format zs_format;
249 float offset_units;
250 float offset_scale;
251 };
252
253 struct r600_blend_state {
254 struct r600_command_buffer buffer;
255 struct r600_command_buffer buffer_no_blend;
256 unsigned cb_target_mask;
257 unsigned cb_color_control;
258 unsigned cb_color_control_no_blend;
259 bool dual_src_blend;
260 bool alpha_to_one;
261 };
262
263 struct r600_dsa_state {
264 struct r600_command_buffer buffer;
265 unsigned alpha_ref;
266 ubyte valuemask[2];
267 ubyte writemask[2];
268 unsigned zwritemask;
269 unsigned sx_alpha_test_control;
270 };
271
272 struct r600_pipe_shader;
273
274 struct r600_pipe_shader_selector {
275 struct r600_pipe_shader *current;
276
277 struct tgsi_token *tokens;
278 struct pipe_stream_output_info so;
279
280 unsigned num_shaders;
281
282 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
283 unsigned type;
284
285 unsigned nr_ps_max_color_exports;
286 };
287
288 struct r600_pipe_sampler_state {
289 uint32_t tex_sampler_words[3];
290 union pipe_color_union border_color;
291 bool border_color_use;
292 bool seamless_cube_map;
293 };
294
295 /* needed for blitter save */
296 #define NUM_TEX_UNITS 16
297
298 struct r600_seamless_cube_map {
299 struct r600_atom atom;
300 bool enabled;
301 };
302
303 struct r600_samplerview_state {
304 struct r600_atom atom;
305 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
306 uint32_t enabled_mask;
307 uint32_t dirty_mask;
308 uint32_t compressed_depthtex_mask; /* which textures are depth */
309 uint32_t compressed_colortex_mask;
310 boolean dirty_txq_constants;
311 boolean dirty_buffer_constants;
312 };
313
314 struct r600_sampler_states {
315 struct r600_atom atom;
316 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
317 uint32_t enabled_mask;
318 uint32_t dirty_mask;
319 uint32_t has_bordercolor_mask; /* which states contain the border color */
320 };
321
322 struct r600_textures_info {
323 struct r600_samplerview_state views;
324 struct r600_sampler_states states;
325 bool is_array_sampler[NUM_TEX_UNITS];
326
327 /* cube array txq workaround */
328 uint32_t *txq_constants;
329 /* buffer related workarounds */
330 uint32_t *buffer_constants;
331 };
332
333 struct r600_constbuf_state
334 {
335 struct r600_atom atom;
336 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
337 uint32_t enabled_mask;
338 uint32_t dirty_mask;
339 };
340
341 struct r600_vertexbuf_state
342 {
343 struct r600_atom atom;
344 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
345 uint32_t enabled_mask; /* non-NULL buffers */
346 uint32_t dirty_mask;
347 };
348
349 /* CSO (constant state object, in other words, immutable state). */
350 struct r600_cso_state
351 {
352 struct r600_atom atom;
353 void *cso; /* e.g. r600_blend_state */
354 struct r600_command_buffer *cb;
355 };
356
357 struct r600_scissor_state
358 {
359 struct r600_atom atom;
360 struct pipe_scissor_state scissor;
361 bool enable; /* r6xx only */
362 int idx;
363 };
364
365 struct r600_fetch_shader {
366 struct r600_resource *buffer;
367 unsigned offset;
368 };
369
370 struct r600_shader_state {
371 struct r600_atom atom;
372 struct r600_pipe_shader *shader;
373 };
374
375 struct r600_context {
376 struct r600_common_context b;
377 struct r600_screen *screen;
378 struct blitter_context *blitter;
379 struct u_suballocator *allocator_fetch_shader;
380
381 /* Hardware info. */
382 boolean has_vertex_cache;
383 boolean keep_tiling_flags;
384 unsigned default_ps_gprs, default_vs_gprs;
385 unsigned r6xx_num_clause_temp_gprs;
386
387 /* Miscellaneous state objects. */
388 void *custom_dsa_flush;
389 void *custom_blend_resolve;
390 void *custom_blend_decompress;
391 void *custom_blend_fastclear;
392 /* With rasterizer discard, there doesn't have to be a pixel shader.
393 * In that case, we bind this one: */
394 void *dummy_pixel_shader;
395 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
396 * bug where valid CMASK and FMASK are required to be present to avoid
397 * a hardlock in certain operations but aren't actually used
398 * for anything useful. */
399 struct r600_resource *dummy_fmask;
400 struct r600_resource *dummy_cmask;
401
402 /* State binding slots are here. */
403 struct r600_atom *atoms[R600_NUM_ATOMS];
404 /* States for CS initialization. */
405 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
406 /** Compute specific registers initializations. The start_cs_cmd atom
407 * must be emitted before start_compute_cs_cmd. */
408 struct r600_command_buffer start_compute_cs_cmd;
409 /* Register states. */
410 struct r600_alphatest_state alphatest_state;
411 struct r600_cso_state blend_state;
412 struct r600_blend_color blend_color;
413 struct r600_cb_misc_state cb_misc_state;
414 struct r600_clip_misc_state clip_misc_state;
415 struct r600_clip_state clip_state;
416 struct r600_db_misc_state db_misc_state;
417 struct r600_db_state db_state;
418 struct r600_cso_state dsa_state;
419 struct r600_framebuffer framebuffer;
420 struct r600_poly_offset_state poly_offset_state;
421 struct r600_cso_state rasterizer_state;
422 struct r600_sample_mask sample_mask;
423 struct r600_scissor_state scissor[16];
424 struct r600_seamless_cube_map seamless_cube_map;
425 struct r600_config_state config_state;
426 struct r600_stencil_ref_state stencil_ref;
427 struct r600_vgt_state vgt_state;
428 struct r600_viewport_state viewport[16];
429 /* Shaders and shader resources. */
430 struct r600_cso_state vertex_fetch_shader;
431 struct r600_shader_state vertex_shader;
432 struct r600_shader_state pixel_shader;
433 struct r600_shader_state geometry_shader;
434 struct r600_shader_state export_shader;
435 struct r600_cs_shader_state cs_shader_state;
436 struct r600_shader_stages_state shader_stages;
437 struct r600_gs_rings_state gs_rings;
438 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
439 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
440 /** Vertex buffers for fetch shaders */
441 struct r600_vertexbuf_state vertex_buffer_state;
442 /** Vertex buffers for compute shaders */
443 struct r600_vertexbuf_state cs_vertex_buffer_state;
444
445 /* Additional context states. */
446 unsigned compute_cb_target_mask;
447 struct r600_pipe_shader_selector *ps_shader;
448 struct r600_pipe_shader_selector *vs_shader;
449 struct r600_pipe_shader_selector *gs_shader;
450 struct r600_rasterizer_state *rasterizer;
451 bool alpha_to_one;
452 bool force_blend_disable;
453 boolean dual_src_blend;
454 unsigned zwritemask;
455
456 /* Index buffer. */
457 struct pipe_index_buffer index_buffer;
458
459 /* Last draw state (-1 = unset). */
460 int last_primitive_type; /* Last primitive type used in draw_vbo. */
461 int last_start_instance;
462
463 void *sb_context;
464 struct r600_isa *isa;
465 };
466
467 static INLINE void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
468 struct r600_command_buffer *cb)
469 {
470 assert(cs->cdw + cb->num_dw <= RADEON_MAX_CMDBUF_DWORDS);
471 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->num_dw);
472 cs->cdw += cb->num_dw;
473 }
474
475 void r600_trace_emit(struct r600_context *rctx);
476
477 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
478 {
479 atom->emit(&rctx->b, atom);
480 atom->dirty = false;
481 if (rctx->screen->b.trace_bo) {
482 r600_trace_emit(rctx);
483 }
484 }
485
486 static INLINE void r600_set_cso_state(struct r600_cso_state *state, void *cso)
487 {
488 state->cso = cso;
489 state->atom.dirty = cso != NULL;
490 }
491
492 static INLINE void r600_set_cso_state_with_cb(struct r600_cso_state *state, void *cso,
493 struct r600_command_buffer *cb)
494 {
495 state->cb = cb;
496 state->atom.num_dw = cb ? cb->num_dw : 0;
497 r600_set_cso_state(state, cso);
498 }
499
500 /* compute_memory_pool.c */
501 struct compute_memory_pool;
502 void compute_memory_pool_delete(struct compute_memory_pool* pool);
503 struct compute_memory_pool* compute_memory_pool_new(
504 struct r600_screen *rscreen);
505
506 /* evergreen_compute.c */
507 void evergreen_set_cs_sampler_view(struct pipe_context *ctx_,
508 unsigned start_slot, unsigned count,
509 struct pipe_sampler_view **views);
510
511 /* evergreen_state.c */
512 struct pipe_sampler_view *
513 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
514 struct pipe_resource *texture,
515 const struct pipe_sampler_view *state,
516 unsigned width0, unsigned height0,
517 unsigned force_level);
518 void evergreen_init_common_regs(struct r600_command_buffer *cb,
519 enum chip_class ctx_chip_class,
520 enum radeon_family ctx_family,
521 int ctx_drm_minor);
522 void cayman_init_common_regs(struct r600_command_buffer *cb,
523 enum chip_class ctx_chip_class,
524 enum radeon_family ctx_family,
525 int ctx_drm_minor);
526
527 void evergreen_init_state_functions(struct r600_context *rctx);
528 void evergreen_init_atom_start_cs(struct r600_context *rctx);
529 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
530 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
531 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
532 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
533 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
534 void *evergreen_create_resolve_blend(struct r600_context *rctx);
535 void *evergreen_create_decompress_blend(struct r600_context *rctx);
536 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
537 boolean evergreen_is_format_supported(struct pipe_screen *screen,
538 enum pipe_format format,
539 enum pipe_texture_target target,
540 unsigned sample_count,
541 unsigned usage);
542 void evergreen_init_color_surface(struct r600_context *rctx,
543 struct r600_surface *surf);
544 void evergreen_init_color_surface_rat(struct r600_context *rctx,
545 struct r600_surface *surf);
546 void evergreen_update_db_shader_control(struct r600_context * rctx);
547
548 /* r600_blit.c */
549 void r600_init_blit_functions(struct r600_context *rctx);
550 void r600_decompress_depth_textures(struct r600_context *rctx,
551 struct r600_samplerview_state *textures);
552 void r600_decompress_color_textures(struct r600_context *rctx,
553 struct r600_samplerview_state *textures);
554 void r600_resource_copy_region(struct pipe_context *ctx,
555 struct pipe_resource *dst,
556 unsigned dst_level,
557 unsigned dstx, unsigned dsty, unsigned dstz,
558 struct pipe_resource *src,
559 unsigned src_level,
560 const struct pipe_box *src_box);
561
562 /* r600_shader.c */
563 int r600_pipe_shader_create(struct pipe_context *ctx,
564 struct r600_pipe_shader *shader,
565 struct r600_shader_key key);
566
567 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
568
569 /* r600_state.c */
570 struct pipe_sampler_view *
571 r600_create_sampler_view_custom(struct pipe_context *ctx,
572 struct pipe_resource *texture,
573 const struct pipe_sampler_view *state,
574 unsigned width_first_level, unsigned height_first_level);
575 void r600_init_state_functions(struct r600_context *rctx);
576 void r600_init_atom_start_cs(struct r600_context *rctx);
577 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
578 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
579 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
580 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
581 void *r600_create_db_flush_dsa(struct r600_context *rctx);
582 void *r600_create_resolve_blend(struct r600_context *rctx);
583 void *r700_create_resolve_blend(struct r600_context *rctx);
584 void *r600_create_decompress_blend(struct r600_context *rctx);
585 bool r600_adjust_gprs(struct r600_context *rctx);
586 boolean r600_is_format_supported(struct pipe_screen *screen,
587 enum pipe_format format,
588 enum pipe_texture_target target,
589 unsigned sample_count,
590 unsigned usage);
591 void r600_update_db_shader_control(struct r600_context * rctx);
592
593 /* r600_hw_context.c */
594 void r600_context_gfx_flush(void *context, unsigned flags,
595 struct pipe_fence_handle **fence);
596 void r600_begin_new_cs(struct r600_context *ctx);
597 void r600_flush_emit(struct r600_context *ctx);
598 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
599 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
600 struct pipe_resource *dst, uint64_t dst_offset,
601 struct pipe_resource *src, uint64_t src_offset,
602 unsigned size);
603 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
604 struct pipe_resource *dst, uint64_t offset,
605 unsigned size, uint32_t clear_value);
606 void r600_dma_copy_buffer(struct r600_context *rctx,
607 struct pipe_resource *dst,
608 struct pipe_resource *src,
609 uint64_t dst_offset,
610 uint64_t src_offset,
611 uint64_t size);
612
613 /*
614 * evergreen_hw_context.c
615 */
616 void evergreen_dma_copy_buffer(struct r600_context *rctx,
617 struct pipe_resource *dst,
618 struct pipe_resource *src,
619 uint64_t dst_offset,
620 uint64_t src_offset,
621 uint64_t size);
622
623 /* r600_state_common.c */
624 void r600_init_common_state_functions(struct r600_context *rctx);
625 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
626 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
627 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
628 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
629 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
630 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
631 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom);
632 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
633 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
634 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
635 unsigned num_dw);
636 void r600_vertex_buffers_dirty(struct r600_context *rctx);
637 void r600_sampler_views_dirty(struct r600_context *rctx,
638 struct r600_samplerview_state *state);
639 void r600_sampler_states_dirty(struct r600_context *rctx,
640 struct r600_sampler_states *state);
641 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
642 uint32_t r600_translate_stencil_op(int s_op);
643 uint32_t r600_translate_fill(uint32_t func);
644 unsigned r600_tex_wrap(unsigned wrap);
645 unsigned r600_tex_filter(unsigned filter);
646 unsigned r600_tex_mipfilter(unsigned filter);
647 unsigned r600_tex_compare(unsigned compare);
648 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
649 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
650 struct pipe_resource *texture,
651 const struct pipe_surface *templ,
652 unsigned width, unsigned height);
653 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
654 const unsigned char *swizzle_view,
655 boolean vtx);
656 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
657 const unsigned char *swizzle_view,
658 uint32_t *word4_p, uint32_t *yuv_format_p);
659 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format);
660 uint32_t r600_colorformat_endian_swap(uint32_t colorformat);
661
662 /* r600_uvd.c */
663 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
664 const struct pipe_video_codec *decoder);
665
666 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
667 const struct pipe_video_buffer *tmpl);
668
669 /*
670 * Helpers for building command buffers
671 */
672
673 #define PKT3_SET_CONFIG_REG 0x68
674 #define PKT3_SET_CONTEXT_REG 0x69
675 #define PKT3_SET_CTL_CONST 0x6F
676 #define PKT3_SET_LOOP_CONST 0x6C
677
678 #define R600_CONFIG_REG_OFFSET 0x08000
679 #define R600_CONTEXT_REG_OFFSET 0x28000
680 #define R600_CTL_CONST_OFFSET 0x3CFF0
681 #define R600_LOOP_CONST_OFFSET 0X0003E200
682 #define EG_LOOP_CONST_OFFSET 0x0003A200
683
684 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
685 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
686 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
687 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
688 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
689
690 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
691
692 /*Evergreen Compute packet3*/
693 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
694
695 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
696 {
697 cb->buf[cb->num_dw++] = value;
698 }
699
700 static INLINE void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
701 {
702 assert(cb->num_dw+num <= cb->max_num_dw);
703 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
704 cb->num_dw += num;
705 }
706
707 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
708 {
709 assert(reg < R600_CONTEXT_REG_OFFSET);
710 assert(cb->num_dw+2+num <= cb->max_num_dw);
711 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
712 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
713 }
714
715 /**
716 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
717 * shaders.
718 */
719 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
720 {
721 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
722 assert(cb->num_dw+2+num <= cb->max_num_dw);
723 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
724 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
725 }
726
727 /**
728 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
729 * shaders.
730 */
731 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
732 {
733 assert(reg >= R600_CTL_CONST_OFFSET);
734 assert(cb->num_dw+2+num <= cb->max_num_dw);
735 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
736 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
737 }
738
739 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
740 {
741 assert(reg >= R600_LOOP_CONST_OFFSET);
742 assert(cb->num_dw+2+num <= cb->max_num_dw);
743 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
744 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
745 }
746
747 /**
748 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
749 * shaders.
750 */
751 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
752 {
753 assert(reg >= EG_LOOP_CONST_OFFSET);
754 assert(cb->num_dw+2+num <= cb->max_num_dw);
755 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
756 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
757 }
758
759 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
760 {
761 r600_store_config_reg_seq(cb, reg, 1);
762 r600_store_value(cb, value);
763 }
764
765 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
766 {
767 r600_store_context_reg_seq(cb, reg, 1);
768 r600_store_value(cb, value);
769 }
770
771 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
772 {
773 r600_store_ctl_const_seq(cb, reg, 1);
774 r600_store_value(cb, value);
775 }
776
777 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
778 {
779 r600_store_loop_const_seq(cb, reg, 1);
780 r600_store_value(cb, value);
781 }
782
783 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
784 {
785 eg_store_loop_const_seq(cb, reg, 1);
786 r600_store_value(cb, value);
787 }
788
789 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
790 void r600_release_command_buffer(struct r600_command_buffer *cb);
791
792 static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
793 {
794 r600_write_context_reg_seq(cs, reg, num);
795 /* Set the compute bit on the packet header */
796 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
797 }
798
799 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
800 {
801 assert(reg >= R600_CTL_CONST_OFFSET);
802 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
803 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
804 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
805 }
806
807 static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
808 {
809 r600_write_compute_context_reg_seq(cs, reg, 1);
810 radeon_emit(cs, value);
811 }
812
813 static INLINE void r600_write_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
814 {
815 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
816 r600_write_compute_context_reg(cs, reg, value);
817 } else {
818 r600_write_context_reg(cs, reg, value);
819 }
820 }
821
822 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
823 {
824 r600_write_ctl_const_seq(cs, reg, 1);
825 radeon_emit(cs, value);
826 }
827
828 /*
829 * common helpers
830 */
831 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
832 {
833 return value * (1 << frac_bits);
834 }
835 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
836
837 /* 12.4 fixed-point */
838 static INLINE unsigned r600_pack_float_12p4(float x)
839 {
840 return x <= 0 ? 0 :
841 x >= 4096 ? 0xffff : x * 16;
842 }
843
844 /* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */
845 static INLINE bool r600_can_read_depth(struct r600_texture *rtex)
846 {
847 return rtex->resource.b.b.nr_samples <= 1 &&
848 (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
849 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT);
850 }
851
852 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
853 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
854 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
855
856 static INLINE unsigned r600_conv_prim_to_gs_out(unsigned mode)
857 {
858 static const int prim_conv[] = {
859 V_028A6C_OUTPRIM_TYPE_POINTLIST,
860 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
861 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
862 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
863 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
864 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
865 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
866 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
867 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
868 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
869 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
870 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
871 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
872 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
873 V_028A6C_OUTPRIM_TYPE_TRISTRIP
874 };
875 assert(mode < Elements(prim_conv));
876
877 return prim_conv[mode];
878 }
879
880 #endif