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[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "radeon/r600_pipe_common.h"
30 #include "radeon/r600_cs.h"
31
32 #include "r600_llvm.h"
33 #include "r600_public.h"
34
35 #include "util/u_suballoc.h"
36 #include "util/u_double_list.h"
37 #include "util/u_transfer.h"
38
39 #define R600_NUM_ATOMS 73
40
41 /* the number of CS dwords for flushing and drawing */
42 #define R600_MAX_FLUSH_CS_DWORDS 16
43 #define R600_MAX_DRAW_CS_DWORDS 40
44 #define R600_TRACE_CS_DWORDS 7
45
46 #define R600_MAX_USER_CONST_BUFFERS 13
47 #define R600_MAX_DRIVER_CONST_BUFFERS 4
48 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
49
50 /* start driver buffers after user buffers */
51 #define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
52 #define R600_TXQ_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
53 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
54 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 3)
55 /* Currently R600_MAX_CONST_BUFFERS is too large, the hardware only has 16 buffers, but the driver is
56 * trying to use 17. Avoid accidentally aliasing with user UBOs for SAMPLE_POSITIONS by using an id<16.
57 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
58 *
59 * Fixing this properly would require the driver to combine its buffers into a single hardware buffer,
60 * which would also allow supporting the d3d 11 mandated minimum of 15 user const buffers.
61 */
62 #define R600_SAMPLE_POSITIONS_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
63
64 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
65
66 #ifdef PIPE_ARCH_BIG_ENDIAN
67 #define R600_BIG_ENDIAN 1
68 #else
69 #define R600_BIG_ENDIAN 0
70 #endif
71
72 struct r600_context;
73 struct r600_bytecode;
74 struct r600_shader_key;
75
76 /* This is an atom containing GPU commands that never change.
77 * This is supposed to be copied directly into the CS. */
78 struct r600_command_buffer {
79 uint32_t *buf;
80 unsigned num_dw;
81 unsigned max_num_dw;
82 unsigned pkt_flags;
83 };
84
85 struct r600_db_state {
86 struct r600_atom atom;
87 struct r600_surface *rsurf;
88 };
89
90 struct r600_db_misc_state {
91 struct r600_atom atom;
92 bool occlusion_query_enabled;
93 bool flush_depthstencil_through_cb;
94 bool flush_depthstencil_in_place;
95 bool copy_depth, copy_stencil;
96 unsigned copy_sample;
97 unsigned log_samples;
98 unsigned db_shader_control;
99 bool htile_clear;
100 };
101
102 struct r600_cb_misc_state {
103 struct r600_atom atom;
104 unsigned cb_color_control; /* this comes from blend state */
105 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
106 unsigned nr_cbufs;
107 unsigned nr_ps_color_outputs;
108 bool multiwrite;
109 bool dual_src_blend;
110 };
111
112 struct r600_clip_misc_state {
113 struct r600_atom atom;
114 unsigned pa_cl_clip_cntl; /* from rasterizer */
115 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
116 unsigned clip_plane_enable; /* from rasterizer */
117 unsigned clip_dist_write; /* from vertex shader */
118 boolean clip_disable; /* from vertex shader */
119 };
120
121 struct r600_alphatest_state {
122 struct r600_atom atom;
123 unsigned sx_alpha_test_control; /* this comes from dsa state */
124 unsigned sx_alpha_ref; /* this comes from dsa state */
125 bool bypass;
126 bool cb0_export_16bpc; /* from set_framebuffer_state */
127 };
128
129 struct r600_vgt_state {
130 struct r600_atom atom;
131 uint32_t vgt_multi_prim_ib_reset_en;
132 uint32_t vgt_multi_prim_ib_reset_indx;
133 uint32_t vgt_indx_offset;
134 };
135
136 struct r600_blend_color {
137 struct r600_atom atom;
138 struct pipe_blend_color state;
139 };
140
141 struct r600_clip_state {
142 struct r600_atom atom;
143 struct pipe_clip_state state;
144 };
145
146 struct r600_cs_shader_state {
147 struct r600_atom atom;
148 unsigned kernel_index;
149 unsigned pc;
150 struct r600_pipe_compute *shader;
151 };
152
153 struct r600_framebuffer {
154 struct r600_atom atom;
155 struct pipe_framebuffer_state state;
156 unsigned compressed_cb_mask;
157 unsigned nr_samples;
158 bool export_16bpc;
159 bool cb0_is_integer;
160 bool is_msaa_resolve;
161 };
162
163 struct r600_sample_mask {
164 struct r600_atom atom;
165 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
166 };
167
168 struct r600_config_state {
169 struct r600_atom atom;
170 unsigned sq_gpr_resource_mgmt_1;
171 unsigned sq_gpr_resource_mgmt_2;
172 };
173
174 struct r600_stencil_ref
175 {
176 ubyte ref_value[2];
177 ubyte valuemask[2];
178 ubyte writemask[2];
179 };
180
181 struct r600_stencil_ref_state {
182 struct r600_atom atom;
183 struct r600_stencil_ref state;
184 struct pipe_stencil_ref pipe_state;
185 };
186
187 struct r600_viewport_state {
188 struct r600_atom atom;
189 struct pipe_viewport_state state;
190 int idx;
191 };
192
193 struct r600_shader_stages_state {
194 struct r600_atom atom;
195 unsigned geom_enable;
196 };
197
198 struct r600_gs_rings_state {
199 struct r600_atom atom;
200 unsigned enable;
201 struct pipe_constant_buffer esgs_ring;
202 struct pipe_constant_buffer gsvs_ring;
203 };
204
205 /* This must start from 16. */
206 /* features */
207 #define DBG_LLVM (1 << 29)
208 #define DBG_NO_CP_DMA (1 << 30)
209 /* shader backend */
210 #define DBG_NO_SB (1 << 21)
211 #define DBG_SB_CS (1 << 22)
212 #define DBG_SB_DRY_RUN (1 << 23)
213 #define DBG_SB_STAT (1 << 24)
214 #define DBG_SB_DUMP (1 << 25)
215 #define DBG_SB_NO_FALLBACK (1 << 26)
216 #define DBG_SB_DISASM (1 << 27)
217 #define DBG_SB_SAFEMATH (1 << 28)
218
219 struct r600_screen {
220 struct r600_common_screen b;
221 bool has_msaa;
222 bool has_compressed_msaa_texturing;
223
224 /*for compute global memory binding, we allocate stuff here, instead of
225 * buffers.
226 * XXX: Not sure if this is the best place for global_pool. Also,
227 * it's not thread safe, so it won't work with multiple contexts. */
228 struct compute_memory_pool *global_pool;
229 };
230
231 struct r600_pipe_sampler_view {
232 struct pipe_sampler_view base;
233 struct list_head list;
234 struct r600_resource *tex_resource;
235 uint32_t tex_resource_words[8];
236 bool skip_mip_address_reloc;
237 };
238
239 struct r600_rasterizer_state {
240 struct r600_command_buffer buffer;
241 boolean flatshade;
242 boolean two_side;
243 unsigned sprite_coord_enable;
244 unsigned clip_plane_enable;
245 unsigned pa_sc_line_stipple;
246 unsigned pa_cl_clip_cntl;
247 unsigned pa_su_sc_mode_cntl;
248 float offset_units;
249 float offset_scale;
250 bool offset_enable;
251 bool scissor_enable;
252 bool multisample_enable;
253 };
254
255 struct r600_poly_offset_state {
256 struct r600_atom atom;
257 enum pipe_format zs_format;
258 float offset_units;
259 float offset_scale;
260 };
261
262 struct r600_blend_state {
263 struct r600_command_buffer buffer;
264 struct r600_command_buffer buffer_no_blend;
265 unsigned cb_target_mask;
266 unsigned cb_color_control;
267 unsigned cb_color_control_no_blend;
268 bool dual_src_blend;
269 bool alpha_to_one;
270 };
271
272 struct r600_dsa_state {
273 struct r600_command_buffer buffer;
274 unsigned alpha_ref;
275 ubyte valuemask[2];
276 ubyte writemask[2];
277 unsigned zwritemask;
278 unsigned sx_alpha_test_control;
279 };
280
281 struct r600_pipe_shader;
282
283 struct r600_pipe_shader_selector {
284 struct r600_pipe_shader *current;
285
286 struct tgsi_token *tokens;
287 struct pipe_stream_output_info so;
288
289 unsigned num_shaders;
290
291 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
292 unsigned type;
293
294 unsigned nr_ps_max_color_exports;
295 };
296
297 struct r600_pipe_sampler_state {
298 uint32_t tex_sampler_words[3];
299 union pipe_color_union border_color;
300 bool border_color_use;
301 bool seamless_cube_map;
302 };
303
304 /* needed for blitter save */
305 #define NUM_TEX_UNITS 16
306
307 struct r600_seamless_cube_map {
308 struct r600_atom atom;
309 bool enabled;
310 };
311
312 struct r600_samplerview_state {
313 struct r600_atom atom;
314 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
315 uint32_t enabled_mask;
316 uint32_t dirty_mask;
317 uint32_t compressed_depthtex_mask; /* which textures are depth */
318 uint32_t compressed_colortex_mask;
319 boolean dirty_txq_constants;
320 boolean dirty_buffer_constants;
321 };
322
323 struct r600_sampler_states {
324 struct r600_atom atom;
325 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
326 uint32_t enabled_mask;
327 uint32_t dirty_mask;
328 uint32_t has_bordercolor_mask; /* which states contain the border color */
329 };
330
331 struct r600_textures_info {
332 struct r600_samplerview_state views;
333 struct r600_sampler_states states;
334 bool is_array_sampler[NUM_TEX_UNITS];
335
336 /* cube array txq workaround */
337 uint32_t *txq_constants;
338 /* buffer related workarounds */
339 uint32_t *buffer_constants;
340 };
341
342 struct r600_constbuf_state
343 {
344 struct r600_atom atom;
345 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
346 uint32_t enabled_mask;
347 uint32_t dirty_mask;
348 };
349
350 struct r600_vertexbuf_state
351 {
352 struct r600_atom atom;
353 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
354 uint32_t enabled_mask; /* non-NULL buffers */
355 uint32_t dirty_mask;
356 };
357
358 /* CSO (constant state object, in other words, immutable state). */
359 struct r600_cso_state
360 {
361 struct r600_atom atom;
362 void *cso; /* e.g. r600_blend_state */
363 struct r600_command_buffer *cb;
364 };
365
366 struct r600_scissor_state
367 {
368 struct r600_atom atom;
369 struct pipe_scissor_state scissor;
370 bool enable; /* r6xx only */
371 int idx;
372 };
373
374 struct r600_fetch_shader {
375 struct r600_resource *buffer;
376 unsigned offset;
377 };
378
379 struct r600_shader_state {
380 struct r600_atom atom;
381 struct r600_pipe_shader *shader;
382 };
383
384 struct r600_context {
385 struct r600_common_context b;
386 struct r600_screen *screen;
387 struct blitter_context *blitter;
388 struct u_suballocator *allocator_fetch_shader;
389
390 /* Hardware info. */
391 boolean has_vertex_cache;
392 boolean keep_tiling_flags;
393 unsigned default_ps_gprs, default_vs_gprs;
394 unsigned r6xx_num_clause_temp_gprs;
395
396 /* Miscellaneous state objects. */
397 void *custom_dsa_flush;
398 void *custom_blend_resolve;
399 void *custom_blend_decompress;
400 void *custom_blend_fastclear;
401 /* With rasterizer discard, there doesn't have to be a pixel shader.
402 * In that case, we bind this one: */
403 void *dummy_pixel_shader;
404 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
405 * bug where valid CMASK and FMASK are required to be present to avoid
406 * a hardlock in certain operations but aren't actually used
407 * for anything useful. */
408 struct r600_resource *dummy_fmask;
409 struct r600_resource *dummy_cmask;
410
411 /* State binding slots are here. */
412 struct r600_atom *atoms[R600_NUM_ATOMS];
413 /* States for CS initialization. */
414 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
415 /** Compute specific registers initializations. The start_cs_cmd atom
416 * must be emitted before start_compute_cs_cmd. */
417 struct r600_command_buffer start_compute_cs_cmd;
418 /* Register states. */
419 struct r600_alphatest_state alphatest_state;
420 struct r600_cso_state blend_state;
421 struct r600_blend_color blend_color;
422 struct r600_cb_misc_state cb_misc_state;
423 struct r600_clip_misc_state clip_misc_state;
424 struct r600_clip_state clip_state;
425 struct r600_db_misc_state db_misc_state;
426 struct r600_db_state db_state;
427 struct r600_cso_state dsa_state;
428 struct r600_framebuffer framebuffer;
429 struct r600_poly_offset_state poly_offset_state;
430 struct r600_cso_state rasterizer_state;
431 struct r600_sample_mask sample_mask;
432 struct r600_scissor_state scissor[16];
433 struct r600_seamless_cube_map seamless_cube_map;
434 struct r600_config_state config_state;
435 struct r600_stencil_ref_state stencil_ref;
436 struct r600_vgt_state vgt_state;
437 struct r600_viewport_state viewport[16];
438 /* Shaders and shader resources. */
439 struct r600_cso_state vertex_fetch_shader;
440 struct r600_shader_state vertex_shader;
441 struct r600_shader_state pixel_shader;
442 struct r600_shader_state geometry_shader;
443 struct r600_shader_state export_shader;
444 struct r600_cs_shader_state cs_shader_state;
445 struct r600_shader_stages_state shader_stages;
446 struct r600_gs_rings_state gs_rings;
447 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
448 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
449 /** Vertex buffers for fetch shaders */
450 struct r600_vertexbuf_state vertex_buffer_state;
451 /** Vertex buffers for compute shaders */
452 struct r600_vertexbuf_state cs_vertex_buffer_state;
453
454 /* Additional context states. */
455 unsigned compute_cb_target_mask;
456 struct r600_pipe_shader_selector *ps_shader;
457 struct r600_pipe_shader_selector *vs_shader;
458 struct r600_pipe_shader_selector *gs_shader;
459 struct r600_rasterizer_state *rasterizer;
460 bool alpha_to_one;
461 bool force_blend_disable;
462 boolean dual_src_blend;
463 unsigned zwritemask;
464 int ps_iter_samples;
465
466 /* Index buffer. */
467 struct pipe_index_buffer index_buffer;
468
469 /* Last draw state (-1 = unset). */
470 int last_primitive_type; /* Last primitive type used in draw_vbo. */
471 int last_start_instance;
472
473 void *sb_context;
474 struct r600_isa *isa;
475 };
476
477 static INLINE void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
478 struct r600_command_buffer *cb)
479 {
480 assert(cs->cdw + cb->num_dw <= RADEON_MAX_CMDBUF_DWORDS);
481 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->num_dw);
482 cs->cdw += cb->num_dw;
483 }
484
485 void r600_trace_emit(struct r600_context *rctx);
486
487 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
488 {
489 atom->emit(&rctx->b, atom);
490 atom->dirty = false;
491 if (rctx->screen->b.trace_bo) {
492 r600_trace_emit(rctx);
493 }
494 }
495
496 static INLINE void r600_set_cso_state(struct r600_cso_state *state, void *cso)
497 {
498 state->cso = cso;
499 state->atom.dirty = cso != NULL;
500 }
501
502 static INLINE void r600_set_cso_state_with_cb(struct r600_cso_state *state, void *cso,
503 struct r600_command_buffer *cb)
504 {
505 state->cb = cb;
506 state->atom.num_dw = cb ? cb->num_dw : 0;
507 r600_set_cso_state(state, cso);
508 }
509
510 /* compute_memory_pool.c */
511 struct compute_memory_pool;
512 void compute_memory_pool_delete(struct compute_memory_pool* pool);
513 struct compute_memory_pool* compute_memory_pool_new(
514 struct r600_screen *rscreen);
515
516 /* evergreen_compute.c */
517 void evergreen_set_cs_sampler_view(struct pipe_context *ctx_,
518 unsigned start_slot, unsigned count,
519 struct pipe_sampler_view **views);
520
521 /* evergreen_state.c */
522 struct pipe_sampler_view *
523 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
524 struct pipe_resource *texture,
525 const struct pipe_sampler_view *state,
526 unsigned width0, unsigned height0,
527 unsigned force_level);
528 void evergreen_init_common_regs(struct r600_command_buffer *cb,
529 enum chip_class ctx_chip_class,
530 enum radeon_family ctx_family,
531 int ctx_drm_minor);
532 void cayman_init_common_regs(struct r600_command_buffer *cb,
533 enum chip_class ctx_chip_class,
534 enum radeon_family ctx_family,
535 int ctx_drm_minor);
536
537 void evergreen_init_state_functions(struct r600_context *rctx);
538 void evergreen_init_atom_start_cs(struct r600_context *rctx);
539 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
540 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
541 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
542 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
543 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
544 void *evergreen_create_resolve_blend(struct r600_context *rctx);
545 void *evergreen_create_decompress_blend(struct r600_context *rctx);
546 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
547 boolean evergreen_is_format_supported(struct pipe_screen *screen,
548 enum pipe_format format,
549 enum pipe_texture_target target,
550 unsigned sample_count,
551 unsigned usage);
552 void evergreen_init_color_surface(struct r600_context *rctx,
553 struct r600_surface *surf);
554 void evergreen_init_color_surface_rat(struct r600_context *rctx,
555 struct r600_surface *surf);
556 void evergreen_update_db_shader_control(struct r600_context * rctx);
557
558 /* r600_blit.c */
559 void r600_init_blit_functions(struct r600_context *rctx);
560 void r600_decompress_depth_textures(struct r600_context *rctx,
561 struct r600_samplerview_state *textures);
562 void r600_decompress_color_textures(struct r600_context *rctx,
563 struct r600_samplerview_state *textures);
564 void r600_resource_copy_region(struct pipe_context *ctx,
565 struct pipe_resource *dst,
566 unsigned dst_level,
567 unsigned dstx, unsigned dsty, unsigned dstz,
568 struct pipe_resource *src,
569 unsigned src_level,
570 const struct pipe_box *src_box);
571
572 /* r600_shader.c */
573 int r600_pipe_shader_create(struct pipe_context *ctx,
574 struct r600_pipe_shader *shader,
575 struct r600_shader_key key);
576
577 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
578
579 /* r600_state.c */
580 struct pipe_sampler_view *
581 r600_create_sampler_view_custom(struct pipe_context *ctx,
582 struct pipe_resource *texture,
583 const struct pipe_sampler_view *state,
584 unsigned width_first_level, unsigned height_first_level);
585 void r600_init_state_functions(struct r600_context *rctx);
586 void r600_init_atom_start_cs(struct r600_context *rctx);
587 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
588 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
589 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
590 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
591 void *r600_create_db_flush_dsa(struct r600_context *rctx);
592 void *r600_create_resolve_blend(struct r600_context *rctx);
593 void *r700_create_resolve_blend(struct r600_context *rctx);
594 void *r600_create_decompress_blend(struct r600_context *rctx);
595 bool r600_adjust_gprs(struct r600_context *rctx);
596 boolean r600_is_format_supported(struct pipe_screen *screen,
597 enum pipe_format format,
598 enum pipe_texture_target target,
599 unsigned sample_count,
600 unsigned usage);
601 void r600_update_db_shader_control(struct r600_context * rctx);
602
603 /* r600_hw_context.c */
604 void r600_context_gfx_flush(void *context, unsigned flags,
605 struct pipe_fence_handle **fence);
606 void r600_begin_new_cs(struct r600_context *ctx);
607 void r600_flush_emit(struct r600_context *ctx);
608 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
609 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
610 struct pipe_resource *dst, uint64_t dst_offset,
611 struct pipe_resource *src, uint64_t src_offset,
612 unsigned size);
613 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
614 struct pipe_resource *dst, uint64_t offset,
615 unsigned size, uint32_t clear_value);
616 void r600_dma_copy_buffer(struct r600_context *rctx,
617 struct pipe_resource *dst,
618 struct pipe_resource *src,
619 uint64_t dst_offset,
620 uint64_t src_offset,
621 uint64_t size);
622
623 /*
624 * evergreen_hw_context.c
625 */
626 void evergreen_dma_copy_buffer(struct r600_context *rctx,
627 struct pipe_resource *dst,
628 struct pipe_resource *src,
629 uint64_t dst_offset,
630 uint64_t src_offset,
631 uint64_t size);
632
633 /* r600_state_common.c */
634 void r600_init_common_state_functions(struct r600_context *rctx);
635 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
636 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
637 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
638 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
639 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
640 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
641 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom);
642 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
643 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
644 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
645 unsigned num_dw);
646 void r600_vertex_buffers_dirty(struct r600_context *rctx);
647 void r600_sampler_views_dirty(struct r600_context *rctx,
648 struct r600_samplerview_state *state);
649 void r600_sampler_states_dirty(struct r600_context *rctx,
650 struct r600_sampler_states *state);
651 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
652 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
653 uint32_t r600_translate_stencil_op(int s_op);
654 uint32_t r600_translate_fill(uint32_t func);
655 unsigned r600_tex_wrap(unsigned wrap);
656 unsigned r600_tex_filter(unsigned filter);
657 unsigned r600_tex_mipfilter(unsigned filter);
658 unsigned r600_tex_compare(unsigned compare);
659 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
660 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
661 struct pipe_resource *texture,
662 const struct pipe_surface *templ,
663 unsigned width, unsigned height);
664 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
665 const unsigned char *swizzle_view,
666 boolean vtx);
667 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
668 const unsigned char *swizzle_view,
669 uint32_t *word4_p, uint32_t *yuv_format_p);
670 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format);
671 uint32_t r600_colorformat_endian_swap(uint32_t colorformat);
672
673 /* r600_uvd.c */
674 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
675 const struct pipe_video_codec *decoder);
676
677 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
678 const struct pipe_video_buffer *tmpl);
679
680 /*
681 * Helpers for building command buffers
682 */
683
684 #define PKT3_SET_CONFIG_REG 0x68
685 #define PKT3_SET_CONTEXT_REG 0x69
686 #define PKT3_SET_CTL_CONST 0x6F
687 #define PKT3_SET_LOOP_CONST 0x6C
688
689 #define R600_CONFIG_REG_OFFSET 0x08000
690 #define R600_CONTEXT_REG_OFFSET 0x28000
691 #define R600_CTL_CONST_OFFSET 0x3CFF0
692 #define R600_LOOP_CONST_OFFSET 0X0003E200
693 #define EG_LOOP_CONST_OFFSET 0x0003A200
694
695 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
696 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
697 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
698 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
699 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
700
701 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
702
703 /*Evergreen Compute packet3*/
704 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
705
706 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
707 {
708 cb->buf[cb->num_dw++] = value;
709 }
710
711 static INLINE void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
712 {
713 assert(cb->num_dw+num <= cb->max_num_dw);
714 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
715 cb->num_dw += num;
716 }
717
718 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
719 {
720 assert(reg < R600_CONTEXT_REG_OFFSET);
721 assert(cb->num_dw+2+num <= cb->max_num_dw);
722 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
723 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
724 }
725
726 /**
727 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
728 * shaders.
729 */
730 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
731 {
732 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
733 assert(cb->num_dw+2+num <= cb->max_num_dw);
734 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
735 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
736 }
737
738 /**
739 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
740 * shaders.
741 */
742 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
743 {
744 assert(reg >= R600_CTL_CONST_OFFSET);
745 assert(cb->num_dw+2+num <= cb->max_num_dw);
746 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
747 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
748 }
749
750 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
751 {
752 assert(reg >= R600_LOOP_CONST_OFFSET);
753 assert(cb->num_dw+2+num <= cb->max_num_dw);
754 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
755 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
756 }
757
758 /**
759 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
760 * shaders.
761 */
762 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
763 {
764 assert(reg >= EG_LOOP_CONST_OFFSET);
765 assert(cb->num_dw+2+num <= cb->max_num_dw);
766 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
767 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
768 }
769
770 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
771 {
772 r600_store_config_reg_seq(cb, reg, 1);
773 r600_store_value(cb, value);
774 }
775
776 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
777 {
778 r600_store_context_reg_seq(cb, reg, 1);
779 r600_store_value(cb, value);
780 }
781
782 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
783 {
784 r600_store_ctl_const_seq(cb, reg, 1);
785 r600_store_value(cb, value);
786 }
787
788 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
789 {
790 r600_store_loop_const_seq(cb, reg, 1);
791 r600_store_value(cb, value);
792 }
793
794 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
795 {
796 eg_store_loop_const_seq(cb, reg, 1);
797 r600_store_value(cb, value);
798 }
799
800 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
801 void r600_release_command_buffer(struct r600_command_buffer *cb);
802
803 static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
804 {
805 r600_write_context_reg_seq(cs, reg, num);
806 /* Set the compute bit on the packet header */
807 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
808 }
809
810 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
811 {
812 assert(reg >= R600_CTL_CONST_OFFSET);
813 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
814 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
815 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
816 }
817
818 static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
819 {
820 r600_write_compute_context_reg_seq(cs, reg, 1);
821 radeon_emit(cs, value);
822 }
823
824 static INLINE void r600_write_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
825 {
826 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
827 r600_write_compute_context_reg(cs, reg, value);
828 } else {
829 r600_write_context_reg(cs, reg, value);
830 }
831 }
832
833 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
834 {
835 r600_write_ctl_const_seq(cs, reg, 1);
836 radeon_emit(cs, value);
837 }
838
839 /*
840 * common helpers
841 */
842 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
843 {
844 return value * (1 << frac_bits);
845 }
846 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
847
848 /* 12.4 fixed-point */
849 static INLINE unsigned r600_pack_float_12p4(float x)
850 {
851 return x <= 0 ? 0 :
852 x >= 4096 ? 0xffff : x * 16;
853 }
854
855 /* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */
856 static INLINE bool r600_can_read_depth(struct r600_texture *rtex)
857 {
858 return rtex->resource.b.b.nr_samples <= 1 &&
859 (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
860 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT);
861 }
862
863 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
864 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
865 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
866
867 static INLINE unsigned r600_conv_prim_to_gs_out(unsigned mode)
868 {
869 static const int prim_conv[] = {
870 V_028A6C_OUTPRIM_TYPE_POINTLIST,
871 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
872 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
873 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
874 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
875 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
876 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
877 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
878 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
879 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
880 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
881 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
882 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
883 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
884 V_028A6C_OUTPRIM_TYPE_TRISTRIP
885 };
886 assert(mode < Elements(prim_conv));
887
888 return prim_conv[mode];
889 }
890
891 #endif