2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "util/u_blitter.h"
30 #include "util/u_slab.h"
32 #include "r600_llvm.h"
33 #include "r600_public.h"
34 #include "r600_shader.h"
35 #include "r600_resource.h"
36 #include "evergreen_compute.h"
38 #define R600_NUM_ATOMS 24
40 #define R600_MAX_CONST_BUFFERS 2
41 #define R600_MAX_CONST_BUFFER_SIZE 4096
43 #ifdef PIPE_ARCH_BIG_ENDIAN
44 #define R600_BIG_ENDIAN 1
46 #define R600_BIG_ENDIAN 0
49 /* This encapsulates a state or an operation which can emitted into the GPU
50 * command stream. It's not limited to states only, it can be used for anything
51 * that wants to write commands into the CS (e.g. cache flushes). */
53 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
);
59 /* This is an atom containing GPU commands that never change.
60 * This is supposed to be copied directly into the CS. */
61 struct r600_command_buffer
{
62 struct r600_atom atom
;
68 struct r600_db_misc_state
{
69 struct r600_atom atom
;
70 bool occlusion_query_enabled
;
71 bool flush_depthstencil_through_cb
;
72 bool copy_depth
, copy_stencil
;
77 struct r600_cb_misc_state
{
78 struct r600_atom atom
;
79 unsigned cb_color_control
; /* this comes from blend state */
80 unsigned blend_colormask
; /* 8*4 bits for 8 RGBA colorbuffers */
82 unsigned nr_ps_color_outputs
;
87 struct r600_alphatest_state
{
88 struct r600_atom atom
;
89 unsigned sx_alpha_test_control
; /* this comes from dsa state */
90 unsigned sx_alpha_ref
; /* this comes from dsa state */
92 bool cb0_export_16bpc
; /* from set_framebuffer_state */
95 struct r600_blend_color
{
96 struct r600_atom atom
;
97 struct pipe_blend_color state
;
100 struct r600_clip_state
{
101 struct r600_atom atom
;
102 struct pipe_clip_state state
;
105 struct r600_cs_shader_state
{
106 struct r600_atom atom
;
107 struct r600_pipe_compute
*shader
;
110 struct r600_sample_mask
{
111 struct r600_atom atom
;
112 uint16_t sample_mask
; /* there are only 8 bits on EG, 16 bits on Cayman */
115 struct r600_stencil_ref
122 struct r600_stencil_ref_state
{
123 struct r600_atom atom
;
124 struct r600_stencil_ref state
;
125 struct pipe_stencil_ref pipe_state
;
128 struct r600_viewport_state
{
129 struct r600_atom atom
;
130 struct pipe_viewport_state state
;
133 enum r600_pipe_state_id
{
134 R600_PIPE_STATE_BLEND
= 0,
135 R600_PIPE_STATE_SCISSOR
,
136 R600_PIPE_STATE_RASTERIZER
,
138 R600_PIPE_STATE_FRAMEBUFFER
,
140 R600_PIPE_STATE_POLYGON_OFFSET
,
141 R600_PIPE_STATE_FETCH_SHADER
,
145 struct compute_memory_pool
;
146 void compute_memory_pool_delete(struct compute_memory_pool
* pool
);
147 struct compute_memory_pool
* compute_memory_pool_new(
148 struct r600_screen
*rscreen
);
150 struct r600_pipe_fences
{
151 struct r600_resource
*bo
;
154 /* linked list of preallocated blocks */
155 struct list_head blocks
;
156 /* linked list of freed fences */
157 struct list_head pool
;
162 struct pipe_screen screen
;
163 struct radeon_winsys
*ws
;
165 enum chip_class chip_class
;
166 struct radeon_info info
;
168 struct r600_tiling_info tiling_info
;
169 struct r600_pipe_fences fences
;
171 /*for compute global memory binding, we allocate stuff here, instead of
173 * XXX: Not sure if this is the best place for global_pool. Also,
174 * it's not thread safe, so it won't work with multiple contexts. */
175 struct compute_memory_pool
*global_pool
;
178 struct r600_pipe_sampler_view
{
179 struct pipe_sampler_view base
;
180 struct r600_resource
*tex_resource
;
181 uint32_t tex_resource_words
[8];
184 struct r600_pipe_rasterizer
{
185 struct r600_pipe_state rstate
;
188 unsigned sprite_coord_enable
;
189 unsigned clip_plane_enable
;
190 unsigned pa_sc_line_stipple
;
191 unsigned pa_cl_clip_cntl
;
195 bool multisample_enable
;
198 struct r600_pipe_blend
{
199 struct r600_pipe_state rstate
;
200 unsigned cb_target_mask
;
201 unsigned cb_color_control
;
206 struct r600_pipe_dsa
{
207 struct r600_pipe_state rstate
;
211 unsigned sx_alpha_test_control
;
214 struct r600_vertex_element
217 struct pipe_vertex_element elements
[PIPE_MAX_ATTRIBS
];
218 struct r600_resource
*fetch_shader
;
220 struct r600_pipe_state rstate
;
223 struct r600_pipe_shader
;
225 struct r600_pipe_shader_selector
{
226 struct r600_pipe_shader
*current
;
228 struct tgsi_token
*tokens
;
229 struct pipe_stream_output_info so
;
231 unsigned num_shaders
;
233 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
236 unsigned nr_ps_max_color_exports
;
239 struct r600_pipe_shader
{
240 struct r600_pipe_shader_selector
*selector
;
241 struct r600_pipe_shader
*next_variant
;
242 struct r600_shader shader
;
243 struct r600_pipe_state rstate
;
244 struct r600_resource
*bo
;
245 struct r600_resource
*bo_fetch
;
246 struct r600_vertex_element vertex_elements
;
247 unsigned sprite_coord_enable
;
249 unsigned pa_cl_vs_out_cntl
;
250 unsigned nr_ps_color_outputs
;
252 unsigned db_shader_control
;
253 unsigned ps_depth_export
;
256 struct r600_pipe_sampler_state
{
257 uint32_t tex_sampler_words
[3];
258 uint32_t border_color
[4];
259 bool border_color_use
;
260 bool seamless_cube_map
;
263 /* needed for blitter save */
264 #define NUM_TEX_UNITS 16
266 struct r600_seamless_cube_map
{
267 struct r600_atom atom
;
271 struct r600_samplerview_state
{
272 struct r600_atom atom
;
273 struct r600_pipe_sampler_view
*views
[NUM_TEX_UNITS
];
274 uint32_t enabled_mask
;
276 uint32_t compressed_depthtex_mask
; /* which textures are depth */
277 uint32_t compressed_colortex_mask
;
280 struct r600_sampler_states
{
281 struct r600_atom atom
;
282 struct r600_pipe_sampler_state
*states
[NUM_TEX_UNITS
];
283 uint32_t enabled_mask
;
285 uint32_t has_bordercolor_mask
; /* which states contain the border color */
288 struct r600_textures_info
{
289 struct r600_samplerview_state views
;
290 struct r600_sampler_states states
;
291 bool is_array_sampler
[NUM_TEX_UNITS
];
295 struct pipe_reference reference
;
296 unsigned index
; /* in the shared bo */
297 struct r600_resource
*sleep_bo
;
298 struct list_head head
;
301 #define FENCE_BLOCK_SIZE 16
303 struct r600_fence_block
{
304 struct r600_fence fences
[FENCE_BLOCK_SIZE
];
305 struct list_head head
;
308 #define R600_CONSTANT_ARRAY_SIZE 256
309 #define R600_RESOURCE_ARRAY_SIZE 160
311 struct r600_constbuf_state
313 struct r600_atom atom
;
314 struct pipe_constant_buffer cb
[PIPE_MAX_CONSTANT_BUFFERS
];
315 uint32_t enabled_mask
;
319 struct r600_vertexbuf_state
321 struct r600_atom atom
;
322 struct pipe_vertex_buffer vb
[PIPE_MAX_ATTRIBS
];
323 uint32_t enabled_mask
; /* non-NULL buffers */
327 struct r600_context
{
328 struct pipe_context context
;
329 struct blitter_context
*blitter
;
330 enum radeon_family family
;
331 enum chip_class chip_class
;
332 boolean has_vertex_cache
;
333 unsigned r6xx_num_clause_temp_gprs
;
334 void *custom_dsa_flush
;
335 void *custom_blend_resolve
;
336 void *custom_blend_decompress
;
338 struct r600_screen
*screen
;
339 struct radeon_winsys
*ws
;
340 struct r600_pipe_state
*states
[R600_PIPE_NSTATES
];
341 struct r600_vertex_element
*vertex_elements
;
342 struct pipe_framebuffer_state framebuffer
;
343 unsigned compressed_cb_mask
;
344 unsigned compute_cb_target_mask
;
345 unsigned db_shader_control
;
346 unsigned pa_sc_line_stipple
;
347 unsigned pa_cl_clip_cntl
;
348 /* for saving when using blitter */
349 struct r600_pipe_shader_selector
*ps_shader
;
350 struct r600_pipe_shader_selector
*vs_shader
;
351 struct r600_pipe_rasterizer
*rasterizer
;
352 struct r600_pipe_state vgt
;
353 struct r600_pipe_state spi
;
354 struct pipe_query
*current_render_cond
;
355 unsigned current_render_cond_mode
;
356 struct pipe_query
*saved_render_cond
;
357 unsigned saved_render_cond_mode
;
358 /* shader information */
361 unsigned sprite_coord_enable
;
363 boolean export_16bpc
;
366 bool multisample_enable
;
369 struct u_upload_mgr
*uploader
;
370 struct util_slab_mempool pool_transfers
;
372 unsigned default_ps_gprs
, default_vs_gprs
;
374 /******************************/
375 /* States based on r600_atom. */
376 struct r600_atom
*atoms
[R600_NUM_ATOMS
];
377 /* States for CS initialization. */
378 struct r600_command_buffer start_cs_cmd
; /* invariant state mostly */
379 /** Compute specific registers initializations. The start_cs_cmd atom
380 * must be emitted before start_compute_cs_cmd. */
381 struct r600_command_buffer start_compute_cs_cmd
;
382 /* Register states. */
383 struct r600_alphatest_state alphatest_state
;
384 struct r600_blend_color blend_color
;
385 struct r600_cb_misc_state cb_misc_state
;
386 struct r600_clip_state clip_state
;
387 struct r600_db_misc_state db_misc_state
;
388 struct r600_seamless_cube_map seamless_cube_map
;
389 struct r600_stencil_ref_state stencil_ref
;
390 struct r600_sample_mask sample_mask
;
391 struct r600_viewport_state viewport
;
392 /* Shaders and shader resources. */
393 struct r600_cs_shader_state cs_shader_state
;
394 struct r600_constbuf_state constbuf_state
[PIPE_SHADER_TYPES
];
395 struct r600_textures_info samplers
[PIPE_SHADER_TYPES
];
396 /** Vertex buffers for fetch shaders */
397 struct r600_vertexbuf_state vertex_buffer_state
;
398 /** Vertex buffers for compute shaders */
399 struct r600_vertexbuf_state cs_vertex_buffer_state
;
400 /******************************/
402 /* current external blend state (from state tracker) */
403 struct r600_pipe_blend
*blend
;
404 /* state with disabled blending - used internally with blend_override */
405 struct r600_pipe_blend
*no_blend
;
407 /* 1 - override current blend state with no_blend, 0 - use external state */
408 unsigned blend_override
;
410 struct radeon_winsys_cs
*cs
;
412 struct r600_range
*range
;
414 struct r600_block
**blocks
;
415 struct list_head dirty
;
416 struct list_head enable_list
;
417 unsigned pm4_dirty_cdwords
;
418 unsigned ctx_pm4_ndwords
;
420 /* The list of active queries. Only one query of each type can be active. */
421 int num_occlusion_queries
;
423 /* Manage queries in two separate groups:
424 * The timer ones and the others (streamout, occlusion).
426 * We do this because we should only suspend non-timer queries for u_blitter,
427 * and later if the non-timer queries are suspended, the context flush should
428 * only suspend and resume the timer queries. */
429 struct list_head active_timer_queries
;
430 unsigned num_cs_dw_timer_queries_suspend
;
431 struct list_head active_nontimer_queries
;
432 unsigned num_cs_dw_nontimer_queries_suspend
;
434 bool timer_queries_suspended
;
435 bool nontimer_queries_suspended
;
436 bool streamout_suspended
;
438 unsigned num_cs_dw_streamout_end
;
440 unsigned backend_mask
;
441 unsigned max_db
; /* for OQ */
443 boolean predicate_drawing
;
445 unsigned num_so_targets
;
446 struct r600_so_target
*so_targets
[PIPE_MAX_SO_BUFFERS
];
447 boolean streamout_start
;
448 unsigned streamout_append_bitmask
;
450 /* There is no scissor enable bit on r6xx, so we must use a workaround.
451 * These track the current scissor state. */
453 struct pipe_scissor_state scissor_state
;
455 /* With rasterizer discard, there doesn't have to be a pixel shader.
456 * In that case, we bind this one: */
457 void *dummy_pixel_shader
;
459 boolean dual_src_blend
;
462 struct pipe_index_buffer index_buffer
;
464 /* Dummy CMASK and FMASK buffers used to get around the R6xx hardware
465 * bug where valid CMASK and FMASK are required to be present to avoid
466 * a hardlock in certain operations but aren't actually used
467 * for anything useful. */
468 struct r600_resource
*dummy_fmask
;
469 struct r600_resource
*dummy_cmask
;
472 static INLINE
void r600_emit_atom(struct r600_context
*rctx
, struct r600_atom
*atom
)
474 atom
->emit(rctx
, atom
);
478 static INLINE
void r600_atom_dirty(struct r600_context
*rctx
, struct r600_atom
*state
)
483 /* evergreen_state.c */
484 void evergreen_init_common_regs(struct r600_command_buffer
*cb
,
485 enum chip_class ctx_chip_class
,
486 enum radeon_family ctx_family
,
489 void evergreen_init_state_functions(struct r600_context
*rctx
);
490 void evergreen_init_atom_start_cs(struct r600_context
*rctx
);
491 void evergreen_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
492 void evergreen_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
493 void evergreen_fetch_shader(struct pipe_context
*ctx
, struct r600_vertex_element
*ve
);
494 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
);
495 void *evergreen_create_resolve_blend(struct r600_context
*rctx
);
496 void *evergreen_create_decompress_blend(struct r600_context
*rctx
);
497 void evergreen_polygon_offset_update(struct r600_context
*rctx
);
498 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
499 enum pipe_format format
,
500 enum pipe_texture_target target
,
501 unsigned sample_count
,
503 void evergreen_init_color_surface(struct r600_context
*rctx
,
504 struct r600_surface
*surf
);
505 void evergreen_update_dual_export_state(struct r600_context
* rctx
);
508 void r600_copy_buffer(struct pipe_context
*ctx
, struct
509 pipe_resource
*dst
, unsigned dstx
,
510 struct pipe_resource
*src
, const struct pipe_box
*src_box
);
511 void r600_init_blit_functions(struct r600_context
*rctx
);
512 void r600_blit_decompress_depth(struct pipe_context
*ctx
,
513 struct r600_texture
*texture
,
514 struct r600_texture
*staging
,
515 unsigned first_level
, unsigned last_level
,
516 unsigned first_layer
, unsigned last_layer
,
517 unsigned first_sample
, unsigned last_sample
);
518 void r600_decompress_depth_textures(struct r600_context
*rctx
,
519 struct r600_samplerview_state
*textures
);
520 void r600_decompress_color_textures(struct r600_context
*rctx
,
521 struct r600_samplerview_state
*textures
);
524 bool r600_init_resource(struct r600_screen
*rscreen
,
525 struct r600_resource
*res
,
526 unsigned size
, unsigned alignment
,
527 unsigned bind
, unsigned usage
);
528 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
529 const struct pipe_resource
*templ
,
533 void r600_flush(struct pipe_context
*ctx
, struct pipe_fence_handle
**fence
,
537 void r600_init_query_functions(struct r600_context
*rctx
);
538 void r600_suspend_nontimer_queries(struct r600_context
*ctx
);
539 void r600_resume_nontimer_queries(struct r600_context
*ctx
);
540 void r600_suspend_timer_queries(struct r600_context
*ctx
);
541 void r600_resume_timer_queries(struct r600_context
*ctx
);
543 /* r600_resource.c */
544 void r600_init_context_resource_functions(struct r600_context
*r600
);
547 int r600_pipe_shader_create(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
549 int r600_compute_shader_create(struct pipe_context
* ctx
,
550 LLVMModuleRef mod
, struct r600_bytecode
* bytecode
);
552 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
555 void r600_set_scissor_state(struct r600_context
*rctx
,
556 const struct pipe_scissor_state
*state
);
557 void r600_init_state_functions(struct r600_context
*rctx
);
558 void r600_init_atom_start_cs(struct r600_context
*rctx
);
559 void r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
560 void r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
561 void r600_fetch_shader(struct pipe_context
*ctx
, struct r600_vertex_element
*ve
);
562 void *r600_create_db_flush_dsa(struct r600_context
*rctx
);
563 void *r600_create_resolve_blend(struct r600_context
*rctx
);
564 void *r700_create_resolve_blend(struct r600_context
*rctx
);
565 void *r600_create_decompress_blend(struct r600_context
*rctx
);
566 void r600_polygon_offset_update(struct r600_context
*rctx
);
567 void r600_adjust_gprs(struct r600_context
*rctx
);
568 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
569 enum pipe_format format
,
570 enum pipe_texture_target target
,
571 unsigned sample_count
,
573 void r600_update_dual_export_state(struct r600_context
* rctx
);
576 void r600_init_screen_texture_functions(struct pipe_screen
*screen
);
577 void r600_init_surface_functions(struct r600_context
*r600
);
578 uint32_t r600_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
579 const unsigned char *swizzle_view
,
580 uint32_t *word4_p
, uint32_t *yuv_format_p
);
581 unsigned r600_texture_get_offset(struct r600_texture
*rtex
,
582 unsigned level
, unsigned layer
);
584 /* r600_translate.c */
585 void r600_translate_index_buffer(struct r600_context
*r600
,
586 struct pipe_index_buffer
*ib
,
589 /* r600_state_common.c */
590 void r600_init_common_state_functions(struct r600_context
*rctx
);
591 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
592 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
);
593 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
);
594 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
595 void r600_init_atom(struct r600_context
*rctx
, struct r600_atom
*atom
, unsigned id
,
596 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
598 void r600_vertex_buffers_dirty(struct r600_context
*rctx
);
599 void r600_sampler_views_dirty(struct r600_context
*rctx
,
600 struct r600_samplerview_state
*state
);
601 void r600_sampler_states_dirty(struct r600_context
*rctx
,
602 struct r600_sampler_states
*state
);
603 void r600_set_max_scissor(struct r600_context
*rctx
);
604 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
);
605 void r600_draw_rectangle(struct blitter_context
*blitter
,
606 unsigned x1
, unsigned y1
, unsigned x2
, unsigned y2
, float depth
,
607 enum blitter_attrib_type type
, const union pipe_color_union
*attrib
);
608 uint32_t r600_translate_stencil_op(int s_op
);
609 uint32_t r600_translate_fill(uint32_t func
);
610 unsigned r600_tex_wrap(unsigned wrap
);
611 unsigned r600_tex_filter(unsigned filter
);
612 unsigned r600_tex_mipfilter(unsigned filter
);
613 unsigned r600_tex_compare(unsigned compare
);
616 * Helpers for building command buffers
619 #define PKT3_SET_CONFIG_REG 0x68
620 #define PKT3_SET_CONTEXT_REG 0x69
621 #define PKT3_SET_CTL_CONST 0x6F
622 #define PKT3_SET_LOOP_CONST 0x6C
624 #define R600_CONFIG_REG_OFFSET 0x08000
625 #define R600_CONTEXT_REG_OFFSET 0x28000
626 #define R600_CTL_CONST_OFFSET 0x3CFF0
627 #define R600_LOOP_CONST_OFFSET 0X0003E200
628 #define EG_LOOP_CONST_OFFSET 0x0003A200
630 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
631 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
632 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
633 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
634 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
636 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
638 /*Evergreen Compute packet3*/
639 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
641 static INLINE
void r600_store_value(struct r600_command_buffer
*cb
, unsigned value
)
643 cb
->buf
[cb
->atom
.num_dw
++] = value
;
646 static INLINE
void r600_store_config_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
648 assert(reg
< R600_CONTEXT_REG_OFFSET
);
649 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
650 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
651 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
655 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
658 static INLINE
void r600_store_context_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
660 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
661 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
662 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0) | cb
->pkt_flags
;
663 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
667 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
670 static INLINE
void r600_store_ctl_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
672 assert(reg
>= R600_CTL_CONST_OFFSET
);
673 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
674 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0) | cb
->pkt_flags
;
675 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
678 static INLINE
void r600_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
680 assert(reg
>= R600_LOOP_CONST_OFFSET
);
681 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
682 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0);
683 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_LOOP_CONST_OFFSET
) >> 2;
687 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
690 static INLINE
void eg_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
692 assert(reg
>= EG_LOOP_CONST_OFFSET
);
693 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
694 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0) | cb
->pkt_flags
;
695 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- EG_LOOP_CONST_OFFSET
) >> 2;
698 static INLINE
void r600_store_config_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
700 r600_store_config_reg_seq(cb
, reg
, 1);
701 r600_store_value(cb
, value
);
704 static INLINE
void r600_store_context_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
706 r600_store_context_reg_seq(cb
, reg
, 1);
707 r600_store_value(cb
, value
);
710 static INLINE
void r600_store_ctl_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
712 r600_store_ctl_const_seq(cb
, reg
, 1);
713 r600_store_value(cb
, value
);
716 static INLINE
void r600_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
718 r600_store_loop_const_seq(cb
, reg
, 1);
719 r600_store_value(cb
, value
);
722 static INLINE
void eg_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
724 eg_store_loop_const_seq(cb
, reg
, 1);
725 r600_store_value(cb
, value
);
728 void r600_init_command_buffer(struct r600_context
*rctx
, struct r600_command_buffer
*cb
, unsigned id
, unsigned num_dw
);
729 void r600_release_command_buffer(struct r600_command_buffer
*cb
);
732 * Helpers for emitting state into a command stream directly.
735 static INLINE
unsigned r600_context_bo_reloc(struct r600_context
*ctx
, struct r600_resource
*rbo
,
736 enum radeon_bo_usage usage
)
739 return ctx
->ws
->cs_add_reloc(ctx
->cs
, rbo
->cs_buf
, usage
, rbo
->domains
) * 4;
742 static INLINE
void r600_write_value(struct radeon_winsys_cs
*cs
, unsigned value
)
744 cs
->buf
[cs
->cdw
++] = value
;
747 static INLINE
void r600_write_array(struct radeon_winsys_cs
*cs
, unsigned num
, unsigned *ptr
)
749 assert(cs
->cdw
+num
<= RADEON_MAX_CMDBUF_DWORDS
);
750 memcpy(&cs
->buf
[cs
->cdw
], ptr
, num
* sizeof(ptr
[0]));
754 static INLINE
void r600_write_config_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
756 assert(reg
< R600_CONTEXT_REG_OFFSET
);
757 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
758 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
759 cs
->buf
[cs
->cdw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
762 static INLINE
void r600_write_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
764 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
765 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
766 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0);
767 cs
->buf
[cs
->cdw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
770 static INLINE
void r600_write_compute_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
772 r600_write_context_reg_seq(cs
, reg
, num
);
773 /* Set the compute bit on the packet header */
774 cs
->buf
[cs
->cdw
- 2] |= RADEON_CP_PACKET3_COMPUTE_MODE
;
777 static INLINE
void r600_write_ctl_const_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
779 assert(reg
>= R600_CTL_CONST_OFFSET
);
780 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
781 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0);
782 cs
->buf
[cs
->cdw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
785 static INLINE
void r600_write_config_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
787 r600_write_config_reg_seq(cs
, reg
, 1);
788 r600_write_value(cs
, value
);
791 static INLINE
void r600_write_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
793 r600_write_context_reg_seq(cs
, reg
, 1);
794 r600_write_value(cs
, value
);
797 static INLINE
void r600_write_compute_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
799 r600_write_compute_context_reg_seq(cs
, reg
, 1);
800 r600_write_value(cs
, value
);
803 static INLINE
void r600_write_ctl_const(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
805 r600_write_ctl_const_seq(cs
, reg
, 1);
806 r600_write_value(cs
, value
);
812 static INLINE
uint32_t S_FIXED(float value
, uint32_t frac_bits
)
814 return value
* (1 << frac_bits
);
816 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
818 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
820 if (filter
<= 1) return 0;
821 if (filter
<= 2) return 1;
822 if (filter
<= 4) return 2;
823 if (filter
<= 8) return 3;
827 /* 12.4 fixed-point */
828 static INLINE
unsigned r600_pack_float_12p4(float x
)
831 x
>= 4096 ? 0xffff : x
* 16;
834 static INLINE
uint64_t r600_resource_va(struct pipe_screen
*screen
, struct pipe_resource
*resource
)
836 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
837 struct r600_resource
*rresource
= (struct r600_resource
*)resource
;
839 return rscreen
->ws
->buffer_get_virtual_address(rresource
->cs_buf
);