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r600g: use TGSI_PROPERTY to disable viewport and clipping
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "../radeon/r600_pipe_common.h"
30 #include "../radeon/r600_cs.h"
31
32 #include "r600_llvm.h"
33 #include "r600_public.h"
34
35 #include "util/u_blitter.h"
36 #include "util/u_suballoc.h"
37 #include "util/u_double_list.h"
38 #include "util/u_transfer.h"
39
40 #define R600_NUM_ATOMS 73
41
42 /* the number of CS dwords for flushing and drawing */
43 #define R600_MAX_FLUSH_CS_DWORDS 16
44 #define R600_MAX_DRAW_CS_DWORDS 37
45 #define R600_TRACE_CS_DWORDS 7
46
47 #define R600_MAX_USER_CONST_BUFFERS 13
48 #define R600_MAX_DRIVER_CONST_BUFFERS 4
49 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
50
51 /* start driver buffers after user buffers */
52 #define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
53 #define R600_TXQ_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
54 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
55 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 3)
56
57 #define R600_MAX_CONST_BUFFER_SIZE 4096
58
59 #ifdef PIPE_ARCH_BIG_ENDIAN
60 #define R600_BIG_ENDIAN 1
61 #else
62 #define R600_BIG_ENDIAN 0
63 #endif
64
65 struct r600_context;
66 struct r600_bytecode;
67 struct r600_shader_key;
68
69 /* This is an atom containing GPU commands that never change.
70 * This is supposed to be copied directly into the CS. */
71 struct r600_command_buffer {
72 uint32_t *buf;
73 unsigned num_dw;
74 unsigned max_num_dw;
75 unsigned pkt_flags;
76 };
77
78 struct r600_db_state {
79 struct r600_atom atom;
80 struct r600_surface *rsurf;
81 };
82
83 struct r600_db_misc_state {
84 struct r600_atom atom;
85 bool occlusion_query_enabled;
86 bool flush_depthstencil_through_cb;
87 bool flush_depthstencil_in_place;
88 bool copy_depth, copy_stencil;
89 unsigned copy_sample;
90 unsigned log_samples;
91 unsigned db_shader_control;
92 bool htile_clear;
93 };
94
95 struct r600_cb_misc_state {
96 struct r600_atom atom;
97 unsigned cb_color_control; /* this comes from blend state */
98 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
99 unsigned nr_cbufs;
100 unsigned nr_ps_color_outputs;
101 bool multiwrite;
102 bool dual_src_blend;
103 };
104
105 struct r600_clip_misc_state {
106 struct r600_atom atom;
107 unsigned pa_cl_clip_cntl; /* from rasterizer */
108 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
109 unsigned clip_plane_enable; /* from rasterizer */
110 unsigned clip_dist_write; /* from vertex shader */
111 boolean clip_disable; /* from vertex shader */
112 };
113
114 struct r600_alphatest_state {
115 struct r600_atom atom;
116 unsigned sx_alpha_test_control; /* this comes from dsa state */
117 unsigned sx_alpha_ref; /* this comes from dsa state */
118 bool bypass;
119 bool cb0_export_16bpc; /* from set_framebuffer_state */
120 };
121
122 struct r600_vgt_state {
123 struct r600_atom atom;
124 uint32_t vgt_multi_prim_ib_reset_en;
125 uint32_t vgt_multi_prim_ib_reset_indx;
126 uint32_t vgt_indx_offset;
127 };
128
129 struct r600_blend_color {
130 struct r600_atom atom;
131 struct pipe_blend_color state;
132 };
133
134 struct r600_clip_state {
135 struct r600_atom atom;
136 struct pipe_clip_state state;
137 };
138
139 struct r600_cs_shader_state {
140 struct r600_atom atom;
141 unsigned kernel_index;
142 struct r600_pipe_compute *shader;
143 };
144
145 struct r600_framebuffer {
146 struct r600_atom atom;
147 struct pipe_framebuffer_state state;
148 unsigned compressed_cb_mask;
149 unsigned nr_samples;
150 bool export_16bpc;
151 bool cb0_is_integer;
152 bool is_msaa_resolve;
153 };
154
155 struct r600_sample_mask {
156 struct r600_atom atom;
157 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
158 };
159
160 struct r600_config_state {
161 struct r600_atom atom;
162 unsigned sq_gpr_resource_mgmt_1;
163 unsigned sq_gpr_resource_mgmt_2;
164 };
165
166 struct r600_stencil_ref
167 {
168 ubyte ref_value[2];
169 ubyte valuemask[2];
170 ubyte writemask[2];
171 };
172
173 struct r600_stencil_ref_state {
174 struct r600_atom atom;
175 struct r600_stencil_ref state;
176 struct pipe_stencil_ref pipe_state;
177 };
178
179 struct r600_viewport_state {
180 struct r600_atom atom;
181 struct pipe_viewport_state state;
182 int idx;
183 };
184
185 struct r600_shader_stages_state {
186 struct r600_atom atom;
187 unsigned geom_enable;
188 };
189
190 struct r600_gs_rings_state {
191 struct r600_atom atom;
192 unsigned enable;
193 struct pipe_constant_buffer esgs_ring;
194 struct pipe_constant_buffer gsvs_ring;
195 };
196
197 /* This must start from 16. */
198 /* features */
199 #define DBG_LLVM (1 << 17)
200 #define DBG_NO_CP_DMA (1 << 18)
201 /* shader backend */
202 #define DBG_NO_SB (1 << 21)
203 #define DBG_SB_CS (1 << 22)
204 #define DBG_SB_DRY_RUN (1 << 23)
205 #define DBG_SB_STAT (1 << 24)
206 #define DBG_SB_DUMP (1 << 25)
207 #define DBG_SB_NO_FALLBACK (1 << 26)
208 #define DBG_SB_DISASM (1 << 27)
209 #define DBG_SB_SAFEMATH (1 << 28)
210
211 struct r600_screen {
212 struct r600_common_screen b;
213 bool has_msaa;
214 bool has_compressed_msaa_texturing;
215
216 /*for compute global memory binding, we allocate stuff here, instead of
217 * buffers.
218 * XXX: Not sure if this is the best place for global_pool. Also,
219 * it's not thread safe, so it won't work with multiple contexts. */
220 struct compute_memory_pool *global_pool;
221 };
222
223 struct r600_pipe_sampler_view {
224 struct pipe_sampler_view base;
225 struct r600_resource *tex_resource;
226 uint32_t tex_resource_words[8];
227 bool skip_mip_address_reloc;
228 };
229
230 struct r600_rasterizer_state {
231 struct r600_command_buffer buffer;
232 boolean flatshade;
233 boolean two_side;
234 unsigned sprite_coord_enable;
235 unsigned clip_plane_enable;
236 unsigned pa_sc_line_stipple;
237 unsigned pa_cl_clip_cntl;
238 unsigned pa_su_sc_mode_cntl;
239 float offset_units;
240 float offset_scale;
241 bool offset_enable;
242 bool scissor_enable;
243 bool multisample_enable;
244 };
245
246 struct r600_poly_offset_state {
247 struct r600_atom atom;
248 enum pipe_format zs_format;
249 float offset_units;
250 float offset_scale;
251 };
252
253 struct r600_blend_state {
254 struct r600_command_buffer buffer;
255 struct r600_command_buffer buffer_no_blend;
256 unsigned cb_target_mask;
257 unsigned cb_color_control;
258 unsigned cb_color_control_no_blend;
259 bool dual_src_blend;
260 bool alpha_to_one;
261 };
262
263 struct r600_dsa_state {
264 struct r600_command_buffer buffer;
265 unsigned alpha_ref;
266 ubyte valuemask[2];
267 ubyte writemask[2];
268 unsigned zwritemask;
269 unsigned sx_alpha_test_control;
270 };
271
272 struct r600_pipe_shader;
273
274 struct r600_pipe_shader_selector {
275 struct r600_pipe_shader *current;
276
277 struct tgsi_token *tokens;
278 struct pipe_stream_output_info so;
279
280 unsigned num_shaders;
281
282 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
283 unsigned type;
284
285 unsigned nr_ps_max_color_exports;
286 };
287
288 struct r600_pipe_sampler_state {
289 uint32_t tex_sampler_words[3];
290 union pipe_color_union border_color;
291 bool border_color_use;
292 bool seamless_cube_map;
293 };
294
295 /* needed for blitter save */
296 #define NUM_TEX_UNITS 16
297
298 struct r600_seamless_cube_map {
299 struct r600_atom atom;
300 bool enabled;
301 };
302
303 struct r600_samplerview_state {
304 struct r600_atom atom;
305 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
306 uint32_t enabled_mask;
307 uint32_t dirty_mask;
308 uint32_t compressed_depthtex_mask; /* which textures are depth */
309 uint32_t compressed_colortex_mask;
310 boolean dirty_txq_constants;
311 boolean dirty_buffer_constants;
312 };
313
314 struct r600_sampler_states {
315 struct r600_atom atom;
316 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
317 uint32_t enabled_mask;
318 uint32_t dirty_mask;
319 uint32_t has_bordercolor_mask; /* which states contain the border color */
320 };
321
322 struct r600_textures_info {
323 struct r600_samplerview_state views;
324 struct r600_sampler_states states;
325 bool is_array_sampler[NUM_TEX_UNITS];
326
327 /* cube array txq workaround */
328 uint32_t *txq_constants;
329 /* buffer related workarounds */
330 uint32_t *buffer_constants;
331 };
332
333 struct r600_constbuf_state
334 {
335 struct r600_atom atom;
336 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
337 uint32_t enabled_mask;
338 uint32_t dirty_mask;
339 };
340
341 struct r600_vertexbuf_state
342 {
343 struct r600_atom atom;
344 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
345 uint32_t enabled_mask; /* non-NULL buffers */
346 uint32_t dirty_mask;
347 };
348
349 /* CSO (constant state object, in other words, immutable state). */
350 struct r600_cso_state
351 {
352 struct r600_atom atom;
353 void *cso; /* e.g. r600_blend_state */
354 struct r600_command_buffer *cb;
355 };
356
357 struct r600_scissor_state
358 {
359 struct r600_atom atom;
360 struct pipe_scissor_state scissor;
361 bool enable; /* r6xx only */
362 int idx;
363 };
364
365 struct r600_fetch_shader {
366 struct r600_resource *buffer;
367 unsigned offset;
368 };
369
370 struct r600_shader_state {
371 struct r600_atom atom;
372 struct r600_pipe_shader *shader;
373 };
374
375 struct r600_context {
376 struct r600_common_context b;
377 struct r600_screen *screen;
378 struct blitter_context *blitter;
379 struct u_suballocator *allocator_fetch_shader;
380
381 /* Hardware info. */
382 boolean has_vertex_cache;
383 boolean keep_tiling_flags;
384 unsigned default_ps_gprs, default_vs_gprs;
385 unsigned r6xx_num_clause_temp_gprs;
386
387 /* Miscellaneous state objects. */
388 void *custom_dsa_flush;
389 void *custom_blend_resolve;
390 void *custom_blend_decompress;
391 void *custom_blend_fastclear;
392 /* With rasterizer discard, there doesn't have to be a pixel shader.
393 * In that case, we bind this one: */
394 void *dummy_pixel_shader;
395 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
396 * bug where valid CMASK and FMASK are required to be present to avoid
397 * a hardlock in certain operations but aren't actually used
398 * for anything useful. */
399 struct r600_resource *dummy_fmask;
400 struct r600_resource *dummy_cmask;
401
402 /* State binding slots are here. */
403 struct r600_atom *atoms[R600_NUM_ATOMS];
404 /* States for CS initialization. */
405 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
406 /** Compute specific registers initializations. The start_cs_cmd atom
407 * must be emitted before start_compute_cs_cmd. */
408 struct r600_command_buffer start_compute_cs_cmd;
409 /* Register states. */
410 struct r600_alphatest_state alphatest_state;
411 struct r600_cso_state blend_state;
412 struct r600_blend_color blend_color;
413 struct r600_cb_misc_state cb_misc_state;
414 struct r600_clip_misc_state clip_misc_state;
415 struct r600_clip_state clip_state;
416 struct r600_db_misc_state db_misc_state;
417 struct r600_db_state db_state;
418 struct r600_cso_state dsa_state;
419 struct r600_framebuffer framebuffer;
420 struct r600_poly_offset_state poly_offset_state;
421 struct r600_cso_state rasterizer_state;
422 struct r600_sample_mask sample_mask;
423 struct r600_scissor_state scissor[16];
424 struct r600_seamless_cube_map seamless_cube_map;
425 struct r600_config_state config_state;
426 struct r600_stencil_ref_state stencil_ref;
427 struct r600_vgt_state vgt_state;
428 struct r600_viewport_state viewport[16];
429 /* Shaders and shader resources. */
430 struct r600_cso_state vertex_fetch_shader;
431 struct r600_shader_state vertex_shader;
432 struct r600_shader_state pixel_shader;
433 struct r600_shader_state geometry_shader;
434 struct r600_shader_state export_shader;
435 struct r600_cs_shader_state cs_shader_state;
436 struct r600_shader_stages_state shader_stages;
437 struct r600_gs_rings_state gs_rings;
438 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
439 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
440 /** Vertex buffers for fetch shaders */
441 struct r600_vertexbuf_state vertex_buffer_state;
442 /** Vertex buffers for compute shaders */
443 struct r600_vertexbuf_state cs_vertex_buffer_state;
444
445 /* Additional context states. */
446 unsigned compute_cb_target_mask;
447 struct r600_pipe_shader_selector *ps_shader;
448 struct r600_pipe_shader_selector *vs_shader;
449 struct r600_pipe_shader_selector *gs_shader;
450 struct r600_rasterizer_state *rasterizer;
451 bool alpha_to_one;
452 bool force_blend_disable;
453 boolean dual_src_blend;
454 unsigned zwritemask;
455
456 /* Index buffer. */
457 struct pipe_index_buffer index_buffer;
458
459 /* Last draw state (-1 = unset). */
460 int last_primitive_type; /* Last primitive type used in draw_vbo. */
461 int last_start_instance;
462
463 void *sb_context;
464 struct r600_isa *isa;
465 };
466
467 static INLINE void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
468 struct r600_command_buffer *cb)
469 {
470 assert(cs->cdw + cb->num_dw <= RADEON_MAX_CMDBUF_DWORDS);
471 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->num_dw);
472 cs->cdw += cb->num_dw;
473 }
474
475 void r600_trace_emit(struct r600_context *rctx);
476
477 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
478 {
479 atom->emit(&rctx->b, atom);
480 atom->dirty = false;
481 if (rctx->screen->b.trace_bo) {
482 r600_trace_emit(rctx);
483 }
484 }
485
486 static INLINE void r600_set_cso_state(struct r600_cso_state *state, void *cso)
487 {
488 state->cso = cso;
489 state->atom.dirty = cso != NULL;
490 }
491
492 static INLINE void r600_set_cso_state_with_cb(struct r600_cso_state *state, void *cso,
493 struct r600_command_buffer *cb)
494 {
495 state->cb = cb;
496 state->atom.num_dw = cb ? cb->num_dw : 0;
497 r600_set_cso_state(state, cso);
498 }
499
500 /* compute_memory_pool.c */
501 struct compute_memory_pool;
502 void compute_memory_pool_delete(struct compute_memory_pool* pool);
503 struct compute_memory_pool* compute_memory_pool_new(
504 struct r600_screen *rscreen);
505
506 /* evergreen_compute.c */
507 void evergreen_set_cs_sampler_view(struct pipe_context *ctx_,
508 unsigned start_slot, unsigned count,
509 struct pipe_sampler_view **views);
510
511 /* evergreen_state.c */
512 struct pipe_sampler_view *
513 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
514 struct pipe_resource *texture,
515 const struct pipe_sampler_view *state,
516 unsigned width0, unsigned height0,
517 unsigned force_level);
518 void evergreen_init_common_regs(struct r600_command_buffer *cb,
519 enum chip_class ctx_chip_class,
520 enum radeon_family ctx_family,
521 int ctx_drm_minor);
522 void cayman_init_common_regs(struct r600_command_buffer *cb,
523 enum chip_class ctx_chip_class,
524 enum radeon_family ctx_family,
525 int ctx_drm_minor);
526
527 void evergreen_init_state_functions(struct r600_context *rctx);
528 void evergreen_init_atom_start_cs(struct r600_context *rctx);
529 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
530 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
531 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
532 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
533 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
534 void *evergreen_create_resolve_blend(struct r600_context *rctx);
535 void *evergreen_create_decompress_blend(struct r600_context *rctx);
536 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
537 boolean evergreen_is_format_supported(struct pipe_screen *screen,
538 enum pipe_format format,
539 enum pipe_texture_target target,
540 unsigned sample_count,
541 unsigned usage);
542 void evergreen_init_color_surface(struct r600_context *rctx,
543 struct r600_surface *surf);
544 void evergreen_init_color_surface_rat(struct r600_context *rctx,
545 struct r600_surface *surf);
546 void evergreen_update_db_shader_control(struct r600_context * rctx);
547
548 /* r600_blit.c */
549 void r600_init_blit_functions(struct r600_context *rctx);
550 void r600_decompress_depth_textures(struct r600_context *rctx,
551 struct r600_samplerview_state *textures);
552 void r600_decompress_color_textures(struct r600_context *rctx,
553 struct r600_samplerview_state *textures);
554
555 /* r600_shader.c */
556 int r600_pipe_shader_create(struct pipe_context *ctx,
557 struct r600_pipe_shader *shader,
558 struct r600_shader_key key);
559
560 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
561
562 /* r600_state.c */
563 struct pipe_sampler_view *
564 r600_create_sampler_view_custom(struct pipe_context *ctx,
565 struct pipe_resource *texture,
566 const struct pipe_sampler_view *state,
567 unsigned width_first_level, unsigned height_first_level);
568 void r600_init_state_functions(struct r600_context *rctx);
569 void r600_init_atom_start_cs(struct r600_context *rctx);
570 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
571 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
572 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
573 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
574 void *r600_create_db_flush_dsa(struct r600_context *rctx);
575 void *r600_create_resolve_blend(struct r600_context *rctx);
576 void *r700_create_resolve_blend(struct r600_context *rctx);
577 void *r600_create_decompress_blend(struct r600_context *rctx);
578 bool r600_adjust_gprs(struct r600_context *rctx);
579 boolean r600_is_format_supported(struct pipe_screen *screen,
580 enum pipe_format format,
581 enum pipe_texture_target target,
582 unsigned sample_count,
583 unsigned usage);
584 void r600_update_db_shader_control(struct r600_context * rctx);
585
586 /* r600_hw_context.c */
587 void r600_context_gfx_flush(void *context, unsigned flags,
588 struct pipe_fence_handle **fence);
589 void r600_begin_new_cs(struct r600_context *ctx);
590 void r600_flush_emit(struct r600_context *ctx);
591 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
592 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
593 struct pipe_resource *dst, uint64_t dst_offset,
594 struct pipe_resource *src, uint64_t src_offset,
595 unsigned size);
596 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
597 struct pipe_resource *dst, uint64_t offset,
598 unsigned size, uint32_t clear_value);
599 void r600_dma_copy_buffer(struct r600_context *rctx,
600 struct pipe_resource *dst,
601 struct pipe_resource *src,
602 uint64_t dst_offset,
603 uint64_t src_offset,
604 uint64_t size);
605
606 /*
607 * evergreen_hw_context.c
608 */
609 void evergreen_dma_copy_buffer(struct r600_context *rctx,
610 struct pipe_resource *dst,
611 struct pipe_resource *src,
612 uint64_t dst_offset,
613 uint64_t src_offset,
614 uint64_t size);
615
616 /* r600_state_common.c */
617 void r600_init_common_state_functions(struct r600_context *rctx);
618 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
619 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
620 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
621 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
622 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
623 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
624 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom);
625 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
626 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
627 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
628 unsigned num_dw);
629 void r600_vertex_buffers_dirty(struct r600_context *rctx);
630 void r600_sampler_views_dirty(struct r600_context *rctx,
631 struct r600_samplerview_state *state);
632 void r600_sampler_states_dirty(struct r600_context *rctx,
633 struct r600_sampler_states *state);
634 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
635 void r600_draw_rectangle(struct blitter_context *blitter,
636 int x1, int y1, int x2, int y2, float depth,
637 enum blitter_attrib_type type, const union pipe_color_union *attrib);
638 uint32_t r600_translate_stencil_op(int s_op);
639 uint32_t r600_translate_fill(uint32_t func);
640 unsigned r600_tex_wrap(unsigned wrap);
641 unsigned r600_tex_filter(unsigned filter);
642 unsigned r600_tex_mipfilter(unsigned filter);
643 unsigned r600_tex_compare(unsigned compare);
644 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
645 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
646 struct pipe_resource *texture,
647 const struct pipe_surface *templ,
648 unsigned width, unsigned height);
649 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
650 const unsigned char *swizzle_view,
651 boolean vtx);
652 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
653 const unsigned char *swizzle_view,
654 uint32_t *word4_p, uint32_t *yuv_format_p);
655 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format);
656 uint32_t r600_colorformat_endian_swap(uint32_t colorformat);
657
658 /* r600_uvd.c */
659 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
660 const struct pipe_video_codec *decoder);
661
662 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
663 const struct pipe_video_buffer *tmpl);
664
665 /*
666 * Helpers for building command buffers
667 */
668
669 #define PKT3_SET_CONFIG_REG 0x68
670 #define PKT3_SET_CONTEXT_REG 0x69
671 #define PKT3_SET_CTL_CONST 0x6F
672 #define PKT3_SET_LOOP_CONST 0x6C
673
674 #define R600_CONFIG_REG_OFFSET 0x08000
675 #define R600_CONTEXT_REG_OFFSET 0x28000
676 #define R600_CTL_CONST_OFFSET 0x3CFF0
677 #define R600_LOOP_CONST_OFFSET 0X0003E200
678 #define EG_LOOP_CONST_OFFSET 0x0003A200
679
680 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
681 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
682 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
683 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
684 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
685
686 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
687
688 /*Evergreen Compute packet3*/
689 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
690
691 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
692 {
693 cb->buf[cb->num_dw++] = value;
694 }
695
696 static INLINE void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
697 {
698 assert(cb->num_dw+num <= cb->max_num_dw);
699 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
700 cb->num_dw += num;
701 }
702
703 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
704 {
705 assert(reg < R600_CONTEXT_REG_OFFSET);
706 assert(cb->num_dw+2+num <= cb->max_num_dw);
707 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
708 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
709 }
710
711 /**
712 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
713 * shaders.
714 */
715 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
716 {
717 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
718 assert(cb->num_dw+2+num <= cb->max_num_dw);
719 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
720 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
721 }
722
723 /**
724 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
725 * shaders.
726 */
727 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
728 {
729 assert(reg >= R600_CTL_CONST_OFFSET);
730 assert(cb->num_dw+2+num <= cb->max_num_dw);
731 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
732 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
733 }
734
735 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
736 {
737 assert(reg >= R600_LOOP_CONST_OFFSET);
738 assert(cb->num_dw+2+num <= cb->max_num_dw);
739 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
740 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
741 }
742
743 /**
744 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
745 * shaders.
746 */
747 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
748 {
749 assert(reg >= EG_LOOP_CONST_OFFSET);
750 assert(cb->num_dw+2+num <= cb->max_num_dw);
751 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
752 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
753 }
754
755 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
756 {
757 r600_store_config_reg_seq(cb, reg, 1);
758 r600_store_value(cb, value);
759 }
760
761 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
762 {
763 r600_store_context_reg_seq(cb, reg, 1);
764 r600_store_value(cb, value);
765 }
766
767 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
768 {
769 r600_store_ctl_const_seq(cb, reg, 1);
770 r600_store_value(cb, value);
771 }
772
773 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
774 {
775 r600_store_loop_const_seq(cb, reg, 1);
776 r600_store_value(cb, value);
777 }
778
779 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
780 {
781 eg_store_loop_const_seq(cb, reg, 1);
782 r600_store_value(cb, value);
783 }
784
785 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
786 void r600_release_command_buffer(struct r600_command_buffer *cb);
787
788 static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
789 {
790 r600_write_context_reg_seq(cs, reg, num);
791 /* Set the compute bit on the packet header */
792 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
793 }
794
795 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
796 {
797 assert(reg >= R600_CTL_CONST_OFFSET);
798 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
799 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
800 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
801 }
802
803 static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
804 {
805 r600_write_compute_context_reg_seq(cs, reg, 1);
806 radeon_emit(cs, value);
807 }
808
809 static INLINE void r600_write_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
810 {
811 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
812 r600_write_compute_context_reg(cs, reg, value);
813 } else {
814 r600_write_context_reg(cs, reg, value);
815 }
816 }
817
818 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
819 {
820 r600_write_ctl_const_seq(cs, reg, 1);
821 radeon_emit(cs, value);
822 }
823
824 /*
825 * common helpers
826 */
827 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
828 {
829 return value * (1 << frac_bits);
830 }
831 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
832
833 /* 12.4 fixed-point */
834 static INLINE unsigned r600_pack_float_12p4(float x)
835 {
836 return x <= 0 ? 0 :
837 x >= 4096 ? 0xffff : x * 16;
838 }
839
840 /* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */
841 static INLINE bool r600_can_read_depth(struct r600_texture *rtex)
842 {
843 return rtex->resource.b.b.nr_samples <= 1 &&
844 (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
845 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT);
846 }
847
848 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
849 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
850 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
851
852 static INLINE unsigned r600_conv_prim_to_gs_out(unsigned mode)
853 {
854 static const int prim_conv[] = {
855 V_028A6C_OUTPRIM_TYPE_POINTLIST,
856 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
857 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
858 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
859 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
860 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
861 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
862 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
863 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
864 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
865 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
866 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
867 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
868 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
869 V_028A6C_OUTPRIM_TYPE_TRISTRIP
870 };
871 assert(mode < Elements(prim_conv));
872
873 return prim_conv[mode];
874 }
875
876 #endif