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r600: fix missing include for Elements macro
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "radeon/r600_pipe_common.h"
30 #include "radeon/r600_cs.h"
31 #include "r600_public.h"
32
33 #include "util/u_suballoc.h"
34 #include "util/list.h"
35 #include "util/u_transfer.h"
36 #include "util/u_memory.h"
37
38 #include "tgsi/tgsi_scan.h"
39
40 #define R600_NUM_ATOMS 52
41
42 /* read caches */
43 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
44 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
45 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
46 /* read-write caches */
47 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
48 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
49 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
50 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
51 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
52 /* engine synchronization */
53 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
54 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
55 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
56
57 /* the number of CS dwords for flushing and drawing */
58 #define R600_MAX_FLUSH_CS_DWORDS 18
59 #define R600_MAX_DRAW_CS_DWORDS 58
60
61 #define R600_MAX_USER_CONST_BUFFERS 13
62 #define R600_MAX_DRIVER_CONST_BUFFERS 3
63 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
64
65 /* start driver buffers after user buffers */
66 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
67 #define R600_UCP_SIZE (4*4*8)
68 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
69
70 #define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
71 /*
72 * Note GS doesn't use a constant buffer binding, just a resource index,
73 * so it's fine to have it exist at index 16.
74 */
75 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
76 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
77 * of 16 const buffers.
78 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
79 *
80 * In order to support d3d 11 mandated minimum of 15 user const buffers
81 * we'd have to squash all use cases into one driver buffer.
82 */
83 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
84
85 /* HW stages */
86 #define R600_HW_STAGE_PS 0
87 #define R600_HW_STAGE_VS 1
88 #define R600_HW_STAGE_GS 2
89 #define R600_HW_STAGE_ES 3
90 #define EG_HW_STAGE_LS 4
91 #define EG_HW_STAGE_HS 5
92
93 #define R600_NUM_HW_STAGES 4
94 #define EG_NUM_HW_STAGES 6
95
96 struct r600_context;
97 struct r600_bytecode;
98 union r600_shader_key;
99
100 /* This is an atom containing GPU commands that never change.
101 * This is supposed to be copied directly into the CS. */
102 struct r600_command_buffer {
103 uint32_t *buf;
104 unsigned num_dw;
105 unsigned max_num_dw;
106 unsigned pkt_flags;
107 };
108
109 struct r600_db_state {
110 struct r600_atom atom;
111 struct r600_surface *rsurf;
112 };
113
114 struct r600_db_misc_state {
115 struct r600_atom atom;
116 bool occlusion_queries_disabled;
117 bool flush_depthstencil_through_cb;
118 bool flush_depth_inplace;
119 bool flush_stencil_inplace;
120 bool copy_depth, copy_stencil;
121 unsigned copy_sample;
122 unsigned log_samples;
123 unsigned db_shader_control;
124 bool htile_clear;
125 uint8_t ps_conservative_z;
126 };
127
128 struct r600_cb_misc_state {
129 struct r600_atom atom;
130 unsigned cb_color_control; /* this comes from blend state */
131 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
132 unsigned nr_cbufs;
133 unsigned nr_ps_color_outputs;
134 bool multiwrite;
135 bool dual_src_blend;
136 };
137
138 struct r600_clip_misc_state {
139 struct r600_atom atom;
140 unsigned pa_cl_clip_cntl; /* from rasterizer */
141 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
142 unsigned clip_plane_enable; /* from rasterizer */
143 unsigned clip_dist_write; /* from vertex shader */
144 boolean clip_disable; /* from vertex shader */
145 boolean vs_out_viewport; /* from vertex shader */
146 };
147
148 struct r600_alphatest_state {
149 struct r600_atom atom;
150 unsigned sx_alpha_test_control; /* this comes from dsa state */
151 unsigned sx_alpha_ref; /* this comes from dsa state */
152 bool bypass;
153 bool cb0_export_16bpc; /* from set_framebuffer_state */
154 };
155
156 struct r600_vgt_state {
157 struct r600_atom atom;
158 uint32_t vgt_multi_prim_ib_reset_en;
159 uint32_t vgt_multi_prim_ib_reset_indx;
160 uint32_t vgt_indx_offset;
161 bool last_draw_was_indirect;
162 };
163
164 struct r600_blend_color {
165 struct r600_atom atom;
166 struct pipe_blend_color state;
167 };
168
169 struct r600_clip_state {
170 struct r600_atom atom;
171 struct pipe_clip_state state;
172 };
173
174 struct r600_cs_shader_state {
175 struct r600_atom atom;
176 unsigned kernel_index;
177 unsigned pc;
178 struct r600_pipe_compute *shader;
179 };
180
181 struct r600_framebuffer {
182 struct r600_atom atom;
183 struct pipe_framebuffer_state state;
184 unsigned compressed_cb_mask;
185 unsigned nr_samples;
186 bool export_16bpc;
187 bool cb0_is_integer;
188 bool is_msaa_resolve;
189 };
190
191 struct r600_sample_mask {
192 struct r600_atom atom;
193 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
194 };
195
196 struct r600_config_state {
197 struct r600_atom atom;
198 unsigned sq_gpr_resource_mgmt_1;
199 unsigned sq_gpr_resource_mgmt_2;
200 unsigned sq_gpr_resource_mgmt_3;
201 bool dyn_gpr_enabled;
202 };
203
204 struct r600_stencil_ref
205 {
206 ubyte ref_value[2];
207 ubyte valuemask[2];
208 ubyte writemask[2];
209 };
210
211 struct r600_stencil_ref_state {
212 struct r600_atom atom;
213 struct r600_stencil_ref state;
214 struct pipe_stencil_ref pipe_state;
215 };
216
217 struct r600_shader_stages_state {
218 struct r600_atom atom;
219 unsigned geom_enable;
220 };
221
222 struct r600_gs_rings_state {
223 struct r600_atom atom;
224 unsigned enable;
225 struct pipe_constant_buffer esgs_ring;
226 struct pipe_constant_buffer gsvs_ring;
227 };
228
229 /* This must start from 16. */
230 /* features */
231 #define DBG_NO_CP_DMA (1 << 30)
232 /* shader backend */
233 #define DBG_NO_SB (1 << 21)
234 #define DBG_SB_CS (1 << 22)
235 #define DBG_SB_DRY_RUN (1 << 23)
236 #define DBG_SB_STAT (1 << 24)
237 #define DBG_SB_DUMP (1 << 25)
238 #define DBG_SB_NO_FALLBACK (1 << 26)
239 #define DBG_SB_DISASM (1 << 27)
240 #define DBG_SB_SAFEMATH (1 << 28)
241
242 struct r600_screen {
243 struct r600_common_screen b;
244 bool has_msaa;
245 bool has_compressed_msaa_texturing;
246
247 /*for compute global memory binding, we allocate stuff here, instead of
248 * buffers.
249 * XXX: Not sure if this is the best place for global_pool. Also,
250 * it's not thread safe, so it won't work with multiple contexts. */
251 struct compute_memory_pool *global_pool;
252 };
253
254 struct r600_pipe_sampler_view {
255 struct pipe_sampler_view base;
256 struct list_head list;
257 struct r600_resource *tex_resource;
258 uint32_t tex_resource_words[8];
259 bool skip_mip_address_reloc;
260 bool is_stencil_sampler;
261 };
262
263 struct r600_rasterizer_state {
264 struct r600_command_buffer buffer;
265 boolean flatshade;
266 boolean two_side;
267 unsigned sprite_coord_enable;
268 unsigned clip_plane_enable;
269 unsigned pa_sc_line_stipple;
270 unsigned pa_cl_clip_cntl;
271 unsigned pa_su_sc_mode_cntl;
272 float offset_units;
273 float offset_scale;
274 bool offset_enable;
275 bool scissor_enable;
276 bool multisample_enable;
277 };
278
279 struct r600_poly_offset_state {
280 struct r600_atom atom;
281 enum pipe_format zs_format;
282 float offset_units;
283 float offset_scale;
284 };
285
286 struct r600_blend_state {
287 struct r600_command_buffer buffer;
288 struct r600_command_buffer buffer_no_blend;
289 unsigned cb_target_mask;
290 unsigned cb_color_control;
291 unsigned cb_color_control_no_blend;
292 bool dual_src_blend;
293 bool alpha_to_one;
294 };
295
296 struct r600_dsa_state {
297 struct r600_command_buffer buffer;
298 unsigned alpha_ref;
299 ubyte valuemask[2];
300 ubyte writemask[2];
301 unsigned zwritemask;
302 unsigned sx_alpha_test_control;
303 };
304
305 struct r600_pipe_shader;
306
307 struct r600_pipe_shader_selector {
308 struct r600_pipe_shader *current;
309
310 struct tgsi_token *tokens;
311 struct pipe_stream_output_info so;
312 struct tgsi_shader_info info;
313
314 unsigned num_shaders;
315
316 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
317 unsigned type;
318
319 /* geometry shader properties */
320 unsigned gs_output_prim;
321 unsigned gs_max_out_vertices;
322 unsigned gs_num_invocations;
323
324 /* TCS/VS */
325 uint64_t lds_patch_outputs_written_mask;
326 uint64_t lds_outputs_written_mask;
327 unsigned nr_ps_max_color_exports;
328 };
329
330 struct r600_pipe_sampler_state {
331 uint32_t tex_sampler_words[3];
332 union pipe_color_union border_color;
333 bool border_color_use;
334 bool seamless_cube_map;
335 };
336
337 /* needed for blitter save */
338 #define NUM_TEX_UNITS 16
339
340 struct r600_seamless_cube_map {
341 struct r600_atom atom;
342 bool enabled;
343 };
344
345 struct r600_samplerview_state {
346 struct r600_atom atom;
347 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
348 uint32_t enabled_mask;
349 uint32_t dirty_mask;
350 uint32_t compressed_depthtex_mask; /* which textures are depth */
351 uint32_t compressed_colortex_mask;
352 boolean dirty_buffer_constants;
353 };
354
355 struct r600_sampler_states {
356 struct r600_atom atom;
357 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
358 uint32_t enabled_mask;
359 uint32_t dirty_mask;
360 uint32_t has_bordercolor_mask; /* which states contain the border color */
361 };
362
363 struct r600_textures_info {
364 struct r600_samplerview_state views;
365 struct r600_sampler_states states;
366 bool is_array_sampler[NUM_TEX_UNITS];
367 };
368
369 struct r600_shader_driver_constants_info {
370 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
371 uint32_t *constants;
372 uint32_t alloc_size;
373 bool vs_ucp_dirty;
374 bool texture_const_dirty;
375 bool ps_sample_pos_dirty;
376 };
377
378 struct r600_constbuf_state
379 {
380 struct r600_atom atom;
381 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
382 uint32_t enabled_mask;
383 uint32_t dirty_mask;
384 };
385
386 struct r600_vertexbuf_state
387 {
388 struct r600_atom atom;
389 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
390 uint32_t enabled_mask; /* non-NULL buffers */
391 uint32_t dirty_mask;
392 };
393
394 /* CSO (constant state object, in other words, immutable state). */
395 struct r600_cso_state
396 {
397 struct r600_atom atom;
398 void *cso; /* e.g. r600_blend_state */
399 struct r600_command_buffer *cb;
400 };
401
402 struct r600_fetch_shader {
403 struct r600_resource *buffer;
404 unsigned offset;
405 };
406
407 struct r600_shader_state {
408 struct r600_atom atom;
409 struct r600_pipe_shader *shader;
410 };
411
412 struct r600_context {
413 struct r600_common_context b;
414 struct r600_screen *screen;
415 struct blitter_context *blitter;
416 struct u_suballocator *allocator_fetch_shader;
417
418 /* Hardware info. */
419 boolean has_vertex_cache;
420 unsigned default_gprs[EG_NUM_HW_STAGES];
421 unsigned current_gprs[EG_NUM_HW_STAGES];
422 unsigned r6xx_num_clause_temp_gprs;
423
424 /* Miscellaneous state objects. */
425 void *custom_dsa_flush;
426 void *custom_blend_resolve;
427 void *custom_blend_decompress;
428 void *custom_blend_fastclear;
429 /* With rasterizer discard, there doesn't have to be a pixel shader.
430 * In that case, we bind this one: */
431 void *dummy_pixel_shader;
432 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
433 * bug where valid CMASK and FMASK are required to be present to avoid
434 * a hardlock in certain operations but aren't actually used
435 * for anything useful. */
436 struct r600_resource *dummy_fmask;
437 struct r600_resource *dummy_cmask;
438
439 /* State binding slots are here. */
440 struct r600_atom *atoms[R600_NUM_ATOMS];
441 /* Dirty atom bitmask for fast tests */
442 uint64_t dirty_atoms;
443 /* States for CS initialization. */
444 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
445 /** Compute specific registers initializations. The start_cs_cmd atom
446 * must be emitted before start_compute_cs_cmd. */
447 struct r600_command_buffer start_compute_cs_cmd;
448 /* Register states. */
449 struct r600_alphatest_state alphatest_state;
450 struct r600_cso_state blend_state;
451 struct r600_blend_color blend_color;
452 struct r600_cb_misc_state cb_misc_state;
453 struct r600_clip_misc_state clip_misc_state;
454 struct r600_clip_state clip_state;
455 struct r600_db_misc_state db_misc_state;
456 struct r600_db_state db_state;
457 struct r600_cso_state dsa_state;
458 struct r600_framebuffer framebuffer;
459 struct r600_poly_offset_state poly_offset_state;
460 struct r600_cso_state rasterizer_state;
461 struct r600_sample_mask sample_mask;
462 struct r600_seamless_cube_map seamless_cube_map;
463 struct r600_config_state config_state;
464 struct r600_stencil_ref_state stencil_ref;
465 struct r600_vgt_state vgt_state;
466 /* Shaders and shader resources. */
467 struct r600_cso_state vertex_fetch_shader;
468 struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES];
469 struct r600_cs_shader_state cs_shader_state;
470 struct r600_shader_stages_state shader_stages;
471 struct r600_gs_rings_state gs_rings;
472 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
473 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
474
475 struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES];
476
477 /** Vertex buffers for fetch shaders */
478 struct r600_vertexbuf_state vertex_buffer_state;
479 /** Vertex buffers for compute shaders */
480 struct r600_vertexbuf_state cs_vertex_buffer_state;
481
482 /* Additional context states. */
483 unsigned compute_cb_target_mask;
484 struct r600_pipe_shader_selector *ps_shader;
485 struct r600_pipe_shader_selector *vs_shader;
486 struct r600_pipe_shader_selector *gs_shader;
487
488 struct r600_pipe_shader_selector *tcs_shader;
489 struct r600_pipe_shader_selector *tes_shader;
490
491 struct r600_pipe_shader_selector *fixed_func_tcs_shader;
492
493 struct r600_rasterizer_state *rasterizer;
494 bool alpha_to_one;
495 bool force_blend_disable;
496 boolean dual_src_blend;
497 unsigned zwritemask;
498 int ps_iter_samples;
499
500 /* Index buffer. */
501 struct pipe_index_buffer index_buffer;
502
503 /* Last draw state (-1 = unset). */
504 int last_primitive_type; /* Last primitive type used in draw_vbo. */
505 int last_start_instance;
506
507 void *sb_context;
508 struct r600_isa *isa;
509 float sample_positions[4 * 16];
510 float tess_state[8];
511 bool tess_state_dirty;
512 struct r600_pipe_shader_selector *last_ls;
513 struct r600_pipe_shader_selector *last_tcs;
514 unsigned last_num_tcs_input_cp;
515 unsigned lds_alloc;
516 };
517
518 static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
519 struct r600_command_buffer *cb)
520 {
521 assert(cs->cdw + cb->num_dw <= cs->max_dw);
522 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->num_dw);
523 cs->cdw += cb->num_dw;
524 }
525
526 static inline void r600_set_atom_dirty(struct r600_context *rctx,
527 struct r600_atom *atom,
528 bool dirty)
529 {
530 uint64_t mask;
531
532 assert(atom->id != 0);
533 assert(atom->id < sizeof(mask) * 8);
534 mask = 1ull << atom->id;
535 if (dirty)
536 rctx->dirty_atoms |= mask;
537 else
538 rctx->dirty_atoms &= ~mask;
539 }
540
541 static inline void r600_mark_atom_dirty(struct r600_context *rctx,
542 struct r600_atom *atom)
543 {
544 r600_set_atom_dirty(rctx, atom, true);
545 }
546
547 static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
548 {
549 atom->emit(&rctx->b, atom);
550 r600_set_atom_dirty(rctx, atom, false);
551 }
552
553 static inline void r600_set_cso_state(struct r600_context *rctx,
554 struct r600_cso_state *state, void *cso)
555 {
556 state->cso = cso;
557 r600_set_atom_dirty(rctx, &state->atom, cso != NULL);
558 }
559
560 static inline void r600_set_cso_state_with_cb(struct r600_context *rctx,
561 struct r600_cso_state *state, void *cso,
562 struct r600_command_buffer *cb)
563 {
564 state->cb = cb;
565 state->atom.num_dw = cb ? cb->num_dw : 0;
566 r600_set_cso_state(rctx, state, cso);
567 }
568
569 /* compute_memory_pool.c */
570 struct compute_memory_pool;
571 void compute_memory_pool_delete(struct compute_memory_pool* pool);
572 struct compute_memory_pool* compute_memory_pool_new(
573 struct r600_screen *rscreen);
574
575 /* evergreen_state.c */
576 struct pipe_sampler_view *
577 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
578 struct pipe_resource *texture,
579 const struct pipe_sampler_view *state,
580 unsigned width0, unsigned height0,
581 unsigned force_level);
582 void evergreen_init_common_regs(struct r600_context *ctx,
583 struct r600_command_buffer *cb,
584 enum chip_class ctx_chip_class,
585 enum radeon_family ctx_family,
586 int ctx_drm_minor);
587 void cayman_init_common_regs(struct r600_command_buffer *cb,
588 enum chip_class ctx_chip_class,
589 enum radeon_family ctx_family,
590 int ctx_drm_minor);
591
592 void evergreen_init_state_functions(struct r600_context *rctx);
593 void evergreen_init_atom_start_cs(struct r600_context *rctx);
594 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
595 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
596 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
597 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
598 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
599 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
600 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
601 void *evergreen_create_resolve_blend(struct r600_context *rctx);
602 void *evergreen_create_decompress_blend(struct r600_context *rctx);
603 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
604 boolean evergreen_is_format_supported(struct pipe_screen *screen,
605 enum pipe_format format,
606 enum pipe_texture_target target,
607 unsigned sample_count,
608 unsigned usage);
609 void evergreen_init_color_surface(struct r600_context *rctx,
610 struct r600_surface *surf);
611 void evergreen_init_color_surface_rat(struct r600_context *rctx,
612 struct r600_surface *surf);
613 void evergreen_update_db_shader_control(struct r600_context * rctx);
614 bool evergreen_adjust_gprs(struct r600_context *rctx);
615 /* r600_blit.c */
616 void r600_init_blit_functions(struct r600_context *rctx);
617 void r600_decompress_depth_textures(struct r600_context *rctx,
618 struct r600_samplerview_state *textures);
619 void r600_decompress_color_textures(struct r600_context *rctx,
620 struct r600_samplerview_state *textures);
621 void r600_resource_copy_region(struct pipe_context *ctx,
622 struct pipe_resource *dst,
623 unsigned dst_level,
624 unsigned dstx, unsigned dsty, unsigned dstz,
625 struct pipe_resource *src,
626 unsigned src_level,
627 const struct pipe_box *src_box);
628
629 /* r600_shader.c */
630 int r600_pipe_shader_create(struct pipe_context *ctx,
631 struct r600_pipe_shader *shader,
632 union r600_shader_key key);
633
634 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
635
636 /* r600_state.c */
637 struct pipe_sampler_view *
638 r600_create_sampler_view_custom(struct pipe_context *ctx,
639 struct pipe_resource *texture,
640 const struct pipe_sampler_view *state,
641 unsigned width_first_level, unsigned height_first_level);
642 void r600_init_state_functions(struct r600_context *rctx);
643 void r600_init_atom_start_cs(struct r600_context *rctx);
644 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
645 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
646 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
647 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
648 void *r600_create_db_flush_dsa(struct r600_context *rctx);
649 void *r600_create_resolve_blend(struct r600_context *rctx);
650 void *r700_create_resolve_blend(struct r600_context *rctx);
651 void *r600_create_decompress_blend(struct r600_context *rctx);
652 bool r600_adjust_gprs(struct r600_context *rctx);
653 boolean r600_is_format_supported(struct pipe_screen *screen,
654 enum pipe_format format,
655 enum pipe_texture_target target,
656 unsigned sample_count,
657 unsigned usage);
658 void r600_update_db_shader_control(struct r600_context * rctx);
659
660 /* r600_hw_context.c */
661 void r600_context_gfx_flush(void *context, unsigned flags,
662 struct pipe_fence_handle **fence);
663 void r600_begin_new_cs(struct r600_context *ctx);
664 void r600_flush_emit(struct r600_context *ctx);
665 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
666 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
667 struct pipe_resource *dst, uint64_t dst_offset,
668 struct pipe_resource *src, uint64_t src_offset,
669 unsigned size);
670 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
671 struct pipe_resource *dst, uint64_t offset,
672 unsigned size, uint32_t clear_value);
673 void r600_dma_copy_buffer(struct r600_context *rctx,
674 struct pipe_resource *dst,
675 struct pipe_resource *src,
676 uint64_t dst_offset,
677 uint64_t src_offset,
678 uint64_t size);
679
680 /*
681 * evergreen_hw_context.c
682 */
683 void evergreen_dma_copy_buffer(struct r600_context *rctx,
684 struct pipe_resource *dst,
685 struct pipe_resource *src,
686 uint64_t dst_offset,
687 uint64_t src_offset,
688 uint64_t size);
689 void evergreen_setup_tess_constants(struct r600_context *rctx,
690 const struct pipe_draw_info *info,
691 unsigned *num_patches);
692 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
693 const struct pipe_draw_info *info,
694 unsigned num_patches);
695 void evergreen_set_ls_hs_config(struct r600_context *rctx,
696 struct radeon_winsys_cs *cs,
697 uint32_t ls_hs_config);
698 void evergreen_set_lds_alloc(struct r600_context *rctx,
699 struct radeon_winsys_cs *cs,
700 uint32_t lds_alloc);
701
702 /* r600_state_common.c */
703 void r600_init_common_state_functions(struct r600_context *rctx);
704 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
705 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
706 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
707 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
708 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
709 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
710 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
711 void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
712 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
713 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
714 unsigned num_dw);
715 void r600_vertex_buffers_dirty(struct r600_context *rctx);
716 void r600_sampler_views_dirty(struct r600_context *rctx,
717 struct r600_samplerview_state *state);
718 void r600_sampler_states_dirty(struct r600_context *rctx,
719 struct r600_sampler_states *state);
720 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
721 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
722 uint32_t r600_translate_stencil_op(int s_op);
723 uint32_t r600_translate_fill(uint32_t func);
724 unsigned r600_tex_wrap(unsigned wrap);
725 unsigned r600_tex_mipfilter(unsigned filter);
726 unsigned r600_tex_compare(unsigned compare);
727 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
728 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
729 struct pipe_resource *texture,
730 const struct pipe_surface *templ,
731 unsigned width, unsigned height);
732 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
733 const unsigned char *swizzle_view,
734 boolean vtx);
735 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
736 const unsigned char *swizzle_view,
737 uint32_t *word4_p, uint32_t *yuv_format_p);
738 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format);
739 uint32_t r600_colorformat_endian_swap(uint32_t colorformat);
740
741 /* r600_uvd.c */
742 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
743 const struct pipe_video_codec *decoder);
744
745 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
746 const struct pipe_video_buffer *tmpl);
747
748 /*
749 * Helpers for building command buffers
750 */
751
752 #define PKT3_SET_CONFIG_REG 0x68
753 #define PKT3_SET_CONTEXT_REG 0x69
754 #define PKT3_SET_CTL_CONST 0x6F
755 #define PKT3_SET_LOOP_CONST 0x6C
756
757 #define R600_CONFIG_REG_OFFSET 0x08000
758 #define R600_CONTEXT_REG_OFFSET 0x28000
759 #define R600_CTL_CONST_OFFSET 0x3CFF0
760 #define R600_LOOP_CONST_OFFSET 0X0003E200
761 #define EG_LOOP_CONST_OFFSET 0x0003A200
762
763 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
764 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
765 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
766 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
767 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
768
769 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
770
771 /*Evergreen Compute packet3*/
772 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
773
774 static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value)
775 {
776 cb->buf[cb->num_dw++] = value;
777 }
778
779 static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
780 {
781 assert(cb->num_dw+num <= cb->max_num_dw);
782 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
783 cb->num_dw += num;
784 }
785
786 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
787 {
788 assert(reg < R600_CONTEXT_REG_OFFSET);
789 assert(cb->num_dw+2+num <= cb->max_num_dw);
790 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
791 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
792 }
793
794 /**
795 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
796 * shaders.
797 */
798 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
799 {
800 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
801 assert(cb->num_dw+2+num <= cb->max_num_dw);
802 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
803 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
804 }
805
806 /**
807 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
808 * shaders.
809 */
810 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
811 {
812 assert(reg >= R600_CTL_CONST_OFFSET);
813 assert(cb->num_dw+2+num <= cb->max_num_dw);
814 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
815 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
816 }
817
818 static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
819 {
820 assert(reg >= R600_LOOP_CONST_OFFSET);
821 assert(cb->num_dw+2+num <= cb->max_num_dw);
822 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
823 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
824 }
825
826 /**
827 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
828 * shaders.
829 */
830 static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
831 {
832 assert(reg >= EG_LOOP_CONST_OFFSET);
833 assert(cb->num_dw+2+num <= cb->max_num_dw);
834 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
835 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
836 }
837
838 static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
839 {
840 r600_store_config_reg_seq(cb, reg, 1);
841 r600_store_value(cb, value);
842 }
843
844 static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
845 {
846 r600_store_context_reg_seq(cb, reg, 1);
847 r600_store_value(cb, value);
848 }
849
850 static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
851 {
852 r600_store_ctl_const_seq(cb, reg, 1);
853 r600_store_value(cb, value);
854 }
855
856 static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
857 {
858 r600_store_loop_const_seq(cb, reg, 1);
859 r600_store_value(cb, value);
860 }
861
862 static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
863 {
864 eg_store_loop_const_seq(cb, reg, 1);
865 r600_store_value(cb, value);
866 }
867
868 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
869 void r600_release_command_buffer(struct r600_command_buffer *cb);
870
871 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
872 {
873 radeon_set_context_reg_seq(cs, reg, num);
874 /* Set the compute bit on the packet header */
875 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
876 }
877
878 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
879 {
880 assert(reg >= R600_CTL_CONST_OFFSET);
881 assert(cs->cdw+2+num <= cs->max_dw);
882 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
883 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
884 }
885
886 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
887 {
888 radeon_compute_set_context_reg_seq(cs, reg, 1);
889 radeon_emit(cs, value);
890 }
891
892 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
893 {
894 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
895 radeon_compute_set_context_reg(cs, reg, value);
896 } else {
897 radeon_set_context_reg(cs, reg, value);
898 }
899 }
900
901 static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
902 {
903 radeon_set_ctl_const_seq(cs, reg, 1);
904 radeon_emit(cs, value);
905 }
906
907 /*
908 * common helpers
909 */
910 static inline uint32_t S_FIXED(float value, uint32_t frac_bits)
911 {
912 return value * (1 << frac_bits);
913 }
914
915 /* 12.4 fixed-point */
916 static inline unsigned r600_pack_float_12p4(float x)
917 {
918 return x <= 0 ? 0 :
919 x >= 4096 ? 0xffff : x * 16;
920 }
921
922 /* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */
923 static inline bool r600_can_read_depth(struct r600_texture *rtex)
924 {
925 return rtex->resource.b.b.nr_samples <= 1 &&
926 (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
927 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT);
928 }
929
930 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
931 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
932 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
933
934 unsigned r600_conv_prim_to_gs_out(unsigned mode);
935 #endif