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util: Move gallium's linked list to util
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "radeon/r600_pipe_common.h"
30 #include "radeon/r600_cs.h"
31
32 #include "r600_llvm.h"
33 #include "r600_public.h"
34
35 #include "util/u_suballoc.h"
36 #include "util/list.h"
37 #include "util/u_transfer.h"
38
39 #define R600_NUM_ATOMS 73
40
41 #define R600_MAX_VIEWPORTS 16
42
43 /* read caches */
44 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
45 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
46 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
47 /* read-write caches */
48 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
49 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
50 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
51 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
52 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
53 /* engine synchronization */
54 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
55 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
56 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
57
58 /* the number of CS dwords for flushing and drawing */
59 #define R600_MAX_FLUSH_CS_DWORDS 16
60 #define R600_MAX_DRAW_CS_DWORDS 47
61 #define R600_TRACE_CS_DWORDS 7
62
63 #define R600_MAX_USER_CONST_BUFFERS 13
64 #define R600_MAX_DRIVER_CONST_BUFFERS 3
65 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
66
67 /* start driver buffers after user buffers */
68 #define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
69 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
70 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
71 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
72 * of 16 const buffers.
73 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
74 *
75 * In order to support d3d 11 mandated minimum of 15 user const buffers
76 * we'd have to squash all use cases into one driver buffer.
77 */
78 #define R600_SAMPLE_POSITIONS_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
79
80 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
81
82 #ifdef PIPE_ARCH_BIG_ENDIAN
83 #define R600_BIG_ENDIAN 1
84 #else
85 #define R600_BIG_ENDIAN 0
86 #endif
87
88 struct r600_context;
89 struct r600_bytecode;
90 struct r600_shader_key;
91
92 /* This is an atom containing GPU commands that never change.
93 * This is supposed to be copied directly into the CS. */
94 struct r600_command_buffer {
95 uint32_t *buf;
96 unsigned num_dw;
97 unsigned max_num_dw;
98 unsigned pkt_flags;
99 };
100
101 struct r600_db_state {
102 struct r600_atom atom;
103 struct r600_surface *rsurf;
104 };
105
106 struct r600_db_misc_state {
107 struct r600_atom atom;
108 bool occlusion_query_enabled;
109 bool flush_depthstencil_through_cb;
110 bool flush_depthstencil_in_place;
111 bool copy_depth, copy_stencil;
112 unsigned copy_sample;
113 unsigned log_samples;
114 unsigned db_shader_control;
115 bool htile_clear;
116 };
117
118 struct r600_cb_misc_state {
119 struct r600_atom atom;
120 unsigned cb_color_control; /* this comes from blend state */
121 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
122 unsigned nr_cbufs;
123 unsigned nr_ps_color_outputs;
124 bool multiwrite;
125 bool dual_src_blend;
126 };
127
128 struct r600_clip_misc_state {
129 struct r600_atom atom;
130 unsigned pa_cl_clip_cntl; /* from rasterizer */
131 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
132 unsigned clip_plane_enable; /* from rasterizer */
133 unsigned clip_dist_write; /* from vertex shader */
134 boolean clip_disable; /* from vertex shader */
135 };
136
137 struct r600_alphatest_state {
138 struct r600_atom atom;
139 unsigned sx_alpha_test_control; /* this comes from dsa state */
140 unsigned sx_alpha_ref; /* this comes from dsa state */
141 bool bypass;
142 bool cb0_export_16bpc; /* from set_framebuffer_state */
143 };
144
145 struct r600_vgt_state {
146 struct r600_atom atom;
147 uint32_t vgt_multi_prim_ib_reset_en;
148 uint32_t vgt_multi_prim_ib_reset_indx;
149 uint32_t vgt_indx_offset;
150 bool last_draw_was_indirect;
151 };
152
153 struct r600_blend_color {
154 struct r600_atom atom;
155 struct pipe_blend_color state;
156 };
157
158 struct r600_clip_state {
159 struct r600_atom atom;
160 struct pipe_clip_state state;
161 };
162
163 struct r600_cs_shader_state {
164 struct r600_atom atom;
165 unsigned kernel_index;
166 unsigned pc;
167 struct r600_pipe_compute *shader;
168 };
169
170 struct r600_framebuffer {
171 struct r600_atom atom;
172 struct pipe_framebuffer_state state;
173 unsigned compressed_cb_mask;
174 unsigned nr_samples;
175 bool export_16bpc;
176 bool cb0_is_integer;
177 bool is_msaa_resolve;
178 };
179
180 struct r600_sample_mask {
181 struct r600_atom atom;
182 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
183 };
184
185 struct r600_config_state {
186 struct r600_atom atom;
187 unsigned sq_gpr_resource_mgmt_1;
188 unsigned sq_gpr_resource_mgmt_2;
189 };
190
191 struct r600_stencil_ref
192 {
193 ubyte ref_value[2];
194 ubyte valuemask[2];
195 ubyte writemask[2];
196 };
197
198 struct r600_stencil_ref_state {
199 struct r600_atom atom;
200 struct r600_stencil_ref state;
201 struct pipe_stencil_ref pipe_state;
202 };
203
204 struct r600_viewport_state {
205 struct r600_atom atom;
206 struct pipe_viewport_state state;
207 int idx;
208 };
209
210 struct r600_shader_stages_state {
211 struct r600_atom atom;
212 unsigned geom_enable;
213 };
214
215 struct r600_gs_rings_state {
216 struct r600_atom atom;
217 unsigned enable;
218 struct pipe_constant_buffer esgs_ring;
219 struct pipe_constant_buffer gsvs_ring;
220 };
221
222 /* This must start from 16. */
223 /* features */
224 #define DBG_LLVM (1 << 29)
225 #define DBG_NO_CP_DMA (1 << 30)
226 /* shader backend */
227 #define DBG_NO_SB (1 << 21)
228 #define DBG_SB_CS (1 << 22)
229 #define DBG_SB_DRY_RUN (1 << 23)
230 #define DBG_SB_STAT (1 << 24)
231 #define DBG_SB_DUMP (1 << 25)
232 #define DBG_SB_NO_FALLBACK (1 << 26)
233 #define DBG_SB_DISASM (1 << 27)
234 #define DBG_SB_SAFEMATH (1 << 28)
235
236 struct r600_screen {
237 struct r600_common_screen b;
238 bool has_msaa;
239 bool has_compressed_msaa_texturing;
240
241 /*for compute global memory binding, we allocate stuff here, instead of
242 * buffers.
243 * XXX: Not sure if this is the best place for global_pool. Also,
244 * it's not thread safe, so it won't work with multiple contexts. */
245 struct compute_memory_pool *global_pool;
246 };
247
248 struct r600_pipe_sampler_view {
249 struct pipe_sampler_view base;
250 struct list_head list;
251 struct r600_resource *tex_resource;
252 uint32_t tex_resource_words[8];
253 bool skip_mip_address_reloc;
254 };
255
256 struct r600_rasterizer_state {
257 struct r600_command_buffer buffer;
258 boolean flatshade;
259 boolean two_side;
260 unsigned sprite_coord_enable;
261 unsigned clip_plane_enable;
262 unsigned pa_sc_line_stipple;
263 unsigned pa_cl_clip_cntl;
264 unsigned pa_su_sc_mode_cntl;
265 float offset_units;
266 float offset_scale;
267 bool offset_enable;
268 bool scissor_enable;
269 bool multisample_enable;
270 };
271
272 struct r600_poly_offset_state {
273 struct r600_atom atom;
274 enum pipe_format zs_format;
275 float offset_units;
276 float offset_scale;
277 };
278
279 struct r600_blend_state {
280 struct r600_command_buffer buffer;
281 struct r600_command_buffer buffer_no_blend;
282 unsigned cb_target_mask;
283 unsigned cb_color_control;
284 unsigned cb_color_control_no_blend;
285 bool dual_src_blend;
286 bool alpha_to_one;
287 };
288
289 struct r600_dsa_state {
290 struct r600_command_buffer buffer;
291 unsigned alpha_ref;
292 ubyte valuemask[2];
293 ubyte writemask[2];
294 unsigned zwritemask;
295 unsigned sx_alpha_test_control;
296 };
297
298 struct r600_pipe_shader;
299
300 struct r600_pipe_shader_selector {
301 struct r600_pipe_shader *current;
302
303 struct tgsi_token *tokens;
304 struct pipe_stream_output_info so;
305
306 unsigned num_shaders;
307
308 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
309 unsigned type;
310
311 unsigned nr_ps_max_color_exports;
312 };
313
314 struct r600_pipe_sampler_state {
315 uint32_t tex_sampler_words[3];
316 union pipe_color_union border_color;
317 bool border_color_use;
318 bool seamless_cube_map;
319 };
320
321 /* needed for blitter save */
322 #define NUM_TEX_UNITS 16
323
324 struct r600_seamless_cube_map {
325 struct r600_atom atom;
326 bool enabled;
327 };
328
329 struct r600_samplerview_state {
330 struct r600_atom atom;
331 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
332 uint32_t enabled_mask;
333 uint32_t dirty_mask;
334 uint32_t compressed_depthtex_mask; /* which textures are depth */
335 uint32_t compressed_colortex_mask;
336 boolean dirty_buffer_constants;
337 };
338
339 struct r600_sampler_states {
340 struct r600_atom atom;
341 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
342 uint32_t enabled_mask;
343 uint32_t dirty_mask;
344 uint32_t has_bordercolor_mask; /* which states contain the border color */
345 };
346
347 struct r600_textures_info {
348 struct r600_samplerview_state views;
349 struct r600_sampler_states states;
350 bool is_array_sampler[NUM_TEX_UNITS];
351
352 /* cube array txq workaround */
353 uint32_t *txq_constants;
354 /* buffer related workarounds */
355 uint32_t *buffer_constants;
356 };
357
358 struct r600_constbuf_state
359 {
360 struct r600_atom atom;
361 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
362 uint32_t enabled_mask;
363 uint32_t dirty_mask;
364 };
365
366 struct r600_vertexbuf_state
367 {
368 struct r600_atom atom;
369 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
370 uint32_t enabled_mask; /* non-NULL buffers */
371 uint32_t dirty_mask;
372 };
373
374 /* CSO (constant state object, in other words, immutable state). */
375 struct r600_cso_state
376 {
377 struct r600_atom atom;
378 void *cso; /* e.g. r600_blend_state */
379 struct r600_command_buffer *cb;
380 };
381
382 struct r600_scissor_state
383 {
384 struct r600_atom atom;
385 struct pipe_scissor_state scissor;
386 bool enable; /* r6xx only */
387 int idx;
388 };
389
390 struct r600_fetch_shader {
391 struct r600_resource *buffer;
392 unsigned offset;
393 };
394
395 struct r600_shader_state {
396 struct r600_atom atom;
397 struct r600_pipe_shader *shader;
398 };
399
400 struct r600_context {
401 struct r600_common_context b;
402 struct r600_screen *screen;
403 struct blitter_context *blitter;
404 struct u_suballocator *allocator_fetch_shader;
405
406 /* Hardware info. */
407 boolean has_vertex_cache;
408 boolean keep_tiling_flags;
409 unsigned default_ps_gprs, default_vs_gprs;
410 unsigned r6xx_num_clause_temp_gprs;
411
412 /* Miscellaneous state objects. */
413 void *custom_dsa_flush;
414 void *custom_blend_resolve;
415 void *custom_blend_decompress;
416 void *custom_blend_fastclear;
417 /* With rasterizer discard, there doesn't have to be a pixel shader.
418 * In that case, we bind this one: */
419 void *dummy_pixel_shader;
420 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
421 * bug where valid CMASK and FMASK are required to be present to avoid
422 * a hardlock in certain operations but aren't actually used
423 * for anything useful. */
424 struct r600_resource *dummy_fmask;
425 struct r600_resource *dummy_cmask;
426
427 /* State binding slots are here. */
428 struct r600_atom *atoms[R600_NUM_ATOMS];
429 /* States for CS initialization. */
430 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
431 /** Compute specific registers initializations. The start_cs_cmd atom
432 * must be emitted before start_compute_cs_cmd. */
433 struct r600_command_buffer start_compute_cs_cmd;
434 /* Register states. */
435 struct r600_alphatest_state alphatest_state;
436 struct r600_cso_state blend_state;
437 struct r600_blend_color blend_color;
438 struct r600_cb_misc_state cb_misc_state;
439 struct r600_clip_misc_state clip_misc_state;
440 struct r600_clip_state clip_state;
441 struct r600_db_misc_state db_misc_state;
442 struct r600_db_state db_state;
443 struct r600_cso_state dsa_state;
444 struct r600_framebuffer framebuffer;
445 struct r600_poly_offset_state poly_offset_state;
446 struct r600_cso_state rasterizer_state;
447 struct r600_sample_mask sample_mask;
448 struct r600_scissor_state scissor[R600_MAX_VIEWPORTS];
449 struct r600_seamless_cube_map seamless_cube_map;
450 struct r600_config_state config_state;
451 struct r600_stencil_ref_state stencil_ref;
452 struct r600_vgt_state vgt_state;
453 struct r600_viewport_state viewport[R600_MAX_VIEWPORTS];
454 /* Shaders and shader resources. */
455 struct r600_cso_state vertex_fetch_shader;
456 struct r600_shader_state vertex_shader;
457 struct r600_shader_state pixel_shader;
458 struct r600_shader_state geometry_shader;
459 struct r600_shader_state export_shader;
460 struct r600_cs_shader_state cs_shader_state;
461 struct r600_shader_stages_state shader_stages;
462 struct r600_gs_rings_state gs_rings;
463 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
464 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
465 /** Vertex buffers for fetch shaders */
466 struct r600_vertexbuf_state vertex_buffer_state;
467 /** Vertex buffers for compute shaders */
468 struct r600_vertexbuf_state cs_vertex_buffer_state;
469
470 /* Additional context states. */
471 unsigned compute_cb_target_mask;
472 struct r600_pipe_shader_selector *ps_shader;
473 struct r600_pipe_shader_selector *vs_shader;
474 struct r600_pipe_shader_selector *gs_shader;
475 struct r600_rasterizer_state *rasterizer;
476 bool alpha_to_one;
477 bool force_blend_disable;
478 boolean dual_src_blend;
479 unsigned zwritemask;
480 int ps_iter_samples;
481
482 /* Index buffer. */
483 struct pipe_index_buffer index_buffer;
484
485 /* Last draw state (-1 = unset). */
486 int last_primitive_type; /* Last primitive type used in draw_vbo. */
487 int last_start_instance;
488
489 void *sb_context;
490 struct r600_isa *isa;
491 };
492
493 static INLINE void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
494 struct r600_command_buffer *cb)
495 {
496 assert(cs->cdw + cb->num_dw <= RADEON_MAX_CMDBUF_DWORDS);
497 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->num_dw);
498 cs->cdw += cb->num_dw;
499 }
500
501 void r600_trace_emit(struct r600_context *rctx);
502
503 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
504 {
505 atom->emit(&rctx->b, atom);
506 atom->dirty = false;
507 if (rctx->screen->b.trace_bo) {
508 r600_trace_emit(rctx);
509 }
510 }
511
512 static INLINE void r600_set_cso_state(struct r600_cso_state *state, void *cso)
513 {
514 state->cso = cso;
515 state->atom.dirty = cso != NULL;
516 }
517
518 static INLINE void r600_set_cso_state_with_cb(struct r600_cso_state *state, void *cso,
519 struct r600_command_buffer *cb)
520 {
521 state->cb = cb;
522 state->atom.num_dw = cb ? cb->num_dw : 0;
523 r600_set_cso_state(state, cso);
524 }
525
526 /* compute_memory_pool.c */
527 struct compute_memory_pool;
528 void compute_memory_pool_delete(struct compute_memory_pool* pool);
529 struct compute_memory_pool* compute_memory_pool_new(
530 struct r600_screen *rscreen);
531
532 /* evergreen_compute.c */
533 void evergreen_set_cs_sampler_view(struct pipe_context *ctx_,
534 unsigned start_slot, unsigned count,
535 struct pipe_sampler_view **views);
536
537 /* evergreen_state.c */
538 struct pipe_sampler_view *
539 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
540 struct pipe_resource *texture,
541 const struct pipe_sampler_view *state,
542 unsigned width0, unsigned height0,
543 unsigned force_level);
544 void evergreen_init_common_regs(struct r600_command_buffer *cb,
545 enum chip_class ctx_chip_class,
546 enum radeon_family ctx_family,
547 int ctx_drm_minor);
548 void cayman_init_common_regs(struct r600_command_buffer *cb,
549 enum chip_class ctx_chip_class,
550 enum radeon_family ctx_family,
551 int ctx_drm_minor);
552
553 void evergreen_init_state_functions(struct r600_context *rctx);
554 void evergreen_init_atom_start_cs(struct r600_context *rctx);
555 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
556 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
557 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
558 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
559 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
560 void *evergreen_create_resolve_blend(struct r600_context *rctx);
561 void *evergreen_create_decompress_blend(struct r600_context *rctx);
562 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
563 boolean evergreen_is_format_supported(struct pipe_screen *screen,
564 enum pipe_format format,
565 enum pipe_texture_target target,
566 unsigned sample_count,
567 unsigned usage);
568 void evergreen_init_color_surface(struct r600_context *rctx,
569 struct r600_surface *surf);
570 void evergreen_init_color_surface_rat(struct r600_context *rctx,
571 struct r600_surface *surf);
572 void evergreen_update_db_shader_control(struct r600_context * rctx);
573
574 /* r600_blit.c */
575 void r600_init_blit_functions(struct r600_context *rctx);
576 void r600_decompress_depth_textures(struct r600_context *rctx,
577 struct r600_samplerview_state *textures);
578 void r600_decompress_color_textures(struct r600_context *rctx,
579 struct r600_samplerview_state *textures);
580 void r600_resource_copy_region(struct pipe_context *ctx,
581 struct pipe_resource *dst,
582 unsigned dst_level,
583 unsigned dstx, unsigned dsty, unsigned dstz,
584 struct pipe_resource *src,
585 unsigned src_level,
586 const struct pipe_box *src_box);
587
588 /* r600_shader.c */
589 int r600_pipe_shader_create(struct pipe_context *ctx,
590 struct r600_pipe_shader *shader,
591 struct r600_shader_key key);
592
593 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
594
595 /* r600_state.c */
596 struct pipe_sampler_view *
597 r600_create_sampler_view_custom(struct pipe_context *ctx,
598 struct pipe_resource *texture,
599 const struct pipe_sampler_view *state,
600 unsigned width_first_level, unsigned height_first_level);
601 void r600_init_state_functions(struct r600_context *rctx);
602 void r600_init_atom_start_cs(struct r600_context *rctx);
603 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
604 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
605 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
606 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
607 void *r600_create_db_flush_dsa(struct r600_context *rctx);
608 void *r600_create_resolve_blend(struct r600_context *rctx);
609 void *r700_create_resolve_blend(struct r600_context *rctx);
610 void *r600_create_decompress_blend(struct r600_context *rctx);
611 bool r600_adjust_gprs(struct r600_context *rctx);
612 boolean r600_is_format_supported(struct pipe_screen *screen,
613 enum pipe_format format,
614 enum pipe_texture_target target,
615 unsigned sample_count,
616 unsigned usage);
617 void r600_update_db_shader_control(struct r600_context * rctx);
618
619 /* r600_hw_context.c */
620 void r600_context_gfx_flush(void *context, unsigned flags,
621 struct pipe_fence_handle **fence);
622 void r600_begin_new_cs(struct r600_context *ctx);
623 void r600_flush_emit(struct r600_context *ctx);
624 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
625 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
626 struct pipe_resource *dst, uint64_t dst_offset,
627 struct pipe_resource *src, uint64_t src_offset,
628 unsigned size);
629 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
630 struct pipe_resource *dst, uint64_t offset,
631 unsigned size, uint32_t clear_value);
632 void r600_dma_copy_buffer(struct r600_context *rctx,
633 struct pipe_resource *dst,
634 struct pipe_resource *src,
635 uint64_t dst_offset,
636 uint64_t src_offset,
637 uint64_t size);
638
639 /*
640 * evergreen_hw_context.c
641 */
642 void evergreen_dma_copy_buffer(struct r600_context *rctx,
643 struct pipe_resource *dst,
644 struct pipe_resource *src,
645 uint64_t dst_offset,
646 uint64_t src_offset,
647 uint64_t size);
648
649 /* r600_state_common.c */
650 void r600_init_common_state_functions(struct r600_context *rctx);
651 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
652 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
653 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
654 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
655 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
656 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
657 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom);
658 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
659 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
660 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
661 unsigned num_dw);
662 void r600_vertex_buffers_dirty(struct r600_context *rctx);
663 void r600_sampler_views_dirty(struct r600_context *rctx,
664 struct r600_samplerview_state *state);
665 void r600_sampler_states_dirty(struct r600_context *rctx,
666 struct r600_sampler_states *state);
667 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
668 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
669 uint32_t r600_translate_stencil_op(int s_op);
670 uint32_t r600_translate_fill(uint32_t func);
671 unsigned r600_tex_wrap(unsigned wrap);
672 unsigned r600_tex_filter(unsigned filter);
673 unsigned r600_tex_mipfilter(unsigned filter);
674 unsigned r600_tex_compare(unsigned compare);
675 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
676 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
677 struct pipe_resource *texture,
678 const struct pipe_surface *templ,
679 unsigned width, unsigned height);
680 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
681 const unsigned char *swizzle_view,
682 boolean vtx);
683 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
684 const unsigned char *swizzle_view,
685 uint32_t *word4_p, uint32_t *yuv_format_p);
686 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format);
687 uint32_t r600_colorformat_endian_swap(uint32_t colorformat);
688
689 /* r600_uvd.c */
690 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
691 const struct pipe_video_codec *decoder);
692
693 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
694 const struct pipe_video_buffer *tmpl);
695
696 /*
697 * Helpers for building command buffers
698 */
699
700 #define PKT3_SET_CONFIG_REG 0x68
701 #define PKT3_SET_CONTEXT_REG 0x69
702 #define PKT3_SET_CTL_CONST 0x6F
703 #define PKT3_SET_LOOP_CONST 0x6C
704
705 #define R600_CONFIG_REG_OFFSET 0x08000
706 #define R600_CONTEXT_REG_OFFSET 0x28000
707 #define R600_CTL_CONST_OFFSET 0x3CFF0
708 #define R600_LOOP_CONST_OFFSET 0X0003E200
709 #define EG_LOOP_CONST_OFFSET 0x0003A200
710
711 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
712 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
713 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
714 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
715 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
716
717 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
718
719 /*Evergreen Compute packet3*/
720 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
721
722 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
723 {
724 cb->buf[cb->num_dw++] = value;
725 }
726
727 static INLINE void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
728 {
729 assert(cb->num_dw+num <= cb->max_num_dw);
730 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
731 cb->num_dw += num;
732 }
733
734 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
735 {
736 assert(reg < R600_CONTEXT_REG_OFFSET);
737 assert(cb->num_dw+2+num <= cb->max_num_dw);
738 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
739 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
740 }
741
742 /**
743 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
744 * shaders.
745 */
746 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
747 {
748 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
749 assert(cb->num_dw+2+num <= cb->max_num_dw);
750 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
751 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
752 }
753
754 /**
755 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
756 * shaders.
757 */
758 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
759 {
760 assert(reg >= R600_CTL_CONST_OFFSET);
761 assert(cb->num_dw+2+num <= cb->max_num_dw);
762 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
763 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
764 }
765
766 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
767 {
768 assert(reg >= R600_LOOP_CONST_OFFSET);
769 assert(cb->num_dw+2+num <= cb->max_num_dw);
770 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
771 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
772 }
773
774 /**
775 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
776 * shaders.
777 */
778 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
779 {
780 assert(reg >= EG_LOOP_CONST_OFFSET);
781 assert(cb->num_dw+2+num <= cb->max_num_dw);
782 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
783 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
784 }
785
786 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
787 {
788 r600_store_config_reg_seq(cb, reg, 1);
789 r600_store_value(cb, value);
790 }
791
792 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
793 {
794 r600_store_context_reg_seq(cb, reg, 1);
795 r600_store_value(cb, value);
796 }
797
798 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
799 {
800 r600_store_ctl_const_seq(cb, reg, 1);
801 r600_store_value(cb, value);
802 }
803
804 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
805 {
806 r600_store_loop_const_seq(cb, reg, 1);
807 r600_store_value(cb, value);
808 }
809
810 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
811 {
812 eg_store_loop_const_seq(cb, reg, 1);
813 r600_store_value(cb, value);
814 }
815
816 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
817 void r600_release_command_buffer(struct r600_command_buffer *cb);
818
819 static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
820 {
821 r600_write_context_reg_seq(cs, reg, num);
822 /* Set the compute bit on the packet header */
823 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
824 }
825
826 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
827 {
828 assert(reg >= R600_CTL_CONST_OFFSET);
829 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
830 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
831 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
832 }
833
834 static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
835 {
836 r600_write_compute_context_reg_seq(cs, reg, 1);
837 radeon_emit(cs, value);
838 }
839
840 static INLINE void r600_write_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
841 {
842 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
843 r600_write_compute_context_reg(cs, reg, value);
844 } else {
845 r600_write_context_reg(cs, reg, value);
846 }
847 }
848
849 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
850 {
851 r600_write_ctl_const_seq(cs, reg, 1);
852 radeon_emit(cs, value);
853 }
854
855 /*
856 * common helpers
857 */
858 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
859 {
860 return value * (1 << frac_bits);
861 }
862 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
863
864 /* 12.4 fixed-point */
865 static INLINE unsigned r600_pack_float_12p4(float x)
866 {
867 return x <= 0 ? 0 :
868 x >= 4096 ? 0xffff : x * 16;
869 }
870
871 /* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */
872 static INLINE bool r600_can_read_depth(struct r600_texture *rtex)
873 {
874 return rtex->resource.b.b.nr_samples <= 1 &&
875 (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
876 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT);
877 }
878
879 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
880 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
881 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
882
883 static INLINE unsigned r600_conv_prim_to_gs_out(unsigned mode)
884 {
885 static const int prim_conv[] = {
886 V_028A6C_OUTPRIM_TYPE_POINTLIST,
887 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
888 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
889 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
890 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
891 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
892 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
893 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
894 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
895 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
896 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
897 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
898 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
899 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
900 V_028A6C_OUTPRIM_TYPE_TRISTRIP
901 };
902 assert(mode < Elements(prim_conv));
903
904 return prim_conv[mode];
905 }
906
907 #endif