2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "util/u_slab.h"
31 #include "r600_llvm.h"
32 #include "r600_public.h"
33 #include "r600_shader.h"
34 #include "r600_resource.h"
35 #include "evergreen_compute.h"
37 #define R600_MAX_CONST_BUFFERS 2
38 #define R600_MAX_CONST_BUFFER_SIZE 4096
40 #ifdef PIPE_ARCH_BIG_ENDIAN
41 #define R600_BIG_ENDIAN 1
43 #define R600_BIG_ENDIAN 0
46 enum r600_atom_flags
{
47 /* When set, atoms are added at the beginning of the dirty list
48 * instead of the end. */
52 /* This encapsulates a state or an operation which can emitted into the GPU
53 * command stream. It's not limited to states only, it can be used for anything
54 * that wants to write commands into the CS (e.g. cache flushes). */
56 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
);
59 enum r600_atom_flags flags
;
62 struct list_head head
;
65 /* This is an atom containing GPU commands that never change.
66 * This is supposed to be copied directly into the CS. */
67 struct r600_command_buffer
{
68 struct r600_atom atom
;
73 struct r600_surface_sync_cmd
{
74 struct r600_atom atom
;
75 unsigned flush_flags
; /* CP_COHER_CNTL */
78 struct r600_db_misc_state
{
79 struct r600_atom atom
;
80 bool occlusion_query_enabled
;
81 bool flush_depthstencil_enabled
;
84 enum r600_pipe_state_id
{
85 R600_PIPE_STATE_BLEND
= 0,
86 R600_PIPE_STATE_BLEND_COLOR
,
87 R600_PIPE_STATE_CONFIG
,
88 R600_PIPE_STATE_SEAMLESS_CUBEMAP
,
90 R600_PIPE_STATE_SCISSOR
,
91 R600_PIPE_STATE_VIEWPORT
,
92 R600_PIPE_STATE_RASTERIZER
,
94 R600_PIPE_STATE_FRAMEBUFFER
,
96 R600_PIPE_STATE_STENCIL_REF
,
97 R600_PIPE_STATE_PS_SHADER
,
98 R600_PIPE_STATE_VS_SHADER
,
99 R600_PIPE_STATE_CONSTANT
,
100 R600_PIPE_STATE_SAMPLER
,
101 R600_PIPE_STATE_RESOURCE
,
102 R600_PIPE_STATE_POLYGON_OFFSET
,
103 R600_PIPE_STATE_FETCH_SHADER
,
108 struct compute_memory_pool
;
109 void compute_memory_pool_delete(struct compute_memory_pool
* pool
);
110 struct compute_memory_pool
* compute_memory_pool_new(
111 int64_t initial_size_in_dw
,
112 struct r600_screen
*rscreen
);
114 struct r600_pipe_fences
{
115 struct r600_resource
*bo
;
118 /* linked list of preallocated blocks */
119 struct list_head blocks
;
120 /* linked list of freed fences */
121 struct list_head pool
;
126 struct pipe_screen screen
;
127 struct radeon_winsys
*ws
;
129 enum chip_class chip_class
;
130 struct radeon_info info
;
132 struct r600_tiling_info tiling_info
;
133 struct r600_pipe_fences fences
;
135 bool use_surface_alloc
;
136 int glsl_feature_level
;
138 /*for compute global memory binding, we allocate stuff here, instead of
140 * XXX: Not sure if this is the best place for global_pool. Also,
141 * it's not thread safe, so it won't work with multiple contexts. */
142 struct compute_memory_pool
*global_pool
;
145 struct r600_pipe_sampler_view
{
146 struct pipe_sampler_view base
;
147 struct r600_pipe_resource_state state
;
150 struct r600_pipe_rasterizer
{
151 struct r600_pipe_state rstate
;
154 unsigned sprite_coord_enable
;
155 unsigned clip_plane_enable
;
156 unsigned pa_sc_line_stipple
;
157 unsigned pa_cl_clip_cntl
;
163 struct r600_pipe_blend
{
164 struct r600_pipe_state rstate
;
165 unsigned cb_target_mask
;
166 unsigned cb_color_control
;
170 struct r600_pipe_dsa
{
171 struct r600_pipe_state rstate
;
176 unsigned sx_alpha_test_control
;
179 struct r600_vertex_element
182 struct pipe_vertex_element elements
[PIPE_MAX_ATTRIBS
];
183 struct r600_resource
*fetch_shader
;
185 struct r600_pipe_state rstate
;
188 struct r600_pipe_shader
;
190 struct r600_pipe_shader_selector
{
191 struct r600_pipe_shader
*current
;
193 struct tgsi_token
*tokens
;
194 struct pipe_stream_output_info so
;
196 unsigned num_shaders
;
198 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
201 /* 1 on evergreen+ when the shader contains
202 * TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS, otherwise it's 0.
203 * Used to determine whether we need to include nr_cbufs in the key */
204 unsigned eg_fs_write_all
;
207 struct r600_pipe_shader
{
208 struct r600_pipe_shader_selector
*selector
;
209 struct r600_pipe_shader
*next_variant
;
210 struct r600_shader shader
;
211 struct r600_pipe_state rstate
;
212 struct r600_resource
*bo
;
213 struct r600_resource
*bo_fetch
;
214 struct r600_vertex_element vertex_elements
;
215 unsigned sprite_coord_enable
;
217 unsigned pa_cl_vs_out_cntl
;
218 unsigned ps_cb_shader_mask
;
222 struct r600_pipe_sampler_state
{
223 struct r600_pipe_state rstate
;
224 boolean seamless_cube_map
;
227 /* needed for blitter save */
228 #define NUM_TEX_UNITS 16
230 struct r600_textures_info
{
231 struct r600_pipe_sampler_view
*views
[NUM_TEX_UNITS
];
232 struct r600_pipe_sampler_state
*samplers
[NUM_TEX_UNITS
];
236 bool is_array_sampler
[NUM_TEX_UNITS
];
240 struct pipe_reference reference
;
241 unsigned index
; /* in the shared bo */
242 struct r600_resource
*sleep_bo
;
243 struct list_head head
;
246 #define FENCE_BLOCK_SIZE 16
248 struct r600_fence_block
{
249 struct r600_fence fences
[FENCE_BLOCK_SIZE
];
250 struct list_head head
;
253 #define R600_CONSTANT_ARRAY_SIZE 256
254 #define R600_RESOURCE_ARRAY_SIZE 160
256 struct r600_stencil_ref
263 struct r600_constbuf_state
265 struct r600_atom atom
;
266 struct pipe_constant_buffer cb
[PIPE_MAX_CONSTANT_BUFFERS
];
267 uint32_t enabled_mask
;
271 struct r600_context
{
272 struct pipe_context context
;
273 struct blitter_context
*blitter
;
274 enum radeon_family family
;
275 enum chip_class chip_class
;
276 boolean has_vertex_cache
;
277 unsigned r6xx_num_clause_temp_gprs
;
278 void *custom_dsa_flush
;
279 struct r600_screen
*screen
;
280 struct radeon_winsys
*ws
;
281 struct r600_pipe_state
*states
[R600_PIPE_NSTATES
];
282 struct r600_vertex_element
*vertex_elements
;
283 struct pipe_framebuffer_state framebuffer
;
284 unsigned cb_target_mask
;
285 unsigned fb_cb_shader_mask
;
286 unsigned sx_alpha_test_control
;
287 unsigned cb_shader_mask
;
288 unsigned cb_color_control
;
289 unsigned pa_sc_line_stipple
;
290 unsigned pa_cl_clip_cntl
;
291 /* for saving when using blitter */
292 struct pipe_stencil_ref stencil_ref
;
293 struct pipe_viewport_state viewport
;
294 struct pipe_clip_state clip
;
295 struct r600_pipe_shader_selector
*ps_shader
;
296 struct r600_pipe_shader_selector
*vs_shader
;
297 struct r600_pipe_compute
*cs_shader
;
298 struct r600_pipe_rasterizer
*rasterizer
;
299 struct r600_pipe_state vgt
;
300 struct r600_pipe_state spi
;
301 struct pipe_query
*current_render_cond
;
302 unsigned current_render_cond_mode
;
303 struct pipe_query
*saved_render_cond
;
304 unsigned saved_render_cond_mode
;
305 /* shader information */
308 unsigned sprite_coord_enable
;
310 boolean export_16bpc
;
312 boolean alpha_ref_dirty
;
314 struct r600_textures_info vs_samplers
;
315 struct r600_textures_info ps_samplers
;
317 struct u_upload_mgr
*uploader
;
318 struct util_slab_mempool pool_transfers
;
319 boolean have_depth_texture
, have_depth_fb
;
321 unsigned default_ps_gprs
, default_vs_gprs
;
323 /* States based on r600_atom. */
324 struct list_head dirty_states
;
325 struct r600_command_buffer start_cs_cmd
; /* invariant state mostly */
326 struct r600_surface_sync_cmd surface_sync_cmd
;
327 struct r600_atom r6xx_flush_and_inv_cmd
;
328 struct r600_db_misc_state db_misc_state
;
329 struct r600_atom vertex_buffer_state
;
330 struct r600_constbuf_state vs_constbuf_state
;
331 struct r600_constbuf_state ps_constbuf_state
;
333 struct radeon_winsys_cs
*cs
;
335 struct r600_range
*range
;
337 struct r600_block
**blocks
;
338 struct list_head dirty
;
339 struct list_head resource_dirty
;
340 struct list_head enable_list
;
341 unsigned pm4_dirty_cdwords
;
342 unsigned ctx_pm4_ndwords
;
344 /* The list of active queries. Only one query of each type can be active. */
345 int num_occlusion_queries
;
347 /* Manage queries in two separate groups:
348 * The timer ones and the others (streamout, occlusion).
350 * We do this because we should only suspend non-timer queries for u_blitter,
351 * and later if the non-timer queries are suspended, the context flush should
352 * only suspend and resume the timer queries. */
353 struct list_head active_timer_queries
;
354 unsigned num_cs_dw_timer_queries_suspend
;
355 struct list_head active_nontimer_queries
;
356 unsigned num_cs_dw_nontimer_queries_suspend
;
358 unsigned num_cs_dw_streamout_end
;
360 unsigned backend_mask
;
361 unsigned max_db
; /* for OQ */
363 boolean predicate_drawing
;
364 struct r600_range ps_resources
;
365 struct r600_range vs_resources
;
366 int num_ps_resources
, num_vs_resources
;
368 unsigned num_so_targets
;
369 struct r600_so_target
*so_targets
[PIPE_MAX_SO_BUFFERS
];
370 boolean streamout_start
;
371 unsigned streamout_append_bitmask
;
373 /* There is no scissor enable bit on r6xx, so we must use a workaround.
374 * These track the current scissor state. */
376 struct pipe_scissor_state scissor_state
;
378 /* With rasterizer discard, there doesn't have to be a pixel shader.
379 * In that case, we bind this one: */
380 void *dummy_pixel_shader
;
382 boolean dual_src_blend
;
384 /* Vertex and index buffers. */
385 bool vertex_buffers_dirty
;
386 struct pipe_index_buffer index_buffer
;
387 struct pipe_vertex_buffer vertex_buffer
[PIPE_MAX_ATTRIBS
];
388 unsigned nr_vertex_buffers
;
391 static INLINE
void r600_emit_atom(struct r600_context
*rctx
, struct r600_atom
*atom
)
393 atom
->emit(rctx
, atom
);
395 if (atom
->head
.next
&& atom
->head
.prev
)
396 LIST_DELINIT(&atom
->head
);
399 static INLINE
void r600_atom_dirty(struct r600_context
*rctx
, struct r600_atom
*state
)
402 if (state
->flags
& EMIT_EARLY
) {
403 LIST_ADD(&state
->head
, &rctx
->dirty_states
);
405 LIST_ADDTAIL(&state
->head
, &rctx
->dirty_states
);
411 /* evergreen_state.c */
412 void evergreen_init_state_functions(struct r600_context
*rctx
);
413 void evergreen_init_atom_start_cs(struct r600_context
*rctx
);
414 void evergreen_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
415 void evergreen_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
416 void evergreen_fetch_shader(struct pipe_context
*ctx
, struct r600_vertex_element
*ve
);
417 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
);
418 void evergreen_polygon_offset_update(struct r600_context
*rctx
);
419 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
420 enum pipe_format format
,
421 enum pipe_texture_target target
,
422 unsigned sample_count
,
426 void r600_init_blit_functions(struct r600_context
*rctx
);
427 void r600_blit_uncompress_depth(struct pipe_context
*ctx
, struct r600_resource_texture
*texture
);
428 void r600_flush_depth_textures(struct r600_context
*rctx
);
431 bool r600_init_resource(struct r600_screen
*rscreen
,
432 struct r600_resource
*res
,
433 unsigned size
, unsigned alignment
,
434 unsigned bind
, unsigned usage
);
435 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
436 const struct pipe_resource
*templ
);
439 void r600_flush(struct pipe_context
*ctx
, struct pipe_fence_handle
**fence
,
443 void r600_init_query_functions(struct r600_context
*rctx
);
444 void r600_suspend_nontimer_queries(struct r600_context
*ctx
);
445 void r600_resume_nontimer_queries(struct r600_context
*ctx
);
446 void r600_suspend_timer_queries(struct r600_context
*ctx
);
447 void r600_resume_timer_queries(struct r600_context
*ctx
);
449 /* r600_resource.c */
450 void r600_init_context_resource_functions(struct r600_context
*r600
);
453 int r600_pipe_shader_create(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
455 int r600_compute_shader_create(struct pipe_context
* ctx
,
456 LLVMModuleRef mod
, struct r600_bytecode
* bytecode
);
458 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
461 void r600_set_scissor_state(struct r600_context
*rctx
,
462 const struct pipe_scissor_state
*state
);
463 void r600_update_sampler_states(struct r600_context
*rctx
);
464 void r600_init_state_functions(struct r600_context
*rctx
);
465 void r600_init_atom_start_cs(struct r600_context
*rctx
);
466 void r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
467 void r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
468 void r600_fetch_shader(struct pipe_context
*ctx
, struct r600_vertex_element
*ve
);
469 void *r600_create_db_flush_dsa(struct r600_context
*rctx
);
470 void r600_polygon_offset_update(struct r600_context
*rctx
);
471 void r600_adjust_gprs(struct r600_context
*rctx
);
472 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
473 enum pipe_format format
,
474 enum pipe_texture_target target
,
475 unsigned sample_count
,
479 void r600_init_screen_texture_functions(struct pipe_screen
*screen
);
480 void r600_init_surface_functions(struct r600_context
*r600
);
481 uint32_t r600_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
482 const unsigned char *swizzle_view
,
483 uint32_t *word4_p
, uint32_t *yuv_format_p
);
484 unsigned r600_texture_get_offset(struct r600_resource_texture
*rtex
,
485 unsigned level
, unsigned layer
);
487 /* r600_translate.c */
488 void r600_translate_index_buffer(struct r600_context
*r600
,
489 struct pipe_index_buffer
*ib
,
492 /* r600_state_common.c */
493 void r600_init_atom(struct r600_atom
*atom
,
494 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
495 unsigned num_dw
, enum r600_atom_flags flags
);
496 void r600_init_common_atoms(struct r600_context
*rctx
);
497 unsigned r600_get_cb_flush_flags(struct r600_context
*rctx
);
498 void r600_texture_barrier(struct pipe_context
*ctx
);
499 void r600_set_index_buffer(struct pipe_context
*ctx
,
500 const struct pipe_index_buffer
*ib
);
501 void r600_set_vertex_buffers(struct pipe_context
*ctx
, unsigned count
,
502 const struct pipe_vertex_buffer
*buffers
);
503 void *r600_create_vertex_elements(struct pipe_context
*ctx
,
505 const struct pipe_vertex_element
*elements
);
506 void r600_delete_vertex_element(struct pipe_context
*ctx
, void *state
);
507 void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
);
508 void r600_set_blend_color(struct pipe_context
*ctx
,
509 const struct pipe_blend_color
*state
);
510 void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
);
511 void r600_set_max_scissor(struct r600_context
*rctx
);
512 void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
);
513 void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
);
514 void r600_sampler_view_destroy(struct pipe_context
*ctx
,
515 struct pipe_sampler_view
*state
);
516 void r600_delete_state(struct pipe_context
*ctx
, void *state
);
517 void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
);
518 void *r600_create_shader_state_ps(struct pipe_context
*ctx
,
519 const struct pipe_shader_state
*state
);
520 void *r600_create_shader_state_vs(struct pipe_context
*ctx
,
521 const struct pipe_shader_state
*state
);
522 void r600_bind_ps_shader(struct pipe_context
*ctx
, void *state
);
523 void r600_bind_vs_shader(struct pipe_context
*ctx
, void *state
);
524 void r600_delete_ps_shader(struct pipe_context
*ctx
, void *state
);
525 void r600_delete_vs_shader(struct pipe_context
*ctx
, void *state
);
526 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
);
527 void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
528 struct pipe_constant_buffer
*cb
);
529 struct pipe_stream_output_target
*
530 r600_create_so_target(struct pipe_context
*ctx
,
531 struct pipe_resource
*buffer
,
532 unsigned buffer_offset
,
533 unsigned buffer_size
);
534 void r600_so_target_destroy(struct pipe_context
*ctx
,
535 struct pipe_stream_output_target
*target
);
536 void r600_set_so_targets(struct pipe_context
*ctx
,
537 unsigned num_targets
,
538 struct pipe_stream_output_target
**targets
,
539 unsigned append_bitmask
);
540 void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
541 const struct pipe_stencil_ref
*state
);
542 void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
);
543 uint32_t r600_translate_stencil_op(int s_op
);
544 uint32_t r600_translate_fill(uint32_t func
);
545 unsigned r600_tex_wrap(unsigned wrap
);
546 unsigned r600_tex_filter(unsigned filter
);
547 unsigned r600_tex_mipfilter(unsigned filter
);
548 unsigned r600_tex_compare(unsigned compare
);
551 * Helpers for building command buffers
554 #define PKT3_SET_CONFIG_REG 0x68
555 #define PKT3_SET_CONTEXT_REG 0x69
556 #define PKT3_SET_CTL_CONST 0x6F
557 #define PKT3_SET_LOOP_CONST 0x6C
559 #define R600_CONFIG_REG_OFFSET 0x08000
560 #define R600_CONTEXT_REG_OFFSET 0x28000
561 #define R600_CTL_CONST_OFFSET 0x3CFF0
562 #define R600_LOOP_CONST_OFFSET 0X0003E200
563 #define EG_LOOP_CONST_OFFSET 0x0003A200
565 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
566 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
567 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
568 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
569 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
571 static INLINE
void r600_store_value(struct r600_command_buffer
*cb
, unsigned value
)
573 cb
->buf
[cb
->atom
.num_dw
++] = value
;
576 static INLINE
void r600_store_config_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
578 assert(reg
< R600_CONTEXT_REG_OFFSET
);
579 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
580 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
581 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
584 static INLINE
void r600_store_context_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
586 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
587 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
588 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0);
589 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
592 static INLINE
void r600_store_ctl_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
594 assert(reg
>= R600_CTL_CONST_OFFSET
);
595 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
596 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0);
597 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
600 static INLINE
void r600_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
602 assert(reg
>= R600_LOOP_CONST_OFFSET
);
603 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
604 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0);
605 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_LOOP_CONST_OFFSET
) >> 2;
608 static INLINE
void eg_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
610 assert(reg
>= EG_LOOP_CONST_OFFSET
);
611 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
612 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0);
613 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- EG_LOOP_CONST_OFFSET
) >> 2;
616 static INLINE
void r600_store_config_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
618 r600_store_config_reg_seq(cb
, reg
, 1);
619 r600_store_value(cb
, value
);
622 static INLINE
void r600_store_context_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
624 r600_store_context_reg_seq(cb
, reg
, 1);
625 r600_store_value(cb
, value
);
628 static INLINE
void r600_store_ctl_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
630 r600_store_ctl_const_seq(cb
, reg
, 1);
631 r600_store_value(cb
, value
);
634 static INLINE
void r600_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
636 r600_store_loop_const_seq(cb
, reg
, 1);
637 r600_store_value(cb
, value
);
640 static INLINE
void eg_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
642 eg_store_loop_const_seq(cb
, reg
, 1);
643 r600_store_value(cb
, value
);
646 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
, enum r600_atom_flags flags
);
647 void r600_release_command_buffer(struct r600_command_buffer
*cb
);
650 * Helpers for emitting state into a command stream directly.
653 static INLINE
unsigned r600_context_bo_reloc(struct r600_context
*ctx
, struct r600_resource
*rbo
,
654 enum radeon_bo_usage usage
)
657 return ctx
->ws
->cs_add_reloc(ctx
->cs
, rbo
->cs_buf
, usage
, rbo
->domains
) * 4;
660 static INLINE
void r600_write_value(struct radeon_winsys_cs
*cs
, unsigned value
)
662 cs
->buf
[cs
->cdw
++] = value
;
665 static INLINE
void r600_write_config_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
667 assert(reg
< R600_CONTEXT_REG_OFFSET
);
668 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
669 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
670 cs
->buf
[cs
->cdw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
673 static INLINE
void r600_write_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
675 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
676 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
677 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0);
678 cs
->buf
[cs
->cdw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
681 static INLINE
void r600_write_ctl_const_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
683 assert(reg
>= R600_CTL_CONST_OFFSET
);
684 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
685 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0);
686 cs
->buf
[cs
->cdw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
689 static INLINE
void r600_write_config_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
691 r600_write_config_reg_seq(cs
, reg
, 1);
692 r600_write_value(cs
, value
);
695 static INLINE
void r600_write_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
697 r600_write_context_reg_seq(cs
, reg
, 1);
698 r600_write_value(cs
, value
);
701 static INLINE
void r600_write_ctl_const(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
703 r600_write_ctl_const_seq(cs
, reg
, 1);
704 r600_write_value(cs
, value
);
710 static INLINE
uint32_t S_FIXED(float value
, uint32_t frac_bits
)
712 return value
* (1 << frac_bits
);
714 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
716 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
718 if (filter
<= 1) return 0;
719 if (filter
<= 2) return 1;
720 if (filter
<= 4) return 2;
721 if (filter
<= 8) return 3;
725 /* 12.4 fixed-point */
726 static INLINE
unsigned r600_pack_float_12p4(float x
)
729 x
>= 4096 ? 0xffff : x
* 16;
732 static INLINE
uint64_t r600_resource_va(struct pipe_screen
*screen
, struct pipe_resource
*resource
)
734 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
735 struct r600_resource
*rresource
= (struct r600_resource
*)resource
;
737 return rscreen
->ws
->buffer_get_virtual_address(rresource
->cs_buf
);