2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "util/u_slab.h"
31 #include "r600_llvm.h"
32 #include "r600_public.h"
33 #include "r600_shader.h"
34 #include "r600_resource.h"
35 #include "evergreen_compute.h"
37 #define R600_MAX_CONST_BUFFERS 2
38 #define R600_MAX_CONST_BUFFER_SIZE 4096
40 #ifdef PIPE_ARCH_BIG_ENDIAN
41 #define R600_BIG_ENDIAN 1
43 #define R600_BIG_ENDIAN 0
46 enum r600_atom_flags
{
47 /* When set, atoms are added at the beginning of the dirty list
48 * instead of the end. */
52 /* This encapsulates a state or an operation which can emitted into the GPU
53 * command stream. It's not limited to states only, it can be used for anything
54 * that wants to write commands into the CS (e.g. cache flushes). */
56 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
);
59 enum r600_atom_flags flags
;
62 struct list_head head
;
65 /* This is an atom containing GPU commands that never change.
66 * This is supposed to be copied directly into the CS. */
67 struct r600_command_buffer
{
68 struct r600_atom atom
;
74 struct r600_surface_sync_cmd
{
75 struct r600_atom atom
;
76 unsigned flush_flags
; /* CP_COHER_CNTL */
79 struct r600_db_misc_state
{
80 struct r600_atom atom
;
81 bool occlusion_query_enabled
;
82 bool flush_depthstencil_enabled
;
85 enum r600_pipe_state_id
{
86 R600_PIPE_STATE_BLEND
= 0,
87 R600_PIPE_STATE_BLEND_COLOR
,
88 R600_PIPE_STATE_CONFIG
,
89 R600_PIPE_STATE_SEAMLESS_CUBEMAP
,
91 R600_PIPE_STATE_SCISSOR
,
92 R600_PIPE_STATE_VIEWPORT
,
93 R600_PIPE_STATE_RASTERIZER
,
95 R600_PIPE_STATE_FRAMEBUFFER
,
97 R600_PIPE_STATE_STENCIL_REF
,
98 R600_PIPE_STATE_PS_SHADER
,
99 R600_PIPE_STATE_VS_SHADER
,
100 R600_PIPE_STATE_CONSTANT
,
101 R600_PIPE_STATE_SAMPLER
,
102 R600_PIPE_STATE_RESOURCE
,
103 R600_PIPE_STATE_POLYGON_OFFSET
,
104 R600_PIPE_STATE_FETCH_SHADER
,
109 struct compute_memory_pool
;
110 void compute_memory_pool_delete(struct compute_memory_pool
* pool
);
111 struct compute_memory_pool
* compute_memory_pool_new(
112 int64_t initial_size_in_dw
,
113 struct r600_screen
*rscreen
);
115 struct r600_pipe_fences
{
116 struct r600_resource
*bo
;
119 /* linked list of preallocated blocks */
120 struct list_head blocks
;
121 /* linked list of freed fences */
122 struct list_head pool
;
127 struct pipe_screen screen
;
128 struct radeon_winsys
*ws
;
130 enum chip_class chip_class
;
131 struct radeon_info info
;
133 struct r600_tiling_info tiling_info
;
134 struct r600_pipe_fences fences
;
136 bool use_surface_alloc
;
137 int glsl_feature_level
;
139 /*for compute global memory binding, we allocate stuff here, instead of
141 * XXX: Not sure if this is the best place for global_pool. Also,
142 * it's not thread safe, so it won't work with multiple contexts. */
143 struct compute_memory_pool
*global_pool
;
146 struct r600_pipe_sampler_view
{
147 struct pipe_sampler_view base
;
148 struct r600_pipe_resource_state state
;
151 struct r600_pipe_rasterizer
{
152 struct r600_pipe_state rstate
;
155 unsigned sprite_coord_enable
;
156 unsigned clip_plane_enable
;
157 unsigned pa_sc_line_stipple
;
158 unsigned pa_cl_clip_cntl
;
164 struct r600_pipe_blend
{
165 struct r600_pipe_state rstate
;
166 unsigned cb_target_mask
;
167 unsigned cb_color_control
;
171 struct r600_pipe_dsa
{
172 struct r600_pipe_state rstate
;
177 unsigned sx_alpha_test_control
;
180 struct r600_vertex_element
183 struct pipe_vertex_element elements
[PIPE_MAX_ATTRIBS
];
184 struct r600_resource
*fetch_shader
;
186 struct r600_pipe_state rstate
;
189 struct r600_pipe_shader
;
191 struct r600_pipe_shader_selector
{
192 struct r600_pipe_shader
*current
;
194 struct tgsi_token
*tokens
;
195 struct pipe_stream_output_info so
;
197 unsigned num_shaders
;
199 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
202 unsigned nr_ps_max_color_exports
;
205 struct r600_pipe_shader
{
206 struct r600_pipe_shader_selector
*selector
;
207 struct r600_pipe_shader
*next_variant
;
208 struct r600_shader shader
;
209 struct r600_pipe_state rstate
;
210 struct r600_resource
*bo
;
211 struct r600_resource
*bo_fetch
;
212 struct r600_vertex_element vertex_elements
;
213 unsigned sprite_coord_enable
;
215 unsigned pa_cl_vs_out_cntl
;
216 unsigned ps_cb_shader_mask
;
218 unsigned db_shader_control
;
219 unsigned ps_depth_export
;
222 struct r600_pipe_sampler_state
{
223 struct r600_pipe_state rstate
;
224 boolean seamless_cube_map
;
227 /* needed for blitter save */
228 #define NUM_TEX_UNITS 16
230 struct r600_textures_info
{
231 struct r600_pipe_sampler_view
*views
[NUM_TEX_UNITS
];
232 struct r600_pipe_sampler_state
*samplers
[NUM_TEX_UNITS
];
236 bool is_array_sampler
[NUM_TEX_UNITS
];
240 struct pipe_reference reference
;
241 unsigned index
; /* in the shared bo */
242 struct r600_resource
*sleep_bo
;
243 struct list_head head
;
246 #define FENCE_BLOCK_SIZE 16
248 struct r600_fence_block
{
249 struct r600_fence fences
[FENCE_BLOCK_SIZE
];
250 struct list_head head
;
253 #define R600_CONSTANT_ARRAY_SIZE 256
254 #define R600_RESOURCE_ARRAY_SIZE 160
256 struct r600_stencil_ref
263 struct r600_constbuf_state
265 struct r600_atom atom
;
266 struct pipe_constant_buffer cb
[PIPE_MAX_CONSTANT_BUFFERS
];
267 uint32_t enabled_mask
;
271 struct r600_context
{
272 struct pipe_context context
;
273 struct blitter_context
*blitter
;
274 enum radeon_family family
;
275 enum chip_class chip_class
;
276 boolean has_vertex_cache
;
277 unsigned r6xx_num_clause_temp_gprs
;
278 void *custom_dsa_flush
;
279 struct r600_screen
*screen
;
280 struct radeon_winsys
*ws
;
281 struct r600_pipe_state
*states
[R600_PIPE_NSTATES
];
282 struct r600_vertex_element
*vertex_elements
;
283 struct pipe_framebuffer_state framebuffer
;
284 unsigned cb_target_mask
;
285 unsigned fb_cb_shader_mask
;
286 unsigned sx_alpha_test_control
;
287 unsigned cb_shader_mask
;
288 unsigned db_shader_control
;
289 unsigned cb_color_control
;
290 unsigned pa_sc_line_stipple
;
291 unsigned pa_cl_clip_cntl
;
292 /* for saving when using blitter */
293 struct pipe_stencil_ref stencil_ref
;
294 struct pipe_viewport_state viewport
;
295 struct pipe_clip_state clip
;
296 struct r600_pipe_shader_selector
*ps_shader
;
297 struct r600_pipe_shader_selector
*vs_shader
;
298 struct r600_pipe_compute
*cs_shader
;
299 struct r600_pipe_rasterizer
*rasterizer
;
300 struct r600_pipe_state vgt
;
301 struct r600_pipe_state spi
;
302 struct pipe_query
*current_render_cond
;
303 unsigned current_render_cond_mode
;
304 struct pipe_query
*saved_render_cond
;
305 unsigned saved_render_cond_mode
;
306 /* shader information */
309 unsigned sprite_coord_enable
;
311 boolean export_16bpc
;
313 boolean alpha_ref_dirty
;
315 struct r600_textures_info vs_samplers
;
316 struct r600_textures_info ps_samplers
;
318 struct u_upload_mgr
*uploader
;
319 struct util_slab_mempool pool_transfers
;
320 boolean have_depth_texture
, have_depth_fb
;
322 unsigned default_ps_gprs
, default_vs_gprs
;
324 /* States based on r600_atom. */
325 struct list_head dirty_states
;
326 struct r600_command_buffer start_cs_cmd
; /* invariant state mostly */
327 /** Compute specific registers initializations. The start_cs_cmd atom
328 * must be emitted before start_compute_cs_cmd. */
329 struct r600_command_buffer start_compute_cs_cmd
;
330 struct r600_surface_sync_cmd surface_sync_cmd
;
331 struct r600_atom r6xx_flush_and_inv_cmd
;
332 struct r600_db_misc_state db_misc_state
;
333 struct r600_atom vertex_buffer_state
;
334 struct r600_constbuf_state vs_constbuf_state
;
335 struct r600_constbuf_state ps_constbuf_state
;
337 struct radeon_winsys_cs
*cs
;
339 struct r600_range
*range
;
341 struct r600_block
**blocks
;
342 struct list_head dirty
;
343 struct list_head resource_dirty
;
344 struct list_head enable_list
;
345 unsigned pm4_dirty_cdwords
;
346 unsigned ctx_pm4_ndwords
;
348 /* The list of active queries. Only one query of each type can be active. */
349 int num_occlusion_queries
;
351 /* Manage queries in two separate groups:
352 * The timer ones and the others (streamout, occlusion).
354 * We do this because we should only suspend non-timer queries for u_blitter,
355 * and later if the non-timer queries are suspended, the context flush should
356 * only suspend and resume the timer queries. */
357 struct list_head active_timer_queries
;
358 unsigned num_cs_dw_timer_queries_suspend
;
359 struct list_head active_nontimer_queries
;
360 unsigned num_cs_dw_nontimer_queries_suspend
;
362 unsigned num_cs_dw_streamout_end
;
364 unsigned backend_mask
;
365 unsigned max_db
; /* for OQ */
367 boolean predicate_drawing
;
368 struct r600_range ps_resources
;
369 struct r600_range vs_resources
;
370 int num_ps_resources
, num_vs_resources
;
372 unsigned num_so_targets
;
373 struct r600_so_target
*so_targets
[PIPE_MAX_SO_BUFFERS
];
374 boolean streamout_start
;
375 unsigned streamout_append_bitmask
;
377 /* There is no scissor enable bit on r6xx, so we must use a workaround.
378 * These track the current scissor state. */
380 struct pipe_scissor_state scissor_state
;
382 /* With rasterizer discard, there doesn't have to be a pixel shader.
383 * In that case, we bind this one: */
384 void *dummy_pixel_shader
;
386 boolean dual_src_blend
;
388 /* Vertex and index buffers. */
389 bool vertex_buffers_dirty
;
390 struct pipe_index_buffer index_buffer
;
391 struct pipe_vertex_buffer vertex_buffer
[PIPE_MAX_ATTRIBS
];
392 unsigned nr_vertex_buffers
;
395 static INLINE
void r600_emit_atom(struct r600_context
*rctx
, struct r600_atom
*atom
)
397 atom
->emit(rctx
, atom
);
399 if (atom
->head
.next
&& atom
->head
.prev
)
400 LIST_DELINIT(&atom
->head
);
403 static INLINE
void r600_atom_dirty(struct r600_context
*rctx
, struct r600_atom
*state
)
406 if (state
->flags
& EMIT_EARLY
) {
407 LIST_ADD(&state
->head
, &rctx
->dirty_states
);
409 LIST_ADDTAIL(&state
->head
, &rctx
->dirty_states
);
415 /* evergreen_state.c */
416 void evergreen_init_state_functions(struct r600_context
*rctx
);
417 void evergreen_init_atom_start_cs(struct r600_context
*rctx
);
418 void evergreen_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
419 void evergreen_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
420 void evergreen_fetch_shader(struct pipe_context
*ctx
, struct r600_vertex_element
*ve
);
421 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
);
422 void evergreen_polygon_offset_update(struct r600_context
*rctx
);
423 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
424 enum pipe_format format
,
425 enum pipe_texture_target target
,
426 unsigned sample_count
,
429 void evergreen_update_dual_export_state(struct r600_context
* rctx
);
432 void r600_init_blit_functions(struct r600_context
*rctx
);
433 void r600_blit_uncompress_depth(struct pipe_context
*ctx
, struct r600_resource_texture
*texture
);
434 void r600_flush_depth_textures(struct r600_context
*rctx
);
437 bool r600_init_resource(struct r600_screen
*rscreen
,
438 struct r600_resource
*res
,
439 unsigned size
, unsigned alignment
,
440 unsigned bind
, unsigned usage
);
441 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
442 const struct pipe_resource
*templ
);
445 void r600_flush(struct pipe_context
*ctx
, struct pipe_fence_handle
**fence
,
449 void r600_init_query_functions(struct r600_context
*rctx
);
450 void r600_suspend_nontimer_queries(struct r600_context
*ctx
);
451 void r600_resume_nontimer_queries(struct r600_context
*ctx
);
452 void r600_suspend_timer_queries(struct r600_context
*ctx
);
453 void r600_resume_timer_queries(struct r600_context
*ctx
);
455 /* r600_resource.c */
456 void r600_init_context_resource_functions(struct r600_context
*r600
);
459 int r600_pipe_shader_create(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
461 int r600_compute_shader_create(struct pipe_context
* ctx
,
462 LLVMModuleRef mod
, struct r600_bytecode
* bytecode
);
464 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
467 void r600_set_scissor_state(struct r600_context
*rctx
,
468 const struct pipe_scissor_state
*state
);
469 void r600_update_sampler_states(struct r600_context
*rctx
);
470 void r600_init_state_functions(struct r600_context
*rctx
);
471 void r600_init_atom_start_cs(struct r600_context
*rctx
);
472 void r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
473 void r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
474 void r600_fetch_shader(struct pipe_context
*ctx
, struct r600_vertex_element
*ve
);
475 void *r600_create_db_flush_dsa(struct r600_context
*rctx
);
476 void r600_polygon_offset_update(struct r600_context
*rctx
);
477 void r600_adjust_gprs(struct r600_context
*rctx
);
478 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
479 enum pipe_format format
,
480 enum pipe_texture_target target
,
481 unsigned sample_count
,
483 void r600_update_dual_export_state(struct r600_context
* rctx
);
486 void r600_init_screen_texture_functions(struct pipe_screen
*screen
);
487 void r600_init_surface_functions(struct r600_context
*r600
);
488 uint32_t r600_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
489 const unsigned char *swizzle_view
,
490 uint32_t *word4_p
, uint32_t *yuv_format_p
);
491 unsigned r600_texture_get_offset(struct r600_resource_texture
*rtex
,
492 unsigned level
, unsigned layer
);
494 /* r600_translate.c */
495 void r600_translate_index_buffer(struct r600_context
*r600
,
496 struct pipe_index_buffer
*ib
,
499 /* r600_state_common.c */
500 void r600_init_atom(struct r600_atom
*atom
,
501 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
502 unsigned num_dw
, enum r600_atom_flags flags
);
503 void r600_init_common_atoms(struct r600_context
*rctx
);
504 unsigned r600_get_cb_flush_flags(struct r600_context
*rctx
);
505 void r600_texture_barrier(struct pipe_context
*ctx
);
506 void r600_set_index_buffer(struct pipe_context
*ctx
,
507 const struct pipe_index_buffer
*ib
);
508 void r600_set_vertex_buffers(struct pipe_context
*ctx
, unsigned count
,
509 const struct pipe_vertex_buffer
*buffers
);
510 void *r600_create_vertex_elements(struct pipe_context
*ctx
,
512 const struct pipe_vertex_element
*elements
);
513 void r600_delete_vertex_element(struct pipe_context
*ctx
, void *state
);
514 void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
);
515 void r600_set_blend_color(struct pipe_context
*ctx
,
516 const struct pipe_blend_color
*state
);
517 void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
);
518 void r600_set_max_scissor(struct r600_context
*rctx
);
519 void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
);
520 void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
);
521 void r600_sampler_view_destroy(struct pipe_context
*ctx
,
522 struct pipe_sampler_view
*state
);
523 void r600_delete_state(struct pipe_context
*ctx
, void *state
);
524 void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
);
525 void *r600_create_shader_state_ps(struct pipe_context
*ctx
,
526 const struct pipe_shader_state
*state
);
527 void *r600_create_shader_state_vs(struct pipe_context
*ctx
,
528 const struct pipe_shader_state
*state
);
529 void r600_bind_ps_shader(struct pipe_context
*ctx
, void *state
);
530 void r600_bind_vs_shader(struct pipe_context
*ctx
, void *state
);
531 void r600_delete_ps_shader(struct pipe_context
*ctx
, void *state
);
532 void r600_delete_vs_shader(struct pipe_context
*ctx
, void *state
);
533 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
);
534 void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
535 struct pipe_constant_buffer
*cb
);
536 struct pipe_stream_output_target
*
537 r600_create_so_target(struct pipe_context
*ctx
,
538 struct pipe_resource
*buffer
,
539 unsigned buffer_offset
,
540 unsigned buffer_size
);
541 void r600_so_target_destroy(struct pipe_context
*ctx
,
542 struct pipe_stream_output_target
*target
);
543 void r600_set_so_targets(struct pipe_context
*ctx
,
544 unsigned num_targets
,
545 struct pipe_stream_output_target
**targets
,
546 unsigned append_bitmask
);
547 void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
548 const struct pipe_stencil_ref
*state
);
549 void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
);
550 uint32_t r600_translate_stencil_op(int s_op
);
551 uint32_t r600_translate_fill(uint32_t func
);
552 unsigned r600_tex_wrap(unsigned wrap
);
553 unsigned r600_tex_filter(unsigned filter
);
554 unsigned r600_tex_mipfilter(unsigned filter
);
555 unsigned r600_tex_compare(unsigned compare
);
558 * Helpers for building command buffers
561 #define PKT3_SET_CONFIG_REG 0x68
562 #define PKT3_SET_CONTEXT_REG 0x69
563 #define PKT3_SET_CTL_CONST 0x6F
564 #define PKT3_SET_LOOP_CONST 0x6C
566 #define R600_CONFIG_REG_OFFSET 0x08000
567 #define R600_CONTEXT_REG_OFFSET 0x28000
568 #define R600_CTL_CONST_OFFSET 0x3CFF0
569 #define R600_LOOP_CONST_OFFSET 0X0003E200
570 #define EG_LOOP_CONST_OFFSET 0x0003A200
572 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
573 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
574 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
575 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
576 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
578 static INLINE
void r600_store_value(struct r600_command_buffer
*cb
, unsigned value
)
580 cb
->buf
[cb
->atom
.num_dw
++] = value
;
583 static INLINE
void r600_store_config_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
585 assert(reg
< R600_CONTEXT_REG_OFFSET
);
586 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
587 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
588 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
592 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
595 static INLINE
void r600_store_context_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
597 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
598 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
599 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0) | cb
->pkt_flags
;
600 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
604 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
607 static INLINE
void r600_store_ctl_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
609 assert(reg
>= R600_CTL_CONST_OFFSET
);
610 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
611 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0) | cb
->pkt_flags
;
612 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
615 static INLINE
void r600_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
617 assert(reg
>= R600_LOOP_CONST_OFFSET
);
618 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
619 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0);
620 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_LOOP_CONST_OFFSET
) >> 2;
624 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
627 static INLINE
void eg_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
629 assert(reg
>= EG_LOOP_CONST_OFFSET
);
630 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
631 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0) | cb
->pkt_flags
;
632 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- EG_LOOP_CONST_OFFSET
) >> 2;
635 static INLINE
void r600_store_config_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
637 r600_store_config_reg_seq(cb
, reg
, 1);
638 r600_store_value(cb
, value
);
641 static INLINE
void r600_store_context_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
643 r600_store_context_reg_seq(cb
, reg
, 1);
644 r600_store_value(cb
, value
);
647 static INLINE
void r600_store_ctl_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
649 r600_store_ctl_const_seq(cb
, reg
, 1);
650 r600_store_value(cb
, value
);
653 static INLINE
void r600_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
655 r600_store_loop_const_seq(cb
, reg
, 1);
656 r600_store_value(cb
, value
);
659 static INLINE
void eg_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
661 eg_store_loop_const_seq(cb
, reg
, 1);
662 r600_store_value(cb
, value
);
665 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
, enum r600_atom_flags flags
);
666 void r600_release_command_buffer(struct r600_command_buffer
*cb
);
669 * Helpers for emitting state into a command stream directly.
672 static INLINE
unsigned r600_context_bo_reloc(struct r600_context
*ctx
, struct r600_resource
*rbo
,
673 enum radeon_bo_usage usage
)
676 return ctx
->ws
->cs_add_reloc(ctx
->cs
, rbo
->cs_buf
, usage
, rbo
->domains
) * 4;
679 static INLINE
void r600_write_value(struct radeon_winsys_cs
*cs
, unsigned value
)
681 cs
->buf
[cs
->cdw
++] = value
;
684 static INLINE
void r600_write_config_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
686 assert(reg
< R600_CONTEXT_REG_OFFSET
);
687 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
688 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
689 cs
->buf
[cs
->cdw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
692 static INLINE
void r600_write_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
694 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
695 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
696 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0);
697 cs
->buf
[cs
->cdw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
700 static INLINE
void r600_write_ctl_const_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
702 assert(reg
>= R600_CTL_CONST_OFFSET
);
703 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
704 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0);
705 cs
->buf
[cs
->cdw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
708 static INLINE
void r600_write_config_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
710 r600_write_config_reg_seq(cs
, reg
, 1);
711 r600_write_value(cs
, value
);
714 static INLINE
void r600_write_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
716 r600_write_context_reg_seq(cs
, reg
, 1);
717 r600_write_value(cs
, value
);
720 static INLINE
void r600_write_ctl_const(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
722 r600_write_ctl_const_seq(cs
, reg
, 1);
723 r600_write_value(cs
, value
);
729 static INLINE
uint32_t S_FIXED(float value
, uint32_t frac_bits
)
731 return value
* (1 << frac_bits
);
733 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
735 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
737 if (filter
<= 1) return 0;
738 if (filter
<= 2) return 1;
739 if (filter
<= 4) return 2;
740 if (filter
<= 8) return 3;
744 /* 12.4 fixed-point */
745 static INLINE
unsigned r600_pack_float_12p4(float x
)
748 x
>= 4096 ? 0xffff : x
* 16;
751 static INLINE
uint64_t r600_resource_va(struct pipe_screen
*screen
, struct pipe_resource
*resource
)
753 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
754 struct r600_resource
*rresource
= (struct r600_resource
*)resource
;
756 return rscreen
->ws
->buffer_get_virtual_address(rresource
->cs_buf
);