2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "util/u_slab.h"
31 #include "r600_llvm.h"
32 #include "r600_public.h"
33 #include "r600_shader.h"
34 #include "r600_resource.h"
35 #include "evergreen_compute.h"
37 #define R600_MAX_CONST_BUFFERS 2
38 #define R600_MAX_CONST_BUFFER_SIZE 4096
40 #ifdef PIPE_ARCH_BIG_ENDIAN
41 #define R600_BIG_ENDIAN 1
43 #define R600_BIG_ENDIAN 0
46 enum r600_atom_flags
{
47 /* When set, atoms are added at the beginning of the dirty list
48 * instead of the end. */
52 /* This encapsulates a state or an operation which can emitted into the GPU
53 * command stream. It's not limited to states only, it can be used for anything
54 * that wants to write commands into the CS (e.g. cache flushes). */
56 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
);
59 enum r600_atom_flags flags
;
62 struct list_head head
;
65 /* This is an atom containing GPU commands that never change.
66 * This is supposed to be copied directly into the CS. */
67 struct r600_command_buffer
{
68 struct r600_atom atom
;
74 struct r600_surface_sync_cmd
{
75 struct r600_atom atom
;
76 unsigned flush_flags
; /* CP_COHER_CNTL */
79 struct r600_db_misc_state
{
80 struct r600_atom atom
;
81 bool occlusion_query_enabled
;
82 bool flush_depthstencil_through_cb
;
85 struct r600_cb_misc_state
{
86 struct r600_atom atom
;
87 unsigned cb_color_control
; /* this comes from blend state */
88 unsigned blend_colormask
; /* 8*4 bits for 8 RGBA colorbuffers */
90 unsigned nr_ps_color_outputs
;
95 enum r600_pipe_state_id
{
96 R600_PIPE_STATE_BLEND
= 0,
97 R600_PIPE_STATE_BLEND_COLOR
,
98 R600_PIPE_STATE_CONFIG
,
99 R600_PIPE_STATE_SEAMLESS_CUBEMAP
,
100 R600_PIPE_STATE_CLIP
,
101 R600_PIPE_STATE_SCISSOR
,
102 R600_PIPE_STATE_VIEWPORT
,
103 R600_PIPE_STATE_RASTERIZER
,
105 R600_PIPE_STATE_FRAMEBUFFER
,
107 R600_PIPE_STATE_STENCIL_REF
,
108 R600_PIPE_STATE_PS_SHADER
,
109 R600_PIPE_STATE_VS_SHADER
,
110 R600_PIPE_STATE_CONSTANT
,
111 R600_PIPE_STATE_SAMPLER
,
112 R600_PIPE_STATE_RESOURCE
,
113 R600_PIPE_STATE_POLYGON_OFFSET
,
114 R600_PIPE_STATE_FETCH_SHADER
,
119 struct compute_memory_pool
;
120 void compute_memory_pool_delete(struct compute_memory_pool
* pool
);
121 struct compute_memory_pool
* compute_memory_pool_new(
122 struct r600_screen
*rscreen
);
124 struct r600_pipe_fences
{
125 struct r600_resource
*bo
;
128 /* linked list of preallocated blocks */
129 struct list_head blocks
;
130 /* linked list of freed fences */
131 struct list_head pool
;
136 struct pipe_screen screen
;
137 struct radeon_winsys
*ws
;
139 enum chip_class chip_class
;
140 struct radeon_info info
;
142 struct r600_tiling_info tiling_info
;
143 struct r600_pipe_fences fences
;
145 bool use_surface_alloc
;
146 int glsl_feature_level
;
148 /*for compute global memory binding, we allocate stuff here, instead of
150 * XXX: Not sure if this is the best place for global_pool. Also,
151 * it's not thread safe, so it won't work with multiple contexts. */
152 struct compute_memory_pool
*global_pool
;
155 struct r600_pipe_sampler_view
{
156 struct pipe_sampler_view base
;
157 struct r600_pipe_resource_state state
;
160 struct r600_pipe_rasterizer
{
161 struct r600_pipe_state rstate
;
164 unsigned sprite_coord_enable
;
165 unsigned clip_plane_enable
;
166 unsigned pa_sc_line_stipple
;
167 unsigned pa_cl_clip_cntl
;
173 struct r600_pipe_blend
{
174 struct r600_pipe_state rstate
;
175 unsigned cb_target_mask
;
176 unsigned cb_color_control
;
180 struct r600_pipe_dsa
{
181 struct r600_pipe_state rstate
;
185 unsigned sx_alpha_test_control
;
188 struct r600_vertex_element
191 struct pipe_vertex_element elements
[PIPE_MAX_ATTRIBS
];
192 struct r600_resource
*fetch_shader
;
194 struct r600_pipe_state rstate
;
197 struct r600_pipe_shader
;
199 struct r600_pipe_shader_selector
{
200 struct r600_pipe_shader
*current
;
202 struct tgsi_token
*tokens
;
203 struct pipe_stream_output_info so
;
205 unsigned num_shaders
;
207 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
210 unsigned nr_ps_max_color_exports
;
213 struct r600_pipe_shader
{
214 struct r600_pipe_shader_selector
*selector
;
215 struct r600_pipe_shader
*next_variant
;
216 struct r600_shader shader
;
217 struct r600_pipe_state rstate
;
218 struct r600_resource
*bo
;
219 struct r600_resource
*bo_fetch
;
220 struct r600_vertex_element vertex_elements
;
221 unsigned sprite_coord_enable
;
223 unsigned pa_cl_vs_out_cntl
;
224 unsigned nr_ps_color_outputs
;
226 unsigned db_shader_control
;
227 unsigned ps_depth_export
;
230 struct r600_pipe_sampler_state
{
231 struct r600_pipe_state rstate
;
232 boolean seamless_cube_map
;
235 /* needed for blitter save */
236 #define NUM_TEX_UNITS 16
238 struct r600_textures_info
{
239 struct r600_pipe_sampler_view
*views
[NUM_TEX_UNITS
];
240 struct r600_pipe_sampler_state
*samplers
[NUM_TEX_UNITS
];
244 bool is_array_sampler
[NUM_TEX_UNITS
];
248 struct pipe_reference reference
;
249 unsigned index
; /* in the shared bo */
250 struct r600_resource
*sleep_bo
;
251 struct list_head head
;
254 #define FENCE_BLOCK_SIZE 16
256 struct r600_fence_block
{
257 struct r600_fence fences
[FENCE_BLOCK_SIZE
];
258 struct list_head head
;
261 #define R600_CONSTANT_ARRAY_SIZE 256
262 #define R600_RESOURCE_ARRAY_SIZE 160
264 struct r600_stencil_ref
271 struct r600_constbuf_state
273 struct r600_atom atom
;
274 struct pipe_constant_buffer cb
[PIPE_MAX_CONSTANT_BUFFERS
];
275 uint32_t enabled_mask
;
279 struct r600_context
{
280 struct pipe_context context
;
281 struct blitter_context
*blitter
;
282 enum radeon_family family
;
283 enum chip_class chip_class
;
284 boolean has_vertex_cache
;
285 unsigned r6xx_num_clause_temp_gprs
;
286 void *custom_dsa_flush
;
287 struct r600_screen
*screen
;
288 struct radeon_winsys
*ws
;
289 struct r600_pipe_state
*states
[R600_PIPE_NSTATES
];
290 struct r600_vertex_element
*vertex_elements
;
291 struct pipe_framebuffer_state framebuffer
;
292 unsigned compute_cb_target_mask
;
293 unsigned sx_alpha_test_control
;
294 unsigned db_shader_control
;
295 unsigned pa_sc_line_stipple
;
296 unsigned pa_cl_clip_cntl
;
297 /* for saving when using blitter */
298 struct pipe_stencil_ref stencil_ref
;
299 struct pipe_viewport_state viewport
;
300 struct pipe_clip_state clip
;
301 struct r600_pipe_shader_selector
*ps_shader
;
302 struct r600_pipe_shader_selector
*vs_shader
;
303 struct r600_pipe_compute
*cs_shader
;
304 struct r600_pipe_rasterizer
*rasterizer
;
305 struct r600_pipe_state vgt
;
306 struct r600_pipe_state spi
;
307 struct pipe_query
*current_render_cond
;
308 unsigned current_render_cond_mode
;
309 struct pipe_query
*saved_render_cond
;
310 unsigned saved_render_cond_mode
;
311 /* shader information */
314 unsigned sprite_coord_enable
;
316 boolean export_16bpc
;
318 boolean alpha_ref_dirty
;
320 struct r600_textures_info vs_samplers
;
321 struct r600_textures_info ps_samplers
;
323 struct u_upload_mgr
*uploader
;
324 struct util_slab_mempool pool_transfers
;
325 boolean have_depth_texture
, have_depth_fb
;
327 unsigned default_ps_gprs
, default_vs_gprs
;
329 /* States based on r600_atom. */
330 struct list_head dirty_states
;
331 struct r600_command_buffer start_cs_cmd
; /* invariant state mostly */
332 /** Compute specific registers initializations. The start_cs_cmd atom
333 * must be emitted before start_compute_cs_cmd. */
334 struct r600_command_buffer start_compute_cs_cmd
;
335 struct r600_surface_sync_cmd surface_sync_cmd
;
336 struct r600_atom r6xx_flush_and_inv_cmd
;
337 struct r600_cb_misc_state cb_misc_state
;
338 struct r600_db_misc_state db_misc_state
;
339 struct r600_atom vertex_buffer_state
;
340 struct r600_constbuf_state vs_constbuf_state
;
341 struct r600_constbuf_state ps_constbuf_state
;
343 struct radeon_winsys_cs
*cs
;
345 struct r600_range
*range
;
347 struct r600_block
**blocks
;
348 struct list_head dirty
;
349 struct list_head resource_dirty
;
350 struct list_head enable_list
;
351 unsigned pm4_dirty_cdwords
;
352 unsigned ctx_pm4_ndwords
;
354 /* The list of active queries. Only one query of each type can be active. */
355 int num_occlusion_queries
;
357 /* Manage queries in two separate groups:
358 * The timer ones and the others (streamout, occlusion).
360 * We do this because we should only suspend non-timer queries for u_blitter,
361 * and later if the non-timer queries are suspended, the context flush should
362 * only suspend and resume the timer queries. */
363 struct list_head active_timer_queries
;
364 unsigned num_cs_dw_timer_queries_suspend
;
365 struct list_head active_nontimer_queries
;
366 unsigned num_cs_dw_nontimer_queries_suspend
;
368 unsigned num_cs_dw_streamout_end
;
370 unsigned backend_mask
;
371 unsigned max_db
; /* for OQ */
373 boolean predicate_drawing
;
374 struct r600_range ps_resources
;
375 struct r600_range vs_resources
;
376 int num_ps_resources
, num_vs_resources
;
378 unsigned num_so_targets
;
379 struct r600_so_target
*so_targets
[PIPE_MAX_SO_BUFFERS
];
380 boolean streamout_start
;
381 unsigned streamout_append_bitmask
;
383 /* There is no scissor enable bit on r6xx, so we must use a workaround.
384 * These track the current scissor state. */
386 struct pipe_scissor_state scissor_state
;
388 /* With rasterizer discard, there doesn't have to be a pixel shader.
389 * In that case, we bind this one: */
390 void *dummy_pixel_shader
;
392 boolean dual_src_blend
;
394 /* Vertex and index buffers. */
395 bool vertex_buffers_dirty
;
396 struct pipe_index_buffer index_buffer
;
397 struct pipe_vertex_buffer vertex_buffer
[PIPE_MAX_ATTRIBS
];
398 unsigned nr_vertex_buffers
;
401 static INLINE
void r600_emit_atom(struct r600_context
*rctx
, struct r600_atom
*atom
)
403 atom
->emit(rctx
, atom
);
405 if (atom
->head
.next
&& atom
->head
.prev
)
406 LIST_DELINIT(&atom
->head
);
409 static INLINE
void r600_atom_dirty(struct r600_context
*rctx
, struct r600_atom
*state
)
412 if (state
->flags
& EMIT_EARLY
) {
413 LIST_ADD(&state
->head
, &rctx
->dirty_states
);
415 LIST_ADDTAIL(&state
->head
, &rctx
->dirty_states
);
421 /* evergreen_state.c */
422 void evergreen_init_state_functions(struct r600_context
*rctx
);
423 void evergreen_init_atom_start_cs(struct r600_context
*rctx
);
424 void evergreen_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
425 void evergreen_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
426 void evergreen_fetch_shader(struct pipe_context
*ctx
, struct r600_vertex_element
*ve
);
427 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
);
428 void evergreen_polygon_offset_update(struct r600_context
*rctx
);
429 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
430 enum pipe_format format
,
431 enum pipe_texture_target target
,
432 unsigned sample_count
,
434 void evergreen_cb(struct r600_context
*rctx
, struct r600_pipe_state
*rstate
,
435 const struct pipe_framebuffer_state
*state
, int cb
);
438 void evergreen_update_dual_export_state(struct r600_context
* rctx
);
441 void r600_init_blit_functions(struct r600_context
*rctx
);
442 void r600_blit_uncompress_depth(struct pipe_context
*ctx
,
443 struct r600_resource_texture
*texture
,
444 struct r600_resource_texture
*staging
,
445 unsigned first_level
, unsigned last_level
,
446 unsigned first_layer
, unsigned last_layer
);
447 void r600_flush_all_depth_textures(struct r600_context
*rctx
);
450 bool r600_init_resource(struct r600_screen
*rscreen
,
451 struct r600_resource
*res
,
452 unsigned size
, unsigned alignment
,
453 unsigned bind
, unsigned usage
);
454 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
455 const struct pipe_resource
*templ
);
458 void r600_flush(struct pipe_context
*ctx
, struct pipe_fence_handle
**fence
,
462 void r600_init_query_functions(struct r600_context
*rctx
);
463 void r600_suspend_nontimer_queries(struct r600_context
*ctx
);
464 void r600_resume_nontimer_queries(struct r600_context
*ctx
);
465 void r600_suspend_timer_queries(struct r600_context
*ctx
);
466 void r600_resume_timer_queries(struct r600_context
*ctx
);
468 /* r600_resource.c */
469 void r600_init_context_resource_functions(struct r600_context
*r600
);
472 int r600_pipe_shader_create(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
474 int r600_compute_shader_create(struct pipe_context
* ctx
,
475 LLVMModuleRef mod
, struct r600_bytecode
* bytecode
);
477 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
480 void r600_set_scissor_state(struct r600_context
*rctx
,
481 const struct pipe_scissor_state
*state
);
482 void r600_update_sampler_states(struct r600_context
*rctx
);
483 void r600_init_state_functions(struct r600_context
*rctx
);
484 void r600_init_atom_start_cs(struct r600_context
*rctx
);
485 void r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
486 void r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
487 void r600_fetch_shader(struct pipe_context
*ctx
, struct r600_vertex_element
*ve
);
488 void *r600_create_db_flush_dsa(struct r600_context
*rctx
);
489 void r600_polygon_offset_update(struct r600_context
*rctx
);
490 void r600_adjust_gprs(struct r600_context
*rctx
);
491 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
492 enum pipe_format format
,
493 enum pipe_texture_target target
,
494 unsigned sample_count
,
496 void r600_update_dual_export_state(struct r600_context
* rctx
);
499 void r600_init_screen_texture_functions(struct pipe_screen
*screen
);
500 void r600_init_surface_functions(struct r600_context
*r600
);
501 uint32_t r600_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
502 const unsigned char *swizzle_view
,
503 uint32_t *word4_p
, uint32_t *yuv_format_p
);
504 unsigned r600_texture_get_offset(struct r600_resource_texture
*rtex
,
505 unsigned level
, unsigned layer
);
507 /* r600_translate.c */
508 void r600_translate_index_buffer(struct r600_context
*r600
,
509 struct pipe_index_buffer
*ib
,
512 /* r600_state_common.c */
513 void r600_init_atom(struct r600_atom
*atom
,
514 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
515 unsigned num_dw
, enum r600_atom_flags flags
);
516 void r600_init_common_atoms(struct r600_context
*rctx
);
517 unsigned r600_get_cb_flush_flags(struct r600_context
*rctx
);
518 void r600_texture_barrier(struct pipe_context
*ctx
);
519 void r600_set_index_buffer(struct pipe_context
*ctx
,
520 const struct pipe_index_buffer
*ib
);
521 void r600_set_vertex_buffers(struct pipe_context
*ctx
, unsigned count
,
522 const struct pipe_vertex_buffer
*buffers
);
523 void *r600_create_vertex_elements(struct pipe_context
*ctx
,
525 const struct pipe_vertex_element
*elements
);
526 void r600_delete_vertex_element(struct pipe_context
*ctx
, void *state
);
527 void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
);
528 void r600_set_blend_color(struct pipe_context
*ctx
,
529 const struct pipe_blend_color
*state
);
530 void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
);
531 void r600_set_max_scissor(struct r600_context
*rctx
);
532 void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
);
533 void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
);
534 void r600_sampler_view_destroy(struct pipe_context
*ctx
,
535 struct pipe_sampler_view
*state
);
536 void r600_delete_state(struct pipe_context
*ctx
, void *state
);
537 void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
);
538 void *r600_create_shader_state_ps(struct pipe_context
*ctx
,
539 const struct pipe_shader_state
*state
);
540 void *r600_create_shader_state_vs(struct pipe_context
*ctx
,
541 const struct pipe_shader_state
*state
);
542 void r600_bind_ps_shader(struct pipe_context
*ctx
, void *state
);
543 void r600_bind_vs_shader(struct pipe_context
*ctx
, void *state
);
544 void r600_delete_ps_shader(struct pipe_context
*ctx
, void *state
);
545 void r600_delete_vs_shader(struct pipe_context
*ctx
, void *state
);
546 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
);
547 void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
548 struct pipe_constant_buffer
*cb
);
549 struct pipe_stream_output_target
*
550 r600_create_so_target(struct pipe_context
*ctx
,
551 struct pipe_resource
*buffer
,
552 unsigned buffer_offset
,
553 unsigned buffer_size
);
554 void r600_so_target_destroy(struct pipe_context
*ctx
,
555 struct pipe_stream_output_target
*target
);
556 void r600_set_so_targets(struct pipe_context
*ctx
,
557 unsigned num_targets
,
558 struct pipe_stream_output_target
**targets
,
559 unsigned append_bitmask
);
560 void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
561 const struct pipe_stencil_ref
*state
);
562 void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
);
563 uint32_t r600_translate_stencil_op(int s_op
);
564 uint32_t r600_translate_fill(uint32_t func
);
565 unsigned r600_tex_wrap(unsigned wrap
);
566 unsigned r600_tex_filter(unsigned filter
);
567 unsigned r600_tex_mipfilter(unsigned filter
);
568 unsigned r600_tex_compare(unsigned compare
);
571 * Helpers for building command buffers
574 #define PKT3_SET_CONFIG_REG 0x68
575 #define PKT3_SET_CONTEXT_REG 0x69
576 #define PKT3_SET_CTL_CONST 0x6F
577 #define PKT3_SET_LOOP_CONST 0x6C
579 #define R600_CONFIG_REG_OFFSET 0x08000
580 #define R600_CONTEXT_REG_OFFSET 0x28000
581 #define R600_CTL_CONST_OFFSET 0x3CFF0
582 #define R600_LOOP_CONST_OFFSET 0X0003E200
583 #define EG_LOOP_CONST_OFFSET 0x0003A200
585 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
586 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
587 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
588 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
589 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
591 static INLINE
void r600_store_value(struct r600_command_buffer
*cb
, unsigned value
)
593 cb
->buf
[cb
->atom
.num_dw
++] = value
;
596 static INLINE
void r600_store_config_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
598 assert(reg
< R600_CONTEXT_REG_OFFSET
);
599 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
600 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
601 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
605 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
608 static INLINE
void r600_store_context_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
610 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
611 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
612 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0) | cb
->pkt_flags
;
613 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
617 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
620 static INLINE
void r600_store_ctl_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
622 assert(reg
>= R600_CTL_CONST_OFFSET
);
623 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
624 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0) | cb
->pkt_flags
;
625 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
628 static INLINE
void r600_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
630 assert(reg
>= R600_LOOP_CONST_OFFSET
);
631 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
632 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0);
633 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_LOOP_CONST_OFFSET
) >> 2;
637 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
640 static INLINE
void eg_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
642 assert(reg
>= EG_LOOP_CONST_OFFSET
);
643 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
644 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0) | cb
->pkt_flags
;
645 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- EG_LOOP_CONST_OFFSET
) >> 2;
648 static INLINE
void r600_store_config_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
650 r600_store_config_reg_seq(cb
, reg
, 1);
651 r600_store_value(cb
, value
);
654 static INLINE
void r600_store_context_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
656 r600_store_context_reg_seq(cb
, reg
, 1);
657 r600_store_value(cb
, value
);
660 static INLINE
void r600_store_ctl_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
662 r600_store_ctl_const_seq(cb
, reg
, 1);
663 r600_store_value(cb
, value
);
666 static INLINE
void r600_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
668 r600_store_loop_const_seq(cb
, reg
, 1);
669 r600_store_value(cb
, value
);
672 static INLINE
void eg_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
674 eg_store_loop_const_seq(cb
, reg
, 1);
675 r600_store_value(cb
, value
);
678 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
, enum r600_atom_flags flags
);
679 void r600_release_command_buffer(struct r600_command_buffer
*cb
);
682 * Helpers for emitting state into a command stream directly.
685 static INLINE
unsigned r600_context_bo_reloc(struct r600_context
*ctx
, struct r600_resource
*rbo
,
686 enum radeon_bo_usage usage
)
689 return ctx
->ws
->cs_add_reloc(ctx
->cs
, rbo
->cs_buf
, usage
, rbo
->domains
) * 4;
692 static INLINE
void r600_write_value(struct radeon_winsys_cs
*cs
, unsigned value
)
694 cs
->buf
[cs
->cdw
++] = value
;
697 static INLINE
void r600_write_config_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
699 assert(reg
< R600_CONTEXT_REG_OFFSET
);
700 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
701 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
702 cs
->buf
[cs
->cdw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
705 static INLINE
void r600_write_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
707 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
708 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
709 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0);
710 cs
->buf
[cs
->cdw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
713 static INLINE
void r600_write_ctl_const_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
715 assert(reg
>= R600_CTL_CONST_OFFSET
);
716 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
717 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0);
718 cs
->buf
[cs
->cdw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
721 static INLINE
void r600_write_config_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
723 r600_write_config_reg_seq(cs
, reg
, 1);
724 r600_write_value(cs
, value
);
727 static INLINE
void r600_write_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
729 r600_write_context_reg_seq(cs
, reg
, 1);
730 r600_write_value(cs
, value
);
733 static INLINE
void r600_write_ctl_const(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
735 r600_write_ctl_const_seq(cs
, reg
, 1);
736 r600_write_value(cs
, value
);
742 static INLINE
uint32_t S_FIXED(float value
, uint32_t frac_bits
)
744 return value
* (1 << frac_bits
);
746 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
748 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
750 if (filter
<= 1) return 0;
751 if (filter
<= 2) return 1;
752 if (filter
<= 4) return 2;
753 if (filter
<= 8) return 3;
757 /* 12.4 fixed-point */
758 static INLINE
unsigned r600_pack_float_12p4(float x
)
761 x
>= 4096 ? 0xffff : x
* 16;
764 static INLINE
uint64_t r600_resource_va(struct pipe_screen
*screen
, struct pipe_resource
*resource
)
766 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
767 struct r600_resource
*rresource
= (struct r600_resource
*)resource
;
769 return rscreen
->ws
->buffer_get_virtual_address(rresource
->cs_buf
);