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r600g: Fix build
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "util/u_blitter.h"
30 #include "util/u_slab.h"
31 #include "util/u_suballoc.h"
32 #include "util/u_double_list.h"
33 #include "util/u_transfer.h"
34 #include "r600_llvm.h"
35 #include "r600_public.h"
36 #include "r600_resource.h"
37
38 #define R600_NUM_ATOMS 41
39
40 /* the number of CS dwords for flushing and drawing */
41 #define R600_MAX_FLUSH_CS_DWORDS 16
42 #define R600_MAX_DRAW_CS_DWORDS 34
43 #define R600_TRACE_CS_DWORDS 7
44
45 #define R600_MAX_USER_CONST_BUFFERS 13
46 #define R600_MAX_DRIVER_CONST_BUFFERS 3
47 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
48
49 /* start driver buffers after user buffers */
50 #define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
51 #define R600_TXQ_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
52 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
53
54 #define R600_MAX_CONST_BUFFER_SIZE 4096
55
56 #ifdef PIPE_ARCH_BIG_ENDIAN
57 #define R600_BIG_ENDIAN 1
58 #else
59 #define R600_BIG_ENDIAN 0
60 #endif
61
62 #define R600_MAP_BUFFER_ALIGNMENT 64
63
64 #define R600_ERR(fmt, args...) \
65 fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
66
67 #define R600_CONTEXT_INVAL_READ_CACHES (1 << 0)
68 #define R600_CONTEXT_STREAMOUT_FLUSH (1 << 1)
69 #define R600_CONTEXT_WAIT_3D_IDLE (1 << 2)
70 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (1 << 3)
71 #define R600_CONTEXT_FLUSH_AND_INV (1 << 4)
72 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (1 << 5)
73 #define R600_CONTEXT_PS_PARTIAL_FLUSH (1 << 6)
74 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (1 << 7)
75
76 #define R600_QUERY_DRAW_CALLS (PIPE_QUERY_DRIVER_SPECIFIC + 0)
77 #define R600_QUERY_REQUESTED_VRAM (PIPE_QUERY_DRIVER_SPECIFIC + 1)
78 #define R600_QUERY_REQUESTED_GTT (PIPE_QUERY_DRIVER_SPECIFIC + 2)
79 #define R600_QUERY_BUFFER_WAIT_TIME (PIPE_QUERY_DRIVER_SPECIFIC + 3)
80
81 struct r600_context;
82 struct r600_bytecode;
83 struct r600_shader_key;
84
85 /* This encapsulates a state or an operation which can emitted into the GPU
86 * command stream. It's not limited to states only, it can be used for anything
87 * that wants to write commands into the CS (e.g. cache flushes). */
88 struct r600_atom {
89 void (*emit)(struct r600_context *ctx, struct r600_atom *state);
90 unsigned id;
91 unsigned num_dw;
92 bool dirty;
93 };
94
95 /* This is an atom containing GPU commands that never change.
96 * This is supposed to be copied directly into the CS. */
97 struct r600_command_buffer {
98 uint32_t *buf;
99 unsigned num_dw;
100 unsigned max_num_dw;
101 unsigned pkt_flags;
102 };
103
104 struct r600_db_state {
105 struct r600_atom atom;
106 struct r600_surface *rsurf;
107 };
108
109 struct r600_db_misc_state {
110 struct r600_atom atom;
111 bool occlusion_query_enabled;
112 bool flush_depthstencil_through_cb;
113 bool flush_depthstencil_in_place;
114 bool copy_depth, copy_stencil;
115 unsigned copy_sample;
116 unsigned log_samples;
117 unsigned db_shader_control;
118 bool htile_clear;
119 };
120
121 struct r600_cb_misc_state {
122 struct r600_atom atom;
123 unsigned cb_color_control; /* this comes from blend state */
124 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
125 unsigned nr_cbufs;
126 unsigned nr_ps_color_outputs;
127 bool multiwrite;
128 bool dual_src_blend;
129 };
130
131 struct r600_clip_misc_state {
132 struct r600_atom atom;
133 unsigned pa_cl_clip_cntl; /* from rasterizer */
134 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
135 unsigned clip_plane_enable; /* from rasterizer */
136 unsigned clip_dist_write; /* from vertex shader */
137 };
138
139 struct r600_alphatest_state {
140 struct r600_atom atom;
141 unsigned sx_alpha_test_control; /* this comes from dsa state */
142 unsigned sx_alpha_ref; /* this comes from dsa state */
143 bool bypass;
144 bool cb0_export_16bpc; /* from set_framebuffer_state */
145 };
146
147 struct r600_vgt_state {
148 struct r600_atom atom;
149 uint32_t vgt_multi_prim_ib_reset_en;
150 uint32_t vgt_multi_prim_ib_reset_indx;
151 uint32_t vgt_indx_offset;
152 };
153
154 struct r600_blend_color {
155 struct r600_atom atom;
156 struct pipe_blend_color state;
157 };
158
159 struct r600_clip_state {
160 struct r600_atom atom;
161 struct pipe_clip_state state;
162 };
163
164 struct r600_cs_shader_state {
165 struct r600_atom atom;
166 unsigned kernel_index;
167 struct r600_pipe_compute *shader;
168 };
169
170 struct r600_framebuffer {
171 struct r600_atom atom;
172 struct pipe_framebuffer_state state;
173 unsigned compressed_cb_mask;
174 unsigned nr_samples;
175 bool export_16bpc;
176 bool cb0_is_integer;
177 bool is_msaa_resolve;
178 };
179
180 struct r600_sample_mask {
181 struct r600_atom atom;
182 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
183 };
184
185 struct r600_config_state {
186 struct r600_atom atom;
187 unsigned sq_gpr_resource_mgmt_1;
188 };
189
190 struct r600_stencil_ref
191 {
192 ubyte ref_value[2];
193 ubyte valuemask[2];
194 ubyte writemask[2];
195 };
196
197 struct r600_stencil_ref_state {
198 struct r600_atom atom;
199 struct r600_stencil_ref state;
200 struct pipe_stencil_ref pipe_state;
201 };
202
203 struct r600_viewport_state {
204 struct r600_atom atom;
205 struct pipe_viewport_state state;
206 };
207
208 struct r600_pipe_fences {
209 struct r600_resource *bo;
210 unsigned *data;
211 unsigned next_index;
212 /* linked list of preallocated blocks */
213 struct list_head blocks;
214 /* linked list of freed fences */
215 struct list_head pool;
216 pipe_mutex mutex;
217 };
218
219 typedef boolean (*r600g_dma_blit_t)(struct pipe_context *ctx,
220 struct pipe_resource *dst,
221 unsigned dst_level,
222 unsigned dst_x, unsigned dst_y, unsigned dst_z,
223 struct pipe_resource *src,
224 unsigned src_level,
225 const struct pipe_box *src_box);
226
227 /* logging */
228 #define DBG_TEX_DEPTH (1 << 0)
229 #define DBG_COMPUTE (1 << 1)
230 #define DBG_VM (1 << 2)
231 #define DBG_TRACE_CS (1 << 3)
232 /* shaders */
233 #define DBG_FS (1 << 8)
234 #define DBG_VS (1 << 9)
235 #define DBG_GS (1 << 10)
236 #define DBG_PS (1 << 11)
237 #define DBG_CS (1 << 12)
238 /* features */
239 #define DBG_NO_HYPERZ (1 << 16)
240 #define DBG_NO_LLVM (1 << 17)
241 #define DBG_NO_CP_DMA (1 << 18)
242 #define DBG_NO_ASYNC_DMA (1 << 19)
243 #define DBG_NO_DISCARD_RANGE (1 << 20)
244 /* shader backend */
245 #define DBG_SB (1 << 21)
246 #define DBG_SB_CS (1 << 22)
247 #define DBG_SB_DRY_RUN (1 << 23)
248 #define DBG_SB_STAT (1 << 24)
249 #define DBG_SB_DUMP (1 << 25)
250 #define DBG_SB_NO_FALLBACK (1 << 26)
251 #define DBG_SB_DISASM (1 << 27)
252
253 struct r600_tiling_info {
254 unsigned num_channels;
255 unsigned num_banks;
256 unsigned group_bytes;
257 };
258
259 struct r600_screen {
260 struct pipe_screen screen;
261 struct radeon_winsys *ws;
262 unsigned debug_flags;
263 unsigned family;
264 enum chip_class chip_class;
265 struct radeon_info info;
266 bool has_streamout;
267 bool has_msaa;
268 bool has_cp_dma;
269 bool has_compressed_msaa_texturing;
270 struct r600_tiling_info tiling_info;
271 struct r600_pipe_fences fences;
272
273 /*for compute global memory binding, we allocate stuff here, instead of
274 * buffers.
275 * XXX: Not sure if this is the best place for global_pool. Also,
276 * it's not thread safe, so it won't work with multiple contexts. */
277 struct compute_memory_pool *global_pool;
278 struct r600_resource *trace_bo;
279 uint32_t *trace_ptr;
280 unsigned cs_count;
281 r600g_dma_blit_t dma_blit;
282
283 /* Auxiliary context. Mainly used to initialize resources.
284 * It must be locked prior to using and flushed before unlocking. */
285 struct pipe_context *aux_context;
286 pipe_mutex aux_context_lock;
287 };
288
289 struct r600_pipe_sampler_view {
290 struct pipe_sampler_view base;
291 struct r600_resource *tex_resource;
292 uint32_t tex_resource_words[8];
293 bool skip_mip_address_reloc;
294 };
295
296 struct r600_rasterizer_state {
297 struct r600_command_buffer buffer;
298 boolean flatshade;
299 boolean two_side;
300 unsigned sprite_coord_enable;
301 unsigned clip_plane_enable;
302 unsigned pa_sc_line_stipple;
303 unsigned pa_cl_clip_cntl;
304 float offset_units;
305 float offset_scale;
306 bool offset_enable;
307 bool scissor_enable;
308 bool multisample_enable;
309 };
310
311 struct r600_poly_offset_state {
312 struct r600_atom atom;
313 enum pipe_format zs_format;
314 float offset_units;
315 float offset_scale;
316 };
317
318 struct r600_blend_state {
319 struct r600_command_buffer buffer;
320 struct r600_command_buffer buffer_no_blend;
321 unsigned cb_target_mask;
322 unsigned cb_color_control;
323 unsigned cb_color_control_no_blend;
324 bool dual_src_blend;
325 bool alpha_to_one;
326 };
327
328 struct r600_dsa_state {
329 struct r600_command_buffer buffer;
330 unsigned alpha_ref;
331 ubyte valuemask[2];
332 ubyte writemask[2];
333 unsigned zwritemask;
334 unsigned sx_alpha_test_control;
335 };
336
337 struct r600_pipe_shader;
338
339 struct r600_pipe_shader_selector {
340 struct r600_pipe_shader *current;
341
342 struct tgsi_token *tokens;
343 struct pipe_stream_output_info so;
344
345 unsigned num_shaders;
346
347 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
348 unsigned type;
349
350 unsigned nr_ps_max_color_exports;
351 };
352
353 struct r600_pipe_sampler_state {
354 uint32_t tex_sampler_words[3];
355 union pipe_color_union border_color;
356 bool border_color_use;
357 bool seamless_cube_map;
358 };
359
360 /* needed for blitter save */
361 #define NUM_TEX_UNITS 16
362
363 struct r600_seamless_cube_map {
364 struct r600_atom atom;
365 bool enabled;
366 };
367
368 struct r600_samplerview_state {
369 struct r600_atom atom;
370 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
371 uint32_t enabled_mask;
372 uint32_t dirty_mask;
373 uint32_t compressed_depthtex_mask; /* which textures are depth */
374 uint32_t compressed_colortex_mask;
375 boolean dirty_txq_constants;
376 boolean dirty_buffer_constants;
377 };
378
379 struct r600_sampler_states {
380 struct r600_atom atom;
381 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
382 uint32_t enabled_mask;
383 uint32_t dirty_mask;
384 uint32_t has_bordercolor_mask; /* which states contain the border color */
385 };
386
387 struct r600_textures_info {
388 struct r600_samplerview_state views;
389 struct r600_sampler_states states;
390 bool is_array_sampler[NUM_TEX_UNITS];
391
392 /* cube array txq workaround */
393 uint32_t *txq_constants;
394 /* buffer related workarounds */
395 uint32_t *buffer_constants;
396 };
397
398 struct r600_fence {
399 struct pipe_reference reference;
400 unsigned index; /* in the shared bo */
401 struct r600_resource *sleep_bo;
402 struct list_head head;
403 };
404
405 #define FENCE_BLOCK_SIZE 16
406
407 struct r600_fence_block {
408 struct r600_fence fences[FENCE_BLOCK_SIZE];
409 struct list_head head;
410 };
411
412 #define R600_CONSTANT_ARRAY_SIZE 256
413 #define R600_RESOURCE_ARRAY_SIZE 160
414
415 struct r600_constbuf_state
416 {
417 struct r600_atom atom;
418 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
419 uint32_t enabled_mask;
420 uint32_t dirty_mask;
421 };
422
423 struct r600_vertexbuf_state
424 {
425 struct r600_atom atom;
426 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
427 uint32_t enabled_mask; /* non-NULL buffers */
428 uint32_t dirty_mask;
429 };
430
431 /* CSO (constant state object, in other words, immutable state). */
432 struct r600_cso_state
433 {
434 struct r600_atom atom;
435 void *cso; /* e.g. r600_blend_state */
436 struct r600_command_buffer *cb;
437 };
438
439 struct r600_scissor_state
440 {
441 struct r600_atom atom;
442 struct pipe_scissor_state scissor;
443 bool enable; /* r6xx only */
444 };
445
446 struct r600_fetch_shader {
447 struct r600_resource *buffer;
448 unsigned offset;
449 };
450
451 struct r600_shader_state {
452 struct r600_atom atom;
453 struct r600_pipe_shader_selector *shader;
454 };
455
456 struct r600_query_buffer {
457 /* The buffer where query results are stored. */
458 struct r600_resource *buf;
459 /* Offset of the next free result after current query data */
460 unsigned results_end;
461 /* If a query buffer is full, a new buffer is created and the old one
462 * is put in here. When we calculate the result, we sum up the samples
463 * from all buffers. */
464 struct r600_query_buffer *previous;
465 };
466
467 struct r600_query {
468 /* The query buffer and how many results are in it. */
469 struct r600_query_buffer buffer;
470 /* The type of query */
471 unsigned type;
472 /* Size of the result in memory for both begin_query and end_query,
473 * this can be one or two numbers, or it could even be a size of a structure. */
474 unsigned result_size;
475 /* The number of dwords for begin_query or end_query. */
476 unsigned num_cs_dw;
477 /* linked list of queries */
478 struct list_head list;
479 /* for custom non-GPU queries */
480 uint64_t begin_result;
481 uint64_t end_result;
482 };
483
484 struct r600_so_target {
485 struct pipe_stream_output_target b;
486
487 /* The buffer where BUFFER_FILLED_SIZE is stored. */
488 struct r600_resource *buf_filled_size;
489 unsigned buf_filled_size_offset;
490
491 unsigned stride_in_dw;
492 unsigned so_index;
493 };
494
495 struct r600_streamout {
496 struct r600_atom begin_atom;
497 bool begin_emitted;
498 unsigned num_dw_for_end;
499
500 unsigned enabled_mask;
501 unsigned num_targets;
502 struct r600_so_target *targets[PIPE_MAX_SO_BUFFERS];
503
504 unsigned append_bitmask;
505 bool suspended;
506 };
507
508 struct r600_ring {
509 struct radeon_winsys_cs *cs;
510 bool flushing;
511 void (*flush)(void *ctx, unsigned flags);
512 };
513
514 struct r600_rings {
515 struct r600_ring gfx;
516 struct r600_ring dma;
517 };
518
519 struct r600_context {
520 struct pipe_context context;
521 struct r600_screen *screen;
522 struct radeon_winsys *ws;
523 struct r600_rings rings;
524 struct blitter_context *blitter;
525 struct u_upload_mgr *uploader;
526 struct u_suballocator *allocator_so_filled_size;
527 struct u_suballocator *allocator_fetch_shader;
528 struct util_slab_mempool pool_transfers;
529
530 /* Hardware info. */
531 enum radeon_family family;
532 enum chip_class chip_class;
533 boolean has_vertex_cache;
534 boolean keep_tiling_flags;
535 unsigned default_ps_gprs, default_vs_gprs;
536 unsigned r6xx_num_clause_temp_gprs;
537 unsigned backend_mask;
538 unsigned max_db; /* for OQ */
539
540 /* current unaccounted memory usage */
541 uint64_t vram;
542 uint64_t gtt;
543
544 /* Miscellaneous state objects. */
545 void *custom_dsa_flush;
546 void *custom_blend_resolve;
547 void *custom_blend_decompress;
548 /* With rasterizer discard, there doesn't have to be a pixel shader.
549 * In that case, we bind this one: */
550 void *dummy_pixel_shader;
551 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
552 * bug where valid CMASK and FMASK are required to be present to avoid
553 * a hardlock in certain operations but aren't actually used
554 * for anything useful. */
555 struct r600_resource *dummy_fmask;
556 struct r600_resource *dummy_cmask;
557
558 /* State binding slots are here. */
559 struct r600_atom *atoms[R600_NUM_ATOMS];
560 /* States for CS initialization. */
561 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
562 /** Compute specific registers initializations. The start_cs_cmd atom
563 * must be emitted before start_compute_cs_cmd. */
564 struct r600_command_buffer start_compute_cs_cmd;
565 /* Register states. */
566 struct r600_alphatest_state alphatest_state;
567 struct r600_cso_state blend_state;
568 struct r600_blend_color blend_color;
569 struct r600_cb_misc_state cb_misc_state;
570 struct r600_clip_misc_state clip_misc_state;
571 struct r600_clip_state clip_state;
572 struct r600_db_misc_state db_misc_state;
573 struct r600_db_state db_state;
574 struct r600_cso_state dsa_state;
575 struct r600_framebuffer framebuffer;
576 struct r600_poly_offset_state poly_offset_state;
577 struct r600_cso_state rasterizer_state;
578 struct r600_sample_mask sample_mask;
579 struct r600_scissor_state scissor;
580 struct r600_seamless_cube_map seamless_cube_map;
581 struct r600_config_state config_state;
582 struct r600_stencil_ref_state stencil_ref;
583 struct r600_vgt_state vgt_state;
584 struct r600_viewport_state viewport;
585 /* Shaders and shader resources. */
586 struct r600_cso_state vertex_fetch_shader;
587 struct r600_shader_state vertex_shader;
588 struct r600_shader_state pixel_shader;
589 struct r600_cs_shader_state cs_shader_state;
590 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
591 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
592 /** Vertex buffers for fetch shaders */
593 struct r600_vertexbuf_state vertex_buffer_state;
594 /** Vertex buffers for compute shaders */
595 struct r600_vertexbuf_state cs_vertex_buffer_state;
596 struct r600_streamout streamout;
597
598 /* Additional context states. */
599 unsigned flags;
600 unsigned compute_cb_target_mask;
601 struct r600_pipe_shader_selector *ps_shader;
602 struct r600_pipe_shader_selector *vs_shader;
603 struct r600_rasterizer_state *rasterizer;
604 bool alpha_to_one;
605 bool force_blend_disable;
606 boolean dual_src_blend;
607 unsigned zwritemask;
608
609 /* Index buffer. */
610 struct pipe_index_buffer index_buffer;
611
612 /* Last draw state (-1 = unset). */
613 int last_primitive_type; /* Last primitive type used in draw_vbo. */
614 int last_start_instance;
615
616 /* Queries. */
617 /* The list of active queries. Only one query of each type can be active. */
618 int num_occlusion_queries;
619 int num_pipelinestat_queries;
620 /* Keep track of non-timer queries, because they should be suspended
621 * during context flushing.
622 * The timer queries (TIME_ELAPSED) shouldn't be suspended. */
623 struct list_head active_nontimer_queries;
624 unsigned num_cs_dw_nontimer_queries_suspend;
625 /* If queries have been suspended. */
626 bool nontimer_queries_suspended;
627 unsigned num_draw_calls;
628
629 /* Render condition. */
630 struct pipe_query *current_render_cond;
631 unsigned current_render_cond_mode;
632 boolean current_render_cond_cond;
633 boolean predicate_drawing;
634
635 void *sb_context;
636 struct r600_isa *isa;
637 };
638
639 static INLINE void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
640 struct r600_command_buffer *cb)
641 {
642 assert(cs->cdw + cb->num_dw <= RADEON_MAX_CMDBUF_DWORDS);
643 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->num_dw);
644 cs->cdw += cb->num_dw;
645 }
646
647 void r600_trace_emit(struct r600_context *rctx);
648
649 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
650 {
651 atom->emit(rctx, atom);
652 atom->dirty = false;
653 if (rctx->screen->trace_bo) {
654 r600_trace_emit(rctx);
655 }
656 }
657
658 static INLINE void r600_set_cso_state(struct r600_cso_state *state, void *cso)
659 {
660 state->cso = cso;
661 state->atom.dirty = cso != NULL;
662 }
663
664 static INLINE void r600_set_cso_state_with_cb(struct r600_cso_state *state, void *cso,
665 struct r600_command_buffer *cb)
666 {
667 state->cb = cb;
668 state->atom.num_dw = cb->num_dw;
669 r600_set_cso_state(state, cso);
670 }
671
672 /* compute_memory_pool.c */
673 struct compute_memory_pool;
674 void compute_memory_pool_delete(struct compute_memory_pool* pool);
675 struct compute_memory_pool* compute_memory_pool_new(
676 struct r600_screen *rscreen);
677
678 /* evergreen_state.c */
679 struct pipe_sampler_view *
680 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
681 struct pipe_resource *texture,
682 const struct pipe_sampler_view *state,
683 unsigned width0, unsigned height0);
684 void evergreen_init_common_regs(struct r600_command_buffer *cb,
685 enum chip_class ctx_chip_class,
686 enum radeon_family ctx_family,
687 int ctx_drm_minor);
688 void cayman_init_common_regs(struct r600_command_buffer *cb,
689 enum chip_class ctx_chip_class,
690 enum radeon_family ctx_family,
691 int ctx_drm_minor);
692
693 void evergreen_init_state_functions(struct r600_context *rctx);
694 void evergreen_init_atom_start_cs(struct r600_context *rctx);
695 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
696 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
697 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
698 void *evergreen_create_resolve_blend(struct r600_context *rctx);
699 void *evergreen_create_decompress_blend(struct r600_context *rctx);
700 boolean evergreen_is_format_supported(struct pipe_screen *screen,
701 enum pipe_format format,
702 enum pipe_texture_target target,
703 unsigned sample_count,
704 unsigned usage);
705 void evergreen_init_color_surface(struct r600_context *rctx,
706 struct r600_surface *surf);
707 void evergreen_init_color_surface_rat(struct r600_context *rctx,
708 struct r600_surface *surf);
709 void evergreen_update_db_shader_control(struct r600_context * rctx);
710
711 /* r600_blit.c */
712 void r600_copy_buffer(struct pipe_context *ctx, struct pipe_resource *dst, unsigned dstx,
713 struct pipe_resource *src, const struct pipe_box *src_box);
714 void r600_screen_clear_buffer(struct r600_screen *rscreen, struct pipe_resource *dst,
715 unsigned offset, unsigned size, unsigned char value);
716 void r600_init_blit_functions(struct r600_context *rctx);
717 void r600_blit_decompress_depth(struct pipe_context *ctx,
718 struct r600_texture *texture,
719 struct r600_texture *staging,
720 unsigned first_level, unsigned last_level,
721 unsigned first_layer, unsigned last_layer,
722 unsigned first_sample, unsigned last_sample);
723 void r600_decompress_depth_textures(struct r600_context *rctx,
724 struct r600_samplerview_state *textures);
725 void r600_decompress_color_textures(struct r600_context *rctx,
726 struct r600_samplerview_state *textures);
727
728 /* r600_buffer.c */
729 bool r600_init_resource(struct r600_screen *rscreen,
730 struct r600_resource *res,
731 unsigned size, unsigned alignment,
732 bool use_reusable_pool, unsigned usage);
733 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
734 const struct pipe_resource *templ,
735 unsigned alignment);
736
737 /* r600_pipe.c */
738 boolean r600_rings_is_buffer_referenced(struct r600_context *ctx,
739 struct radeon_winsys_cs_handle *buf,
740 enum radeon_bo_usage usage);
741 void *r600_buffer_mmap_sync_with_rings(struct r600_context *ctx,
742 struct r600_resource *resource,
743 unsigned usage);
744 const char * r600_llvm_gpu_string(enum radeon_family family);
745
746
747 /* r600_query.c */
748 void r600_init_query_functions(struct r600_context *rctx);
749 void r600_suspend_nontimer_queries(struct r600_context *ctx);
750 void r600_resume_nontimer_queries(struct r600_context *ctx);
751
752 /* r600_resource.c */
753 void r600_init_context_resource_functions(struct r600_context *r600);
754
755 /* r600_shader.c */
756 int r600_pipe_shader_create(struct pipe_context *ctx,
757 struct r600_pipe_shader *shader,
758 struct r600_shader_key key);
759
760 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
761
762 /* r600_state.c */
763 struct pipe_sampler_view *
764 r600_create_sampler_view_custom(struct pipe_context *ctx,
765 struct pipe_resource *texture,
766 const struct pipe_sampler_view *state,
767 unsigned width_first_level, unsigned height_first_level);
768 void r600_init_state_functions(struct r600_context *rctx);
769 void r600_init_atom_start_cs(struct r600_context *rctx);
770 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
771 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
772 void *r600_create_db_flush_dsa(struct r600_context *rctx);
773 void *r600_create_resolve_blend(struct r600_context *rctx);
774 void *r700_create_resolve_blend(struct r600_context *rctx);
775 void *r600_create_decompress_blend(struct r600_context *rctx);
776 bool r600_adjust_gprs(struct r600_context *rctx);
777 boolean r600_is_format_supported(struct pipe_screen *screen,
778 enum pipe_format format,
779 enum pipe_texture_target target,
780 unsigned sample_count,
781 unsigned usage);
782 void r600_update_db_shader_control(struct r600_context * rctx);
783
784 /* r600_texture.c */
785 void r600_init_screen_texture_functions(struct pipe_screen *screen);
786 void r600_init_surface_functions(struct r600_context *r600);
787 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
788 const unsigned char *swizzle_view,
789 uint32_t *word4_p, uint32_t *yuv_format_p);
790 unsigned r600_texture_get_offset(struct r600_texture *rtex,
791 unsigned level, unsigned layer);
792 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
793 struct pipe_resource *texture,
794 const struct pipe_surface *templ,
795 unsigned width, unsigned height);
796
797 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
798 const unsigned char *swizzle_view,
799 boolean vtx);
800
801 /* r600_hw_context.c */
802 void r600_get_backend_mask(struct r600_context *ctx);
803 void r600_context_flush(struct r600_context *ctx, unsigned flags);
804 void r600_begin_new_cs(struct r600_context *ctx);
805 void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence,
806 unsigned offset, unsigned value);
807 void r600_flush_emit(struct r600_context *ctx);
808 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
809 void r600_need_dma_space(struct r600_context *ctx, unsigned num_dw);
810 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
811 struct pipe_resource *dst, uint64_t dst_offset,
812 struct pipe_resource *src, uint64_t src_offset,
813 unsigned size);
814 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
815 struct pipe_resource *dst, uint64_t offset,
816 unsigned size, uint32_t clear_value);
817 void r600_dma_copy(struct r600_context *rctx,
818 struct pipe_resource *dst,
819 struct pipe_resource *src,
820 uint64_t dst_offset,
821 uint64_t src_offset,
822 uint64_t size);
823 boolean r600_dma_blit(struct pipe_context *ctx,
824 struct pipe_resource *dst,
825 unsigned dst_level,
826 unsigned dst_x, unsigned dst_y, unsigned dst_z,
827 struct pipe_resource *src,
828 unsigned src_level,
829 const struct pipe_box *src_box);
830 void r600_emit_streamout_begin(struct r600_context *ctx, struct r600_atom *atom);
831 void r600_emit_streamout_end(struct r600_context *ctx);
832
833 /*
834 * evergreen_hw_context.c
835 */
836 void evergreen_flush_vgt_streamout(struct r600_context *ctx);
837 void evergreen_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit);
838 void evergreen_dma_copy(struct r600_context *rctx,
839 struct pipe_resource *dst,
840 struct pipe_resource *src,
841 uint64_t dst_offset,
842 uint64_t src_offset,
843 uint64_t size);
844 boolean evergreen_dma_blit(struct pipe_context *ctx,
845 struct pipe_resource *dst,
846 unsigned dst_level,
847 unsigned dst_x, unsigned dst_y, unsigned dst_z,
848 struct pipe_resource *src,
849 unsigned src_level,
850 const struct pipe_box *src_box);
851
852 /* r600_state_common.c */
853 void r600_init_common_state_functions(struct r600_context *rctx);
854 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
855 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
856 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
857 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
858 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
859 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
860 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom);
861 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
862 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
863 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
864 unsigned num_dw);
865 void r600_vertex_buffers_dirty(struct r600_context *rctx);
866 void r600_sampler_views_dirty(struct r600_context *rctx,
867 struct r600_samplerview_state *state);
868 void r600_sampler_states_dirty(struct r600_context *rctx,
869 struct r600_sampler_states *state);
870 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
871 void r600_streamout_buffers_dirty(struct r600_context *rctx);
872 void r600_draw_rectangle(struct blitter_context *blitter,
873 int x1, int y1, int x2, int y2, float depth,
874 enum blitter_attrib_type type, const union pipe_color_union *attrib);
875 uint32_t r600_translate_stencil_op(int s_op);
876 uint32_t r600_translate_fill(uint32_t func);
877 unsigned r600_tex_wrap(unsigned wrap);
878 unsigned r600_tex_filter(unsigned filter);
879 unsigned r600_tex_mipfilter(unsigned filter);
880 unsigned r600_tex_compare(unsigned compare);
881 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
882
883 /* r600_uvd.c */
884 struct pipe_video_decoder *r600_uvd_create_decoder(struct pipe_context *context,
885 enum pipe_video_profile profile,
886 enum pipe_video_entrypoint entrypoint,
887 enum pipe_video_chroma_format chroma_format,
888 unsigned width, unsigned height,
889 unsigned max_references, bool expect_chunked_decode);
890
891 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
892 const struct pipe_video_buffer *tmpl);
893
894 int r600_uvd_get_video_param(struct pipe_screen *screen,
895 enum pipe_video_profile profile,
896 enum pipe_video_cap param);
897
898 /*
899 * Helpers for building command buffers
900 */
901
902 #define PKT3_SET_CONFIG_REG 0x68
903 #define PKT3_SET_CONTEXT_REG 0x69
904 #define PKT3_SET_CTL_CONST 0x6F
905 #define PKT3_SET_LOOP_CONST 0x6C
906
907 #define R600_CONFIG_REG_OFFSET 0x08000
908 #define R600_CONTEXT_REG_OFFSET 0x28000
909 #define R600_CTL_CONST_OFFSET 0x3CFF0
910 #define R600_LOOP_CONST_OFFSET 0X0003E200
911 #define EG_LOOP_CONST_OFFSET 0x0003A200
912
913 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
914 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
915 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
916 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
917 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
918
919 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
920
921 /*Evergreen Compute packet3*/
922 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
923
924 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
925 {
926 cb->buf[cb->num_dw++] = value;
927 }
928
929 static INLINE void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
930 {
931 assert(cb->num_dw+num <= cb->max_num_dw);
932 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
933 cb->num_dw += num;
934 }
935
936 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
937 {
938 assert(reg < R600_CONTEXT_REG_OFFSET);
939 assert(cb->num_dw+2+num <= cb->max_num_dw);
940 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
941 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
942 }
943
944 /**
945 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
946 * shaders.
947 */
948 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
949 {
950 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
951 assert(cb->num_dw+2+num <= cb->max_num_dw);
952 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
953 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
954 }
955
956 /**
957 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
958 * shaders.
959 */
960 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
961 {
962 assert(reg >= R600_CTL_CONST_OFFSET);
963 assert(cb->num_dw+2+num <= cb->max_num_dw);
964 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
965 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
966 }
967
968 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
969 {
970 assert(reg >= R600_LOOP_CONST_OFFSET);
971 assert(cb->num_dw+2+num <= cb->max_num_dw);
972 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
973 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
974 }
975
976 /**
977 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
978 * shaders.
979 */
980 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
981 {
982 assert(reg >= EG_LOOP_CONST_OFFSET);
983 assert(cb->num_dw+2+num <= cb->max_num_dw);
984 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
985 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
986 }
987
988 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
989 {
990 r600_store_config_reg_seq(cb, reg, 1);
991 r600_store_value(cb, value);
992 }
993
994 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
995 {
996 r600_store_context_reg_seq(cb, reg, 1);
997 r600_store_value(cb, value);
998 }
999
1000 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
1001 {
1002 r600_store_ctl_const_seq(cb, reg, 1);
1003 r600_store_value(cb, value);
1004 }
1005
1006 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
1007 {
1008 r600_store_loop_const_seq(cb, reg, 1);
1009 r600_store_value(cb, value);
1010 }
1011
1012 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
1013 {
1014 eg_store_loop_const_seq(cb, reg, 1);
1015 r600_store_value(cb, value);
1016 }
1017
1018 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
1019 void r600_release_command_buffer(struct r600_command_buffer *cb);
1020
1021 /*
1022 * Helpers for emitting state into a command stream directly.
1023 */
1024 static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx,
1025 struct r600_ring *ring,
1026 struct r600_resource *rbo,
1027 enum radeon_bo_usage usage)
1028 {
1029 assert(usage);
1030 /* make sure that all previous ring use are flushed so everything
1031 * look serialized from driver pov
1032 */
1033 if (!ring->flushing) {
1034 if (ring == &ctx->rings.gfx) {
1035 if (ctx->rings.dma.cs) {
1036 /* flush dma ring */
1037 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
1038 }
1039 } else {
1040 /* flush gfx ring */
1041 ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
1042 }
1043 }
1044 return ctx->ws->cs_add_reloc(ring->cs, rbo->cs_buf, usage, rbo->domains) * 4;
1045 }
1046
1047 static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
1048 {
1049 cs->buf[cs->cdw++] = value;
1050 }
1051
1052 static INLINE void r600_write_array(struct radeon_winsys_cs *cs, unsigned num, unsigned *ptr)
1053 {
1054 assert(cs->cdw+num <= RADEON_MAX_CMDBUF_DWORDS);
1055 memcpy(&cs->buf[cs->cdw], ptr, num * sizeof(ptr[0]));
1056 cs->cdw += num;
1057 }
1058
1059 static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
1060 {
1061 assert(reg < R600_CONTEXT_REG_OFFSET);
1062 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
1063 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
1064 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
1065 }
1066
1067 static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
1068 {
1069 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
1070 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
1071 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
1072 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
1073 }
1074
1075 static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
1076 {
1077 r600_write_context_reg_seq(cs, reg, num);
1078 /* Set the compute bit on the packet header */
1079 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
1080 }
1081
1082 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
1083 {
1084 assert(reg >= R600_CTL_CONST_OFFSET);
1085 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
1086 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
1087 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
1088 }
1089
1090 static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
1091 {
1092 r600_write_config_reg_seq(cs, reg, 1);
1093 r600_write_value(cs, value);
1094 }
1095
1096 static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
1097 {
1098 r600_write_context_reg_seq(cs, reg, 1);
1099 r600_write_value(cs, value);
1100 }
1101
1102 static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
1103 {
1104 r600_write_compute_context_reg_seq(cs, reg, 1);
1105 r600_write_value(cs, value);
1106 }
1107
1108 static INLINE void r600_write_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
1109 {
1110 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
1111 r600_write_compute_context_reg(cs, reg, value);
1112 } else {
1113 r600_write_context_reg(cs, reg, value);
1114 }
1115
1116 }
1117 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
1118 {
1119 r600_write_ctl_const_seq(cs, reg, 1);
1120 r600_write_value(cs, value);
1121 }
1122
1123 /*
1124 * common helpers
1125 */
1126 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
1127 {
1128 return value * (1 << frac_bits);
1129 }
1130 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
1131
1132 static inline unsigned r600_tex_aniso_filter(unsigned filter)
1133 {
1134 if (filter <= 1) return 0;
1135 if (filter <= 2) return 1;
1136 if (filter <= 4) return 2;
1137 if (filter <= 8) return 3;
1138 /* else */ return 4;
1139 }
1140
1141 /* 12.4 fixed-point */
1142 static INLINE unsigned r600_pack_float_12p4(float x)
1143 {
1144 return x <= 0 ? 0 :
1145 x >= 4096 ? 0xffff : x * 16;
1146 }
1147
1148 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
1149 {
1150 struct r600_screen *rscreen = (struct r600_screen*)screen;
1151 struct r600_resource *rresource = (struct r600_resource*)resource;
1152
1153 return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
1154 }
1155
1156 static INLINE void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
1157 {
1158 struct r600_context *rctx = (struct r600_context *)ctx;
1159 struct r600_resource *rr = (struct r600_resource *)r;
1160
1161 if (r == NULL) {
1162 return;
1163 }
1164
1165 /*
1166 * The idea is to compute a gross estimate of memory requirement of
1167 * each draw call. After each draw call, memory will be precisely
1168 * accounted. So the uncertainty is only on the current draw call.
1169 * In practice this gave very good estimate (+/- 10% of the target
1170 * memory limit).
1171 */
1172 if (rr->domains & RADEON_DOMAIN_GTT) {
1173 rctx->gtt += rr->buf->size;
1174 }
1175 if (rr->domains & RADEON_DOMAIN_VRAM) {
1176 rctx->vram += rr->buf->size;
1177 }
1178 }
1179
1180 #endif