2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "util/u_slab.h"
31 #include "r600_llvm.h"
32 #include "r600_public.h"
33 #include "r600_shader.h"
34 #include "r600_resource.h"
35 #include "evergreen_compute.h"
37 #define R600_MAX_CONST_BUFFERS 2
38 #define R600_MAX_CONST_BUFFER_SIZE 4096
40 #ifdef PIPE_ARCH_BIG_ENDIAN
41 #define R600_BIG_ENDIAN 1
43 #define R600_BIG_ENDIAN 0
46 enum r600_atom_flags
{
47 /* When set, atoms are added at the beginning of the dirty list
48 * instead of the end. */
52 /* This encapsulates a state or an operation which can emitted into the GPU
53 * command stream. It's not limited to states only, it can be used for anything
54 * that wants to write commands into the CS (e.g. cache flushes). */
56 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
);
59 enum r600_atom_flags flags
;
62 struct list_head head
;
65 /* This is an atom containing GPU commands that never change.
66 * This is supposed to be copied directly into the CS. */
67 struct r600_command_buffer
{
68 struct r600_atom atom
;
74 struct r600_surface_sync_cmd
{
75 struct r600_atom atom
;
76 unsigned flush_flags
; /* CP_COHER_CNTL */
79 struct r600_db_misc_state
{
80 struct r600_atom atom
;
81 bool occlusion_query_enabled
;
82 bool flush_depthstencil_through_cb
;
83 bool copy_depth
, copy_stencil
;
86 struct r600_cb_misc_state
{
87 struct r600_atom atom
;
88 unsigned cb_color_control
; /* this comes from blend state */
89 unsigned blend_colormask
; /* 8*4 bits for 8 RGBA colorbuffers */
91 unsigned nr_ps_color_outputs
;
96 struct r600_alphatest_state
{
97 struct r600_atom atom
;
98 unsigned sx_alpha_test_control
; /* this comes from dsa state */
99 unsigned sx_alpha_ref
; /* this comes from dsa state */
101 bool cb0_export_16bpc
; /* from set_framebuffer_state */
104 struct r600_cs_shader_state
{
105 struct r600_atom atom
;
106 struct r600_pipe_compute
*shader
;
109 enum r600_pipe_state_id
{
110 R600_PIPE_STATE_BLEND
= 0,
111 R600_PIPE_STATE_BLEND_COLOR
,
112 R600_PIPE_STATE_CONFIG
,
113 R600_PIPE_STATE_SEAMLESS_CUBEMAP
,
114 R600_PIPE_STATE_CLIP
,
115 R600_PIPE_STATE_SCISSOR
,
116 R600_PIPE_STATE_VIEWPORT
,
117 R600_PIPE_STATE_RASTERIZER
,
119 R600_PIPE_STATE_FRAMEBUFFER
,
121 R600_PIPE_STATE_STENCIL_REF
,
122 R600_PIPE_STATE_PS_SHADER
,
123 R600_PIPE_STATE_VS_SHADER
,
124 R600_PIPE_STATE_CONSTANT
,
125 R600_PIPE_STATE_SAMPLER
,
126 R600_PIPE_STATE_RESOURCE
,
127 R600_PIPE_STATE_POLYGON_OFFSET
,
128 R600_PIPE_STATE_FETCH_SHADER
,
133 struct compute_memory_pool
;
134 void compute_memory_pool_delete(struct compute_memory_pool
* pool
);
135 struct compute_memory_pool
* compute_memory_pool_new(
136 struct r600_screen
*rscreen
);
138 struct r600_pipe_fences
{
139 struct r600_resource
*bo
;
142 /* linked list of preallocated blocks */
143 struct list_head blocks
;
144 /* linked list of freed fences */
145 struct list_head pool
;
150 struct pipe_screen screen
;
151 struct radeon_winsys
*ws
;
153 enum chip_class chip_class
;
154 struct radeon_info info
;
156 struct r600_tiling_info tiling_info
;
157 struct r600_pipe_fences fences
;
159 /*for compute global memory binding, we allocate stuff here, instead of
161 * XXX: Not sure if this is the best place for global_pool. Also,
162 * it's not thread safe, so it won't work with multiple contexts. */
163 struct compute_memory_pool
*global_pool
;
166 struct r600_pipe_sampler_view
{
167 struct pipe_sampler_view base
;
168 struct r600_resource
*tex_resource
;
169 uint32_t tex_resource_words
[8];
172 struct r600_pipe_rasterizer
{
173 struct r600_pipe_state rstate
;
176 unsigned sprite_coord_enable
;
177 unsigned clip_plane_enable
;
178 unsigned pa_sc_line_stipple
;
179 unsigned pa_cl_clip_cntl
;
183 bool multisample_enable
;
186 struct r600_pipe_blend
{
187 struct r600_pipe_state rstate
;
188 unsigned cb_target_mask
;
189 unsigned cb_color_control
;
194 struct r600_pipe_dsa
{
195 struct r600_pipe_state rstate
;
199 unsigned sx_alpha_test_control
;
202 struct r600_vertex_element
205 struct pipe_vertex_element elements
[PIPE_MAX_ATTRIBS
];
206 struct r600_resource
*fetch_shader
;
208 struct r600_pipe_state rstate
;
211 struct r600_pipe_shader
;
213 struct r600_pipe_shader_selector
{
214 struct r600_pipe_shader
*current
;
216 struct tgsi_token
*tokens
;
217 struct pipe_stream_output_info so
;
219 unsigned num_shaders
;
221 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
224 unsigned nr_ps_max_color_exports
;
227 struct r600_pipe_shader
{
228 struct r600_pipe_shader_selector
*selector
;
229 struct r600_pipe_shader
*next_variant
;
230 struct r600_shader shader
;
231 struct r600_pipe_state rstate
;
232 struct r600_resource
*bo
;
233 struct r600_resource
*bo_fetch
;
234 struct r600_vertex_element vertex_elements
;
235 unsigned sprite_coord_enable
;
237 unsigned pa_cl_vs_out_cntl
;
238 unsigned nr_ps_color_outputs
;
240 unsigned db_shader_control
;
241 unsigned ps_depth_export
;
244 struct r600_pipe_sampler_state
{
245 uint32_t tex_sampler_words
[3];
246 uint32_t border_color
[4];
247 bool border_color_use
;
248 bool seamless_cube_map
;
251 /* needed for blitter save */
252 #define NUM_TEX_UNITS 16
254 struct r600_seamless_cube_map
{
255 struct r600_atom atom
;
259 struct r600_samplerview_state
{
260 struct r600_atom atom
;
261 struct r600_pipe_sampler_view
*views
[NUM_TEX_UNITS
];
262 uint32_t enabled_mask
;
264 uint32_t depth_texture_mask
; /* which textures are depth */
267 struct r600_textures_info
{
268 struct r600_samplerview_state views
;
269 struct r600_atom atom_sampler
;
270 struct r600_pipe_sampler_state
*samplers
[NUM_TEX_UNITS
];
272 bool is_array_sampler
[NUM_TEX_UNITS
];
276 struct pipe_reference reference
;
277 unsigned index
; /* in the shared bo */
278 struct r600_resource
*sleep_bo
;
279 struct list_head head
;
282 #define FENCE_BLOCK_SIZE 16
284 struct r600_fence_block
{
285 struct r600_fence fences
[FENCE_BLOCK_SIZE
];
286 struct list_head head
;
289 #define R600_CONSTANT_ARRAY_SIZE 256
290 #define R600_RESOURCE_ARRAY_SIZE 160
292 struct r600_stencil_ref
299 struct r600_constbuf_state
301 struct r600_atom atom
;
302 struct pipe_constant_buffer cb
[PIPE_MAX_CONSTANT_BUFFERS
];
303 uint32_t enabled_mask
;
307 struct r600_vertexbuf_state
309 struct r600_atom atom
;
310 struct pipe_vertex_buffer vb
[PIPE_MAX_ATTRIBS
];
311 uint32_t enabled_mask
; /* non-NULL buffers */
315 struct r600_context
{
316 struct pipe_context context
;
317 struct blitter_context
*blitter
;
318 enum radeon_family family
;
319 enum chip_class chip_class
;
320 boolean has_vertex_cache
;
321 unsigned r6xx_num_clause_temp_gprs
;
322 void *custom_dsa_flush
;
323 struct r600_screen
*screen
;
324 struct radeon_winsys
*ws
;
325 struct r600_pipe_state
*states
[R600_PIPE_NSTATES
];
326 struct r600_vertex_element
*vertex_elements
;
327 struct pipe_framebuffer_state framebuffer
;
328 unsigned compute_cb_target_mask
;
329 unsigned db_shader_control
;
330 unsigned pa_sc_line_stipple
;
331 unsigned pa_cl_clip_cntl
;
332 /* for saving when using blitter */
333 struct pipe_stencil_ref stencil_ref
;
334 struct pipe_viewport_state viewport
;
335 struct pipe_clip_state clip
;
336 struct r600_pipe_shader_selector
*ps_shader
;
337 struct r600_pipe_shader_selector
*vs_shader
;
338 struct r600_pipe_rasterizer
*rasterizer
;
339 struct r600_pipe_state vgt
;
340 struct r600_pipe_state spi
;
341 struct pipe_query
*current_render_cond
;
342 unsigned current_render_cond_mode
;
343 struct pipe_query
*saved_render_cond
;
344 unsigned saved_render_cond_mode
;
345 /* shader information */
348 unsigned sprite_coord_enable
;
350 boolean export_16bpc
;
353 bool multisample_enable
;
356 struct u_upload_mgr
*uploader
;
357 struct util_slab_mempool pool_transfers
;
359 unsigned default_ps_gprs
, default_vs_gprs
;
361 /* States based on r600_atom. */
362 struct list_head dirty_states
;
363 struct r600_command_buffer start_cs_cmd
; /* invariant state mostly */
364 /** Compute specific registers initializations. The start_cs_cmd atom
365 * must be emitted before start_compute_cs_cmd. */
366 struct r600_command_buffer start_compute_cs_cmd
;
367 struct r600_surface_sync_cmd surface_sync_cmd
;
368 struct r600_atom r6xx_flush_and_inv_cmd
;
369 struct r600_alphatest_state alphatest_state
;
370 struct r600_cb_misc_state cb_misc_state
;
371 struct r600_db_misc_state db_misc_state
;
372 /** Vertex buffers for fetch shaders */
373 struct r600_vertexbuf_state vertex_buffer_state
;
374 /** Vertex buffers for compute shaders */
375 struct r600_vertexbuf_state cs_vertex_buffer_state
;
376 struct r600_constbuf_state vs_constbuf_state
;
377 struct r600_constbuf_state ps_constbuf_state
;
378 struct r600_textures_info vs_samplers
;
379 struct r600_textures_info ps_samplers
;
380 struct r600_seamless_cube_map seamless_cube_map
;
381 struct r600_cs_shader_state cs_shader_state
;
383 struct radeon_winsys_cs
*cs
;
385 struct r600_range
*range
;
387 struct r600_block
**blocks
;
388 struct list_head dirty
;
389 struct list_head enable_list
;
390 unsigned pm4_dirty_cdwords
;
391 unsigned ctx_pm4_ndwords
;
393 /* The list of active queries. Only one query of each type can be active. */
394 int num_occlusion_queries
;
396 /* Manage queries in two separate groups:
397 * The timer ones and the others (streamout, occlusion).
399 * We do this because we should only suspend non-timer queries for u_blitter,
400 * and later if the non-timer queries are suspended, the context flush should
401 * only suspend and resume the timer queries. */
402 struct list_head active_timer_queries
;
403 unsigned num_cs_dw_timer_queries_suspend
;
404 struct list_head active_nontimer_queries
;
405 unsigned num_cs_dw_nontimer_queries_suspend
;
407 unsigned num_cs_dw_streamout_end
;
409 unsigned backend_mask
;
410 unsigned max_db
; /* for OQ */
412 boolean predicate_drawing
;
414 unsigned num_so_targets
;
415 struct r600_so_target
*so_targets
[PIPE_MAX_SO_BUFFERS
];
416 boolean streamout_start
;
417 unsigned streamout_append_bitmask
;
419 /* There is no scissor enable bit on r6xx, so we must use a workaround.
420 * These track the current scissor state. */
422 struct pipe_scissor_state scissor_state
;
424 /* With rasterizer discard, there doesn't have to be a pixel shader.
425 * In that case, we bind this one: */
426 void *dummy_pixel_shader
;
428 boolean dual_src_blend
;
431 struct pipe_index_buffer index_buffer
;
434 static INLINE
void r600_emit_atom(struct r600_context
*rctx
, struct r600_atom
*atom
)
436 atom
->emit(rctx
, atom
);
438 if (atom
->head
.next
&& atom
->head
.prev
)
439 LIST_DELINIT(&atom
->head
);
442 static INLINE
void r600_atom_dirty(struct r600_context
*rctx
, struct r600_atom
*state
)
445 if (state
->flags
& EMIT_EARLY
) {
446 LIST_ADD(&state
->head
, &rctx
->dirty_states
);
448 LIST_ADDTAIL(&state
->head
, &rctx
->dirty_states
);
454 /* evergreen_state.c */
455 void evergreen_init_state_functions(struct r600_context
*rctx
);
456 void evergreen_init_atom_start_cs(struct r600_context
*rctx
);
457 void evergreen_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
458 void evergreen_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
459 void evergreen_fetch_shader(struct pipe_context
*ctx
, struct r600_vertex_element
*ve
);
460 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
);
461 void evergreen_polygon_offset_update(struct r600_context
*rctx
);
462 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
463 enum pipe_format format
,
464 enum pipe_texture_target target
,
465 unsigned sample_count
,
467 void evergreen_init_color_surface(struct r600_context
*rctx
,
468 struct r600_surface
*surf
);
469 void evergreen_update_dual_export_state(struct r600_context
* rctx
);
472 void r600_copy_buffer(struct pipe_context
*ctx
, struct
473 pipe_resource
*dst
, unsigned dstx
,
474 struct pipe_resource
*src
, const struct pipe_box
*src_box
);
475 void r600_init_blit_functions(struct r600_context
*rctx
);
476 void r600_blit_uncompress_depth(struct pipe_context
*ctx
,
477 struct r600_resource_texture
*texture
,
478 struct r600_resource_texture
*staging
,
479 unsigned first_level
, unsigned last_level
,
480 unsigned first_layer
, unsigned last_layer
);
481 void r600_flush_depth_textures(struct r600_context
*rctx
,
482 struct r600_samplerview_state
*textures
);
484 bool r600_init_resource(struct r600_screen
*rscreen
,
485 struct r600_resource
*res
,
486 unsigned size
, unsigned alignment
,
487 unsigned bind
, unsigned usage
);
488 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
489 const struct pipe_resource
*templ
);
492 void r600_flush(struct pipe_context
*ctx
, struct pipe_fence_handle
**fence
,
496 void r600_init_query_functions(struct r600_context
*rctx
);
497 void r600_suspend_nontimer_queries(struct r600_context
*ctx
);
498 void r600_resume_nontimer_queries(struct r600_context
*ctx
);
499 void r600_suspend_timer_queries(struct r600_context
*ctx
);
500 void r600_resume_timer_queries(struct r600_context
*ctx
);
502 /* r600_resource.c */
503 void r600_init_context_resource_functions(struct r600_context
*r600
);
506 int r600_pipe_shader_create(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
508 int r600_compute_shader_create(struct pipe_context
* ctx
,
509 LLVMModuleRef mod
, struct r600_bytecode
* bytecode
);
511 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
514 void r600_set_scissor_state(struct r600_context
*rctx
,
515 const struct pipe_scissor_state
*state
);
516 void r600_init_state_functions(struct r600_context
*rctx
);
517 void r600_init_atom_start_cs(struct r600_context
*rctx
);
518 void r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
519 void r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
520 void r600_fetch_shader(struct pipe_context
*ctx
, struct r600_vertex_element
*ve
);
521 void *r600_create_db_flush_dsa(struct r600_context
*rctx
);
522 void r600_polygon_offset_update(struct r600_context
*rctx
);
523 void r600_adjust_gprs(struct r600_context
*rctx
);
524 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
525 enum pipe_format format
,
526 enum pipe_texture_target target
,
527 unsigned sample_count
,
529 void r600_update_dual_export_state(struct r600_context
* rctx
);
532 void r600_init_screen_texture_functions(struct pipe_screen
*screen
);
533 void r600_init_surface_functions(struct r600_context
*r600
);
534 uint32_t r600_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
535 const unsigned char *swizzle_view
,
536 uint32_t *word4_p
, uint32_t *yuv_format_p
);
537 unsigned r600_texture_get_offset(struct r600_resource_texture
*rtex
,
538 unsigned level
, unsigned layer
);
540 /* r600_translate.c */
541 void r600_translate_index_buffer(struct r600_context
*r600
,
542 struct pipe_index_buffer
*ib
,
545 /* r600_state_common.c */
546 void r600_init_atom(struct r600_atom
*atom
,
547 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
548 unsigned num_dw
, enum r600_atom_flags flags
);
549 void r600_init_common_atoms(struct r600_context
*rctx
);
550 unsigned r600_get_cb_flush_flags(struct r600_context
*rctx
);
551 void r600_texture_barrier(struct pipe_context
*ctx
);
552 void r600_set_index_buffer(struct pipe_context
*ctx
,
553 const struct pipe_index_buffer
*ib
);
554 void r600_vertex_buffers_dirty(struct r600_context
*rctx
);
555 void r600_set_vertex_buffers(struct pipe_context
*ctx
, unsigned count
,
556 const struct pipe_vertex_buffer
*input
);
557 void r600_sampler_views_dirty(struct r600_context
*rctx
,
558 struct r600_samplerview_state
*state
);
559 void r600_set_sampler_views(struct r600_context
*rctx
,
560 struct r600_textures_info
*dst
,
562 struct pipe_sampler_view
**views
);
563 void r600_bind_vs_samplers(struct pipe_context
*ctx
, unsigned count
, void **states
);
564 void r600_bind_ps_samplers(struct pipe_context
*ctx
, unsigned count
, void **states
);
565 void *r600_create_vertex_elements(struct pipe_context
*ctx
,
567 const struct pipe_vertex_element
*elements
);
568 void r600_delete_vertex_element(struct pipe_context
*ctx
, void *state
);
569 void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
);
570 void r600_set_blend_color(struct pipe_context
*ctx
,
571 const struct pipe_blend_color
*state
);
572 void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
);
573 void r600_set_max_scissor(struct r600_context
*rctx
);
574 void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
);
575 void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
);
576 void r600_sampler_view_destroy(struct pipe_context
*ctx
,
577 struct pipe_sampler_view
*state
);
578 void r600_delete_sampler(struct pipe_context
*ctx
, void *state
);
579 void r600_delete_state(struct pipe_context
*ctx
, void *state
);
580 void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
);
581 void *r600_create_shader_state_ps(struct pipe_context
*ctx
,
582 const struct pipe_shader_state
*state
);
583 void *r600_create_shader_state_vs(struct pipe_context
*ctx
,
584 const struct pipe_shader_state
*state
);
585 void r600_bind_ps_shader(struct pipe_context
*ctx
, void *state
);
586 void r600_bind_vs_shader(struct pipe_context
*ctx
, void *state
);
587 void r600_delete_ps_shader(struct pipe_context
*ctx
, void *state
);
588 void r600_delete_vs_shader(struct pipe_context
*ctx
, void *state
);
589 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
);
590 void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
591 struct pipe_constant_buffer
*cb
);
592 struct pipe_stream_output_target
*
593 r600_create_so_target(struct pipe_context
*ctx
,
594 struct pipe_resource
*buffer
,
595 unsigned buffer_offset
,
596 unsigned buffer_size
);
597 void r600_so_target_destroy(struct pipe_context
*ctx
,
598 struct pipe_stream_output_target
*target
);
599 void r600_set_so_targets(struct pipe_context
*ctx
,
600 unsigned num_targets
,
601 struct pipe_stream_output_target
**targets
,
602 unsigned append_bitmask
);
603 void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
604 const struct pipe_stencil_ref
*state
);
605 void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
);
606 uint32_t r600_translate_stencil_op(int s_op
);
607 uint32_t r600_translate_fill(uint32_t func
);
608 unsigned r600_tex_wrap(unsigned wrap
);
609 unsigned r600_tex_filter(unsigned filter
);
610 unsigned r600_tex_mipfilter(unsigned filter
);
611 unsigned r600_tex_compare(unsigned compare
);
614 * Helpers for building command buffers
617 #define PKT3_SET_CONFIG_REG 0x68
618 #define PKT3_SET_CONTEXT_REG 0x69
619 #define PKT3_SET_CTL_CONST 0x6F
620 #define PKT3_SET_LOOP_CONST 0x6C
622 #define R600_CONFIG_REG_OFFSET 0x08000
623 #define R600_CONTEXT_REG_OFFSET 0x28000
624 #define R600_CTL_CONST_OFFSET 0x3CFF0
625 #define R600_LOOP_CONST_OFFSET 0X0003E200
626 #define EG_LOOP_CONST_OFFSET 0x0003A200
628 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
629 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
630 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
631 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
632 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
634 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
636 /*Evergreen Compute packet3*/
637 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
639 static INLINE
void r600_store_value(struct r600_command_buffer
*cb
, unsigned value
)
641 cb
->buf
[cb
->atom
.num_dw
++] = value
;
644 static INLINE
void r600_store_config_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
646 assert(reg
< R600_CONTEXT_REG_OFFSET
);
647 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
648 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
649 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
653 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
656 static INLINE
void r600_store_context_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
658 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
659 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
660 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0) | cb
->pkt_flags
;
661 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
665 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
668 static INLINE
void r600_store_ctl_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
670 assert(reg
>= R600_CTL_CONST_OFFSET
);
671 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
672 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0) | cb
->pkt_flags
;
673 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
676 static INLINE
void r600_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
678 assert(reg
>= R600_LOOP_CONST_OFFSET
);
679 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
680 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0);
681 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- R600_LOOP_CONST_OFFSET
) >> 2;
685 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
688 static INLINE
void eg_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
690 assert(reg
>= EG_LOOP_CONST_OFFSET
);
691 assert(cb
->atom
.num_dw
+2+num
<= cb
->max_num_dw
);
692 cb
->buf
[cb
->atom
.num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0) | cb
->pkt_flags
;
693 cb
->buf
[cb
->atom
.num_dw
++] = (reg
- EG_LOOP_CONST_OFFSET
) >> 2;
696 static INLINE
void r600_store_config_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
698 r600_store_config_reg_seq(cb
, reg
, 1);
699 r600_store_value(cb
, value
);
702 static INLINE
void r600_store_context_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
704 r600_store_context_reg_seq(cb
, reg
, 1);
705 r600_store_value(cb
, value
);
708 static INLINE
void r600_store_ctl_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
710 r600_store_ctl_const_seq(cb
, reg
, 1);
711 r600_store_value(cb
, value
);
714 static INLINE
void r600_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
716 r600_store_loop_const_seq(cb
, reg
, 1);
717 r600_store_value(cb
, value
);
720 static INLINE
void eg_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
722 eg_store_loop_const_seq(cb
, reg
, 1);
723 r600_store_value(cb
, value
);
726 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
, enum r600_atom_flags flags
);
727 void r600_release_command_buffer(struct r600_command_buffer
*cb
);
730 * Helpers for emitting state into a command stream directly.
733 static INLINE
unsigned r600_context_bo_reloc(struct r600_context
*ctx
, struct r600_resource
*rbo
,
734 enum radeon_bo_usage usage
)
737 return ctx
->ws
->cs_add_reloc(ctx
->cs
, rbo
->cs_buf
, usage
, rbo
->domains
) * 4;
740 static INLINE
void r600_write_value(struct radeon_winsys_cs
*cs
, unsigned value
)
742 cs
->buf
[cs
->cdw
++] = value
;
745 static INLINE
void r600_write_array(struct radeon_winsys_cs
*cs
, unsigned num
, unsigned *ptr
)
747 assert(cs
->cdw
+num
<= RADEON_MAX_CMDBUF_DWORDS
);
748 memcpy(&cs
->buf
[cs
->cdw
], ptr
, num
* sizeof(ptr
[0]));
752 static INLINE
void r600_write_config_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
754 assert(reg
< R600_CONTEXT_REG_OFFSET
);
755 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
756 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
757 cs
->buf
[cs
->cdw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
760 static INLINE
void r600_write_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
762 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
763 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
764 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0);
765 cs
->buf
[cs
->cdw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
768 static INLINE
void r600_write_compute_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
770 r600_write_context_reg_seq(cs
, reg
, num
);
771 /* Set the compute bit on the packet header */
772 cs
->buf
[cs
->cdw
- 2] |= RADEON_CP_PACKET3_COMPUTE_MODE
;
775 static INLINE
void r600_write_ctl_const_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
777 assert(reg
>= R600_CTL_CONST_OFFSET
);
778 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
779 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0);
780 cs
->buf
[cs
->cdw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
783 static INLINE
void r600_write_config_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
785 r600_write_config_reg_seq(cs
, reg
, 1);
786 r600_write_value(cs
, value
);
789 static INLINE
void r600_write_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
791 r600_write_context_reg_seq(cs
, reg
, 1);
792 r600_write_value(cs
, value
);
795 static INLINE
void r600_write_compute_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
797 r600_write_compute_context_reg_seq(cs
, reg
, 1);
798 r600_write_value(cs
, value
);
801 static INLINE
void r600_write_ctl_const(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
803 r600_write_ctl_const_seq(cs
, reg
, 1);
804 r600_write_value(cs
, value
);
810 static INLINE
uint32_t S_FIXED(float value
, uint32_t frac_bits
)
812 return value
* (1 << frac_bits
);
814 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
816 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
818 if (filter
<= 1) return 0;
819 if (filter
<= 2) return 1;
820 if (filter
<= 4) return 2;
821 if (filter
<= 8) return 3;
825 /* 12.4 fixed-point */
826 static INLINE
unsigned r600_pack_float_12p4(float x
)
829 x
>= 4096 ? 0xffff : x
* 16;
832 static INLINE
uint64_t r600_resource_va(struct pipe_screen
*screen
, struct pipe_resource
*resource
)
834 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
835 struct r600_resource
*rresource
= (struct r600_resource
*)resource
;
837 return rscreen
->ws
->buffer_get_virtual_address(rresource
->cs_buf
);