2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "../../winsys/radeon/drm/radeon_winsys.h"
31 #include "pipe/p_state.h"
32 #include "pipe/p_screen.h"
33 #include "pipe/p_context.h"
34 #include "util/u_math.h"
35 #include "util/u_slab.h"
36 #include "util/u_vbuf_mgr.h"
38 #include "r600_public.h"
39 #include "r600_shader.h"
40 #include "r600_resource.h"
42 #define R600_MAX_CONST_BUFFERS 1
43 #define R600_MAX_CONST_BUFFER_SIZE 4096
45 #ifdef PIPE_ARCH_BIG_ENDIAN
46 #define R600_BIG_ENDIAN 1
48 #define R600_BIG_ENDIAN 0
51 enum r600_pipe_state_id
{
52 R600_PIPE_STATE_BLEND
= 0,
53 R600_PIPE_STATE_BLEND_COLOR
,
54 R600_PIPE_STATE_CONFIG
,
55 R600_PIPE_STATE_SEAMLESS_CUBEMAP
,
57 R600_PIPE_STATE_SCISSOR
,
58 R600_PIPE_STATE_VIEWPORT
,
59 R600_PIPE_STATE_RASTERIZER
,
61 R600_PIPE_STATE_FRAMEBUFFER
,
63 R600_PIPE_STATE_STENCIL_REF
,
64 R600_PIPE_STATE_PS_SHADER
,
65 R600_PIPE_STATE_VS_SHADER
,
66 R600_PIPE_STATE_CONSTANT
,
67 R600_PIPE_STATE_SAMPLER
,
68 R600_PIPE_STATE_RESOURCE
,
69 R600_PIPE_STATE_POLYGON_OFFSET
,
70 R600_PIPE_STATE_FETCH_SHADER
,
75 struct pipe_screen screen
;
76 struct radeon_winsys
*ws
;
78 enum chip_class chip_class
;
79 struct radeon_info info
;
80 struct r600_tiling_info tiling_info
;
81 struct util_slab_mempool pool_buffers
;
82 unsigned num_contexts
;
84 /* for thread-safe write accessing to num_contexts */
85 pipe_mutex mutex_num_contexts
;
88 struct r600_pipe_sampler_view
{
89 struct pipe_sampler_view base
;
90 struct r600_pipe_resource_state state
;
93 struct r600_pipe_rasterizer
{
94 struct r600_pipe_state rstate
;
95 boolean clamp_vertex_color
;
96 boolean clamp_fragment_color
;
98 unsigned sprite_coord_enable
;
103 struct r600_pipe_blend
{
104 struct r600_pipe_state rstate
;
105 unsigned cb_target_mask
;
108 struct r600_pipe_dsa
{
109 struct r600_pipe_state rstate
;
113 struct r600_vertex_element
116 struct pipe_vertex_element elements
[PIPE_MAX_ATTRIBS
];
117 struct u_vbuf_elements
*vmgr_elements
;
118 struct r600_resource
*fetch_shader
;
120 struct r600_pipe_state rstate
;
121 /* if offset is to big for fetch instructio we need to alterate
122 * offset of vertex buffer, record here the offset need to add
124 unsigned vbuffer_need_offset
;
125 unsigned vbuffer_offset
[PIPE_MAX_ATTRIBS
];
128 struct r600_pipe_shader
{
129 struct r600_shader shader
;
130 struct r600_pipe_state rstate
;
131 struct r600_resource
*bo
;
132 struct r600_resource
*bo_fetch
;
133 struct r600_vertex_element vertex_elements
;
134 struct tgsi_token
*tokens
;
135 unsigned sprite_coord_enable
;
138 struct r600_pipe_sampler_state
{
139 struct r600_pipe_state rstate
;
140 boolean seamless_cube_map
;
143 /* needed for blitter save */
144 #define NUM_TEX_UNITS 16
146 struct r600_textures_info
{
147 struct r600_pipe_sampler_view
*views
[NUM_TEX_UNITS
];
148 struct r600_pipe_sampler_state
*samplers
[NUM_TEX_UNITS
];
152 bool is_array_sampler
[NUM_TEX_UNITS
];
156 struct pipe_reference reference
;
157 struct r600_pipe_context
*ctx
;
158 unsigned index
; /* in the shared bo */
159 struct list_head head
;
162 #define FENCE_BLOCK_SIZE 16
164 struct r600_fence_block
{
165 struct r600_fence fences
[FENCE_BLOCK_SIZE
];
166 struct list_head head
;
169 struct r600_pipe_fences
{
170 struct r600_resource
*bo
;
173 /* linked list of preallocated blocks */
174 struct list_head blocks
;
175 /* linked list of freed fences */
176 struct list_head pool
;
179 #define R600_CONSTANT_ARRAY_SIZE 256
180 #define R600_RESOURCE_ARRAY_SIZE 160
182 struct r600_pipe_context
{
183 struct pipe_context context
;
184 struct blitter_context
*blitter
;
185 enum radeon_family family
;
186 enum chip_class chip_class
;
187 void *custom_dsa_flush
;
188 struct r600_screen
*screen
;
189 struct radeon_winsys
*ws
;
190 struct r600_pipe_state
*states
[R600_PIPE_NSTATES
];
191 struct r600_context ctx
;
192 struct r600_vertex_element
*vertex_elements
;
193 struct r600_pipe_resource_state fs_resource
[PIPE_MAX_ATTRIBS
];
194 struct pipe_framebuffer_state framebuffer
;
195 struct pipe_index_buffer index_buffer
;
196 unsigned cb_target_mask
;
197 /* for saving when using blitter */
198 struct pipe_stencil_ref stencil_ref
;
199 struct pipe_viewport_state viewport
;
200 struct pipe_clip_state clip
;
201 struct r600_pipe_state config
;
202 struct r600_pipe_shader
*ps_shader
;
203 struct r600_pipe_shader
*vs_shader
;
204 struct r600_pipe_state vs_const_buffer
;
205 struct r600_pipe_resource_state vs_const_buffer_resource
[R600_MAX_CONST_BUFFERS
];
206 struct r600_pipe_state ps_const_buffer
;
207 struct r600_pipe_resource_state ps_const_buffer_resource
[R600_MAX_CONST_BUFFERS
];
208 struct r600_pipe_rasterizer
*rasterizer
;
209 struct r600_pipe_state vgt
;
210 struct r600_pipe_state spi
;
211 struct pipe_query
*current_render_cond
;
212 unsigned current_render_cond_mode
;
213 struct pipe_query
*saved_render_cond
;
214 unsigned saved_render_cond_mode
;
215 /* shader information */
216 boolean clamp_vertex_color
;
217 boolean clamp_fragment_color
;
218 unsigned sprite_coord_enable
;
219 boolean export_16bpc
;
221 boolean alpha_ref_dirty
;
223 struct r600_textures_info vs_samplers
;
224 struct r600_textures_info ps_samplers
;
226 struct r600_pipe_fences fences
;
228 struct u_vbuf_mgr
*vbuf_mgr
;
229 struct util_slab_mempool pool_transfers
;
230 boolean have_depth_texture
, have_depth_fb
;
232 unsigned default_ps_gprs
, default_vs_gprs
;
235 /* evergreen_state.c */
236 void evergreen_init_state_functions(struct r600_pipe_context
*rctx
);
237 void evergreen_init_config(struct r600_pipe_context
*rctx
);
238 void evergreen_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
239 void evergreen_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
240 void evergreen_fetch_shader(struct pipe_context
*ctx
, struct r600_vertex_element
*ve
);
241 void *evergreen_create_db_flush_dsa(struct r600_pipe_context
*rctx
);
242 void evergreen_polygon_offset_update(struct r600_pipe_context
*rctx
);
243 void evergreen_pipe_init_buffer_resource(struct r600_pipe_context
*rctx
,
244 struct r600_pipe_resource_state
*rstate
);
245 void evergreen_pipe_mod_buffer_resource(struct r600_pipe_resource_state
*rstate
,
246 struct r600_resource
*rbuffer
,
247 unsigned offset
, unsigned stride
,
248 enum radeon_bo_usage usage
);
249 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
250 enum pipe_format format
,
251 enum pipe_texture_target target
,
252 unsigned sample_count
,
256 void r600_init_blit_functions(struct r600_pipe_context
*rctx
);
257 void r600_blit_uncompress_depth(struct pipe_context
*ctx
, struct r600_resource_texture
*texture
);
258 void r600_blit_push_depth(struct pipe_context
*ctx
, struct r600_resource_texture
*texture
);
259 void r600_flush_depth_textures(struct r600_pipe_context
*rctx
);
262 bool r600_init_resource(struct r600_screen
*rscreen
,
263 struct r600_resource
*res
,
264 unsigned size
, unsigned alignment
,
265 unsigned bind
, unsigned usage
);
266 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
267 const struct pipe_resource
*templ
);
268 struct pipe_resource
*r600_user_buffer_create(struct pipe_screen
*screen
,
269 void *ptr
, unsigned bytes
,
271 void r600_upload_index_buffer(struct r600_pipe_context
*rctx
,
272 struct pipe_index_buffer
*ib
, unsigned count
);
276 void r600_flush(struct pipe_context
*ctx
, struct pipe_fence_handle
**fence
,
280 void r600_init_query_functions(struct r600_pipe_context
*rctx
);
282 /* r600_resource.c */
283 void r600_init_context_resource_functions(struct r600_pipe_context
*r600
);
286 int r600_pipe_shader_create(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
287 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
288 int r600_find_vs_semantic_index(struct r600_shader
*vs
,
289 struct r600_shader
*ps
, int id
);
292 void r600_update_sampler_states(struct r600_pipe_context
*rctx
);
293 void r600_init_state_functions(struct r600_pipe_context
*rctx
);
294 void r600_init_config(struct r600_pipe_context
*rctx
);
295 void r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
296 void r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
297 void r600_fetch_shader(struct pipe_context
*ctx
, struct r600_vertex_element
*ve
);
298 void *r600_create_db_flush_dsa(struct r600_pipe_context
*rctx
);
299 void r600_polygon_offset_update(struct r600_pipe_context
*rctx
);
300 void r600_pipe_init_buffer_resource(struct r600_pipe_context
*rctx
,
301 struct r600_pipe_resource_state
*rstate
);
302 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state
*rstate
,
303 struct r600_resource
*rbuffer
,
304 unsigned offset
, unsigned stride
,
305 enum radeon_bo_usage usage
);
306 void r600_adjust_gprs(struct r600_pipe_context
*rctx
);
307 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
308 enum pipe_format format
,
309 enum pipe_texture_target target
,
310 unsigned sample_count
,
314 void r600_init_screen_texture_functions(struct pipe_screen
*screen
);
315 void r600_init_surface_functions(struct r600_pipe_context
*r600
);
316 uint32_t r600_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
317 const unsigned char *swizzle_view
,
318 uint32_t *word4_p
, uint32_t *yuv_format_p
);
319 unsigned r600_texture_get_offset(struct r600_resource_texture
*rtex
,
320 unsigned level
, unsigned layer
);
322 /* r600_translate.c */
323 void r600_translate_index_buffer(struct r600_pipe_context
*r600
,
324 struct pipe_index_buffer
*ib
,
327 /* r600_state_common.c */
328 void r600_set_index_buffer(struct pipe_context
*ctx
,
329 const struct pipe_index_buffer
*ib
);
330 void r600_set_vertex_buffers(struct pipe_context
*ctx
, unsigned count
,
331 const struct pipe_vertex_buffer
*buffers
);
332 void *r600_create_vertex_elements(struct pipe_context
*ctx
,
334 const struct pipe_vertex_element
*elements
);
335 void r600_delete_vertex_element(struct pipe_context
*ctx
, void *state
);
336 void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
);
337 void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
);
338 void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
);
339 void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
);
340 void r600_sampler_view_destroy(struct pipe_context
*ctx
,
341 struct pipe_sampler_view
*state
);
342 void r600_delete_state(struct pipe_context
*ctx
, void *state
);
343 void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
);
344 void *r600_create_shader_state(struct pipe_context
*ctx
,
345 const struct pipe_shader_state
*state
);
346 void r600_bind_ps_shader(struct pipe_context
*ctx
, void *state
);
347 void r600_bind_vs_shader(struct pipe_context
*ctx
, void *state
);
348 void r600_delete_ps_shader(struct pipe_context
*ctx
, void *state
);
349 void r600_delete_vs_shader(struct pipe_context
*ctx
, void *state
);
350 void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
351 struct pipe_resource
*buffer
);
352 void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*info
);
357 static INLINE u32
S_FIXED(float value
, u32 frac_bits
)
359 return value
* (1 << frac_bits
);
361 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
363 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
365 if (filter
<= 1) return 0;
366 if (filter
<= 2) return 1;
367 if (filter
<= 4) return 2;
368 if (filter
<= 8) return 3;