2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "radeon/r600_pipe_common.h"
30 #include "radeon/r600_cs.h"
32 #include "r600_llvm.h"
33 #include "r600_public.h"
35 #include "util/u_suballoc.h"
36 #include "util/list.h"
37 #include "util/u_transfer.h"
39 #define R600_NUM_ATOMS 75
41 #define R600_MAX_VIEWPORTS 16
44 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
45 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
46 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
47 /* read-write caches */
48 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
49 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
50 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
51 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
52 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
53 /* engine synchronization */
54 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
55 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
56 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
58 /* the number of CS dwords for flushing and drawing */
59 #define R600_MAX_FLUSH_CS_DWORDS 16
60 #define R600_MAX_DRAW_CS_DWORDS 47
61 #define R600_TRACE_CS_DWORDS 7
63 #define R600_MAX_USER_CONST_BUFFERS 13
64 #define R600_MAX_DRIVER_CONST_BUFFERS 3
65 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
67 /* start driver buffers after user buffers */
68 #define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
69 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
70 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
71 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
72 * of 16 const buffers.
73 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
75 * In order to support d3d 11 mandated minimum of 15 user const buffers
76 * we'd have to squash all use cases into one driver buffer.
78 #define R600_SAMPLE_POSITIONS_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
80 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
82 #ifdef PIPE_ARCH_BIG_ENDIAN
83 #define R600_BIG_ENDIAN 1
85 #define R600_BIG_ENDIAN 0
88 #define R600_DIRTY_ATOM_WORD_BITS (sizeof(unsigned long) * 8)
89 #define R600_DIRTY_ATOM_ARRAY_LEN DIV_ROUND_UP(R600_NUM_ATOMS, R600_DIRTY_ATOM_WORD_BITS)
93 struct r600_shader_key
;
95 /* This is an atom containing GPU commands that never change.
96 * This is supposed to be copied directly into the CS. */
97 struct r600_command_buffer
{
104 struct r600_db_state
{
105 struct r600_atom atom
;
106 struct r600_surface
*rsurf
;
109 struct r600_db_misc_state
{
110 struct r600_atom atom
;
111 bool occlusion_query_enabled
;
112 bool flush_depthstencil_through_cb
;
113 bool flush_depthstencil_in_place
;
114 bool copy_depth
, copy_stencil
;
115 unsigned copy_sample
;
116 unsigned log_samples
;
117 unsigned db_shader_control
;
121 struct r600_cb_misc_state
{
122 struct r600_atom atom
;
123 unsigned cb_color_control
; /* this comes from blend state */
124 unsigned blend_colormask
; /* 8*4 bits for 8 RGBA colorbuffers */
126 unsigned nr_ps_color_outputs
;
131 struct r600_clip_misc_state
{
132 struct r600_atom atom
;
133 unsigned pa_cl_clip_cntl
; /* from rasterizer */
134 unsigned pa_cl_vs_out_cntl
; /* from vertex shader */
135 unsigned clip_plane_enable
; /* from rasterizer */
136 unsigned clip_dist_write
; /* from vertex shader */
137 boolean clip_disable
; /* from vertex shader */
140 struct r600_alphatest_state
{
141 struct r600_atom atom
;
142 unsigned sx_alpha_test_control
; /* this comes from dsa state */
143 unsigned sx_alpha_ref
; /* this comes from dsa state */
145 bool cb0_export_16bpc
; /* from set_framebuffer_state */
148 struct r600_vgt_state
{
149 struct r600_atom atom
;
150 uint32_t vgt_multi_prim_ib_reset_en
;
151 uint32_t vgt_multi_prim_ib_reset_indx
;
152 uint32_t vgt_indx_offset
;
153 bool last_draw_was_indirect
;
156 struct r600_blend_color
{
157 struct r600_atom atom
;
158 struct pipe_blend_color state
;
161 struct r600_clip_state
{
162 struct r600_atom atom
;
163 struct pipe_clip_state state
;
166 struct r600_cs_shader_state
{
167 struct r600_atom atom
;
168 unsigned kernel_index
;
170 struct r600_pipe_compute
*shader
;
173 struct r600_framebuffer
{
174 struct r600_atom atom
;
175 struct pipe_framebuffer_state state
;
176 unsigned compressed_cb_mask
;
180 bool is_msaa_resolve
;
183 struct r600_sample_mask
{
184 struct r600_atom atom
;
185 uint16_t sample_mask
; /* there are only 8 bits on EG, 16 bits on Cayman */
188 struct r600_config_state
{
189 struct r600_atom atom
;
190 unsigned sq_gpr_resource_mgmt_1
;
191 unsigned sq_gpr_resource_mgmt_2
;
194 struct r600_stencil_ref
201 struct r600_stencil_ref_state
{
202 struct r600_atom atom
;
203 struct r600_stencil_ref state
;
204 struct pipe_stencil_ref pipe_state
;
207 struct r600_viewport_state
{
208 struct r600_atom atom
;
209 struct pipe_viewport_state state
;
213 struct r600_shader_stages_state
{
214 struct r600_atom atom
;
215 unsigned geom_enable
;
218 struct r600_gs_rings_state
{
219 struct r600_atom atom
;
221 struct pipe_constant_buffer esgs_ring
;
222 struct pipe_constant_buffer gsvs_ring
;
225 /* This must start from 16. */
227 #define DBG_LLVM (1 << 29)
228 #define DBG_NO_CP_DMA (1 << 30)
230 #define DBG_NO_SB (1 << 21)
231 #define DBG_SB_CS (1 << 22)
232 #define DBG_SB_DRY_RUN (1 << 23)
233 #define DBG_SB_STAT (1 << 24)
234 #define DBG_SB_DUMP (1 << 25)
235 #define DBG_SB_NO_FALLBACK (1 << 26)
236 #define DBG_SB_DISASM (1 << 27)
237 #define DBG_SB_SAFEMATH (1 << 28)
240 struct r600_common_screen b
;
242 bool has_compressed_msaa_texturing
;
244 /*for compute global memory binding, we allocate stuff here, instead of
246 * XXX: Not sure if this is the best place for global_pool. Also,
247 * it's not thread safe, so it won't work with multiple contexts. */
248 struct compute_memory_pool
*global_pool
;
251 struct r600_pipe_sampler_view
{
252 struct pipe_sampler_view base
;
253 struct list_head list
;
254 struct r600_resource
*tex_resource
;
255 uint32_t tex_resource_words
[8];
256 bool skip_mip_address_reloc
;
259 struct r600_rasterizer_state
{
260 struct r600_command_buffer buffer
;
263 unsigned sprite_coord_enable
;
264 unsigned clip_plane_enable
;
265 unsigned pa_sc_line_stipple
;
266 unsigned pa_cl_clip_cntl
;
267 unsigned pa_su_sc_mode_cntl
;
272 bool multisample_enable
;
275 struct r600_poly_offset_state
{
276 struct r600_atom atom
;
277 enum pipe_format zs_format
;
282 struct r600_blend_state
{
283 struct r600_command_buffer buffer
;
284 struct r600_command_buffer buffer_no_blend
;
285 unsigned cb_target_mask
;
286 unsigned cb_color_control
;
287 unsigned cb_color_control_no_blend
;
292 struct r600_dsa_state
{
293 struct r600_command_buffer buffer
;
298 unsigned sx_alpha_test_control
;
301 struct r600_pipe_shader
;
303 struct r600_pipe_shader_selector
{
304 struct r600_pipe_shader
*current
;
306 struct tgsi_token
*tokens
;
307 struct pipe_stream_output_info so
;
309 unsigned num_shaders
;
311 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
314 unsigned nr_ps_max_color_exports
;
317 struct r600_pipe_sampler_state
{
318 uint32_t tex_sampler_words
[3];
319 union pipe_color_union border_color
;
320 bool border_color_use
;
321 bool seamless_cube_map
;
324 /* needed for blitter save */
325 #define NUM_TEX_UNITS 16
327 struct r600_seamless_cube_map
{
328 struct r600_atom atom
;
332 struct r600_samplerview_state
{
333 struct r600_atom atom
;
334 struct r600_pipe_sampler_view
*views
[NUM_TEX_UNITS
];
335 uint32_t enabled_mask
;
337 uint32_t compressed_depthtex_mask
; /* which textures are depth */
338 uint32_t compressed_colortex_mask
;
339 boolean dirty_buffer_constants
;
342 struct r600_sampler_states
{
343 struct r600_atom atom
;
344 struct r600_pipe_sampler_state
*states
[NUM_TEX_UNITS
];
345 uint32_t enabled_mask
;
347 uint32_t has_bordercolor_mask
; /* which states contain the border color */
350 struct r600_textures_info
{
351 struct r600_samplerview_state views
;
352 struct r600_sampler_states states
;
353 bool is_array_sampler
[NUM_TEX_UNITS
];
355 /* cube array txq workaround */
356 uint32_t *txq_constants
;
357 /* buffer related workarounds */
358 uint32_t *buffer_constants
;
361 struct r600_constbuf_state
363 struct r600_atom atom
;
364 struct pipe_constant_buffer cb
[PIPE_MAX_CONSTANT_BUFFERS
];
365 uint32_t enabled_mask
;
369 struct r600_vertexbuf_state
371 struct r600_atom atom
;
372 struct pipe_vertex_buffer vb
[PIPE_MAX_ATTRIBS
];
373 uint32_t enabled_mask
; /* non-NULL buffers */
377 /* CSO (constant state object, in other words, immutable state). */
378 struct r600_cso_state
380 struct r600_atom atom
;
381 void *cso
; /* e.g. r600_blend_state */
382 struct r600_command_buffer
*cb
;
385 struct r600_scissor_state
387 struct r600_atom atom
;
388 struct pipe_scissor_state scissor
;
389 bool enable
; /* r6xx only */
393 struct r600_fetch_shader
{
394 struct r600_resource
*buffer
;
398 struct r600_shader_state
{
399 struct r600_atom atom
;
400 struct r600_pipe_shader
*shader
;
403 struct r600_context
{
404 struct r600_common_context b
;
405 struct r600_screen
*screen
;
406 struct blitter_context
*blitter
;
407 struct u_suballocator
*allocator_fetch_shader
;
410 boolean has_vertex_cache
;
411 boolean keep_tiling_flags
;
412 unsigned default_ps_gprs
, default_vs_gprs
;
413 unsigned r6xx_num_clause_temp_gprs
;
415 /* Miscellaneous state objects. */
416 void *custom_dsa_flush
;
417 void *custom_blend_resolve
;
418 void *custom_blend_decompress
;
419 void *custom_blend_fastclear
;
420 /* With rasterizer discard, there doesn't have to be a pixel shader.
421 * In that case, we bind this one: */
422 void *dummy_pixel_shader
;
423 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
424 * bug where valid CMASK and FMASK are required to be present to avoid
425 * a hardlock in certain operations but aren't actually used
426 * for anything useful. */
427 struct r600_resource
*dummy_fmask
;
428 struct r600_resource
*dummy_cmask
;
430 /* State binding slots are here. */
431 struct r600_atom
*atoms
[R600_NUM_ATOMS
];
432 /* Dirty atom bitmask for fast tests */
433 unsigned long dirty_atoms
[R600_DIRTY_ATOM_ARRAY_LEN
];
434 /* States for CS initialization. */
435 struct r600_command_buffer start_cs_cmd
; /* invariant state mostly */
436 /** Compute specific registers initializations. The start_cs_cmd atom
437 * must be emitted before start_compute_cs_cmd. */
438 struct r600_command_buffer start_compute_cs_cmd
;
439 /* Register states. */
440 struct r600_alphatest_state alphatest_state
;
441 struct r600_cso_state blend_state
;
442 struct r600_blend_color blend_color
;
443 struct r600_cb_misc_state cb_misc_state
;
444 struct r600_clip_misc_state clip_misc_state
;
445 struct r600_clip_state clip_state
;
446 struct r600_db_misc_state db_misc_state
;
447 struct r600_db_state db_state
;
448 struct r600_cso_state dsa_state
;
449 struct r600_framebuffer framebuffer
;
450 struct r600_poly_offset_state poly_offset_state
;
451 struct r600_cso_state rasterizer_state
;
452 struct r600_sample_mask sample_mask
;
453 struct r600_scissor_state scissor
[R600_MAX_VIEWPORTS
];
454 struct r600_seamless_cube_map seamless_cube_map
;
455 struct r600_config_state config_state
;
456 struct r600_stencil_ref_state stencil_ref
;
457 struct r600_vgt_state vgt_state
;
458 struct r600_viewport_state viewport
[R600_MAX_VIEWPORTS
];
459 /* Shaders and shader resources. */
460 struct r600_cso_state vertex_fetch_shader
;
461 struct r600_shader_state vertex_shader
;
462 struct r600_shader_state pixel_shader
;
463 struct r600_shader_state geometry_shader
;
464 struct r600_shader_state export_shader
;
465 struct r600_cs_shader_state cs_shader_state
;
466 struct r600_shader_stages_state shader_stages
;
467 struct r600_gs_rings_state gs_rings
;
468 struct r600_constbuf_state constbuf_state
[PIPE_SHADER_TYPES
];
469 struct r600_textures_info samplers
[PIPE_SHADER_TYPES
];
470 /** Vertex buffers for fetch shaders */
471 struct r600_vertexbuf_state vertex_buffer_state
;
472 /** Vertex buffers for compute shaders */
473 struct r600_vertexbuf_state cs_vertex_buffer_state
;
475 /* Additional context states. */
476 unsigned compute_cb_target_mask
;
477 struct r600_pipe_shader_selector
*ps_shader
;
478 struct r600_pipe_shader_selector
*vs_shader
;
479 struct r600_pipe_shader_selector
*gs_shader
;
480 struct r600_rasterizer_state
*rasterizer
;
482 bool force_blend_disable
;
483 boolean dual_src_blend
;
488 struct pipe_index_buffer index_buffer
;
490 /* Last draw state (-1 = unset). */
491 int last_primitive_type
; /* Last primitive type used in draw_vbo. */
492 int last_start_instance
;
495 struct r600_isa
*isa
;
498 static inline void r600_emit_command_buffer(struct radeon_winsys_cs
*cs
,
499 struct r600_command_buffer
*cb
)
501 assert(cs
->cdw
+ cb
->num_dw
<= cs
->max_dw
);
502 memcpy(cs
->buf
+ cs
->cdw
, cb
->buf
, 4 * cb
->num_dw
);
503 cs
->cdw
+= cb
->num_dw
;
506 static inline void r600_set_atom_dirty(struct r600_context
*rctx
,
507 struct r600_atom
*atom
,
515 assert(atom
->id
!= 0);
516 w
= atom
->id
/ R600_DIRTY_ATOM_WORD_BITS
;
517 mask
= 1ul << (atom
->id
% R600_DIRTY_ATOM_WORD_BITS
);
519 rctx
->dirty_atoms
[w
] |= mask
;
521 rctx
->dirty_atoms
[w
] &= ~mask
;
524 static inline void r600_mark_atom_dirty(struct r600_context
*rctx
,
525 struct r600_atom
*atom
)
527 r600_set_atom_dirty(rctx
, atom
, true);
530 static inline unsigned int r600_next_dirty_atom(struct r600_context
*rctx
,
533 #if !defined(DEBUG) && defined(HAVE___BUILTIN_CTZ)
534 unsigned int w
= id
/ R600_DIRTY_ATOM_WORD_BITS
;
535 unsigned int bit
= id
% R600_DIRTY_ATOM_WORD_BITS
;
536 unsigned long bits
, mask
= (1ul << bit
) - 1;
538 for (; w
< R600_DIRTY_ATOM_ARRAY_LEN
; w
++, mask
= 0ul) {
539 bits
= rctx
->dirty_atoms
[w
] & ~mask
;
542 return w
* R600_DIRTY_ATOM_WORD_BITS
+ __builtin_ctzl(bits
);
545 return R600_NUM_ATOMS
;
547 for (; id
< R600_NUM_ATOMS
; id
++) {
548 bool dirty
= !!(rctx
->dirty_atoms
[id
/ R600_DIRTY_ATOM_WORD_BITS
] &
549 (1ul << (id
% R600_DIRTY_ATOM_WORD_BITS
)));
550 assert(dirty
== (rctx
->atoms
[id
] && rctx
->atoms
[id
]->dirty
));
559 void r600_trace_emit(struct r600_context
*rctx
);
561 static inline void r600_emit_atom(struct r600_context
*rctx
, struct r600_atom
*atom
)
563 atom
->emit(&rctx
->b
, atom
);
564 r600_set_atom_dirty(rctx
, atom
, false);
565 if (rctx
->screen
->b
.trace_bo
) {
566 r600_trace_emit(rctx
);
570 static inline void r600_set_cso_state(struct r600_context
*rctx
,
571 struct r600_cso_state
*state
, void *cso
)
574 r600_set_atom_dirty(rctx
, &state
->atom
, cso
!= NULL
);
577 static inline void r600_set_cso_state_with_cb(struct r600_context
*rctx
,
578 struct r600_cso_state
*state
, void *cso
,
579 struct r600_command_buffer
*cb
)
582 state
->atom
.num_dw
= cb
? cb
->num_dw
: 0;
583 r600_set_cso_state(rctx
, state
, cso
);
586 /* compute_memory_pool.c */
587 struct compute_memory_pool
;
588 void compute_memory_pool_delete(struct compute_memory_pool
* pool
);
589 struct compute_memory_pool
* compute_memory_pool_new(
590 struct r600_screen
*rscreen
);
592 /* evergreen_state.c */
593 struct pipe_sampler_view
*
594 evergreen_create_sampler_view_custom(struct pipe_context
*ctx
,
595 struct pipe_resource
*texture
,
596 const struct pipe_sampler_view
*state
,
597 unsigned width0
, unsigned height0
,
598 unsigned force_level
);
599 void evergreen_init_common_regs(struct r600_command_buffer
*cb
,
600 enum chip_class ctx_chip_class
,
601 enum radeon_family ctx_family
,
603 void cayman_init_common_regs(struct r600_command_buffer
*cb
,
604 enum chip_class ctx_chip_class
,
605 enum radeon_family ctx_family
,
608 void evergreen_init_state_functions(struct r600_context
*rctx
);
609 void evergreen_init_atom_start_cs(struct r600_context
*rctx
);
610 void evergreen_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
611 void evergreen_update_es_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
612 void evergreen_update_gs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
613 void evergreen_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
614 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
);
615 void *evergreen_create_resolve_blend(struct r600_context
*rctx
);
616 void *evergreen_create_decompress_blend(struct r600_context
*rctx
);
617 void *evergreen_create_fastclear_blend(struct r600_context
*rctx
);
618 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
619 enum pipe_format format
,
620 enum pipe_texture_target target
,
621 unsigned sample_count
,
623 void evergreen_init_color_surface(struct r600_context
*rctx
,
624 struct r600_surface
*surf
);
625 void evergreen_init_color_surface_rat(struct r600_context
*rctx
,
626 struct r600_surface
*surf
);
627 void evergreen_update_db_shader_control(struct r600_context
* rctx
);
630 void r600_init_blit_functions(struct r600_context
*rctx
);
631 void r600_decompress_depth_textures(struct r600_context
*rctx
,
632 struct r600_samplerview_state
*textures
);
633 void r600_decompress_color_textures(struct r600_context
*rctx
,
634 struct r600_samplerview_state
*textures
);
635 void r600_resource_copy_region(struct pipe_context
*ctx
,
636 struct pipe_resource
*dst
,
638 unsigned dstx
, unsigned dsty
, unsigned dstz
,
639 struct pipe_resource
*src
,
641 const struct pipe_box
*src_box
);
644 int r600_pipe_shader_create(struct pipe_context
*ctx
,
645 struct r600_pipe_shader
*shader
,
646 struct r600_shader_key key
);
648 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
651 struct pipe_sampler_view
*
652 r600_create_sampler_view_custom(struct pipe_context
*ctx
,
653 struct pipe_resource
*texture
,
654 const struct pipe_sampler_view
*state
,
655 unsigned width_first_level
, unsigned height_first_level
);
656 void r600_init_state_functions(struct r600_context
*rctx
);
657 void r600_init_atom_start_cs(struct r600_context
*rctx
);
658 void r600_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
659 void r600_update_es_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
660 void r600_update_gs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
661 void r600_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
662 void *r600_create_db_flush_dsa(struct r600_context
*rctx
);
663 void *r600_create_resolve_blend(struct r600_context
*rctx
);
664 void *r700_create_resolve_blend(struct r600_context
*rctx
);
665 void *r600_create_decompress_blend(struct r600_context
*rctx
);
666 bool r600_adjust_gprs(struct r600_context
*rctx
);
667 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
668 enum pipe_format format
,
669 enum pipe_texture_target target
,
670 unsigned sample_count
,
672 void r600_update_db_shader_control(struct r600_context
* rctx
);
674 /* r600_hw_context.c */
675 void r600_context_gfx_flush(void *context
, unsigned flags
,
676 struct pipe_fence_handle
**fence
);
677 void r600_begin_new_cs(struct r600_context
*ctx
);
678 void r600_flush_emit(struct r600_context
*ctx
);
679 void r600_need_cs_space(struct r600_context
*ctx
, unsigned num_dw
, boolean count_draw_in
);
680 void r600_cp_dma_copy_buffer(struct r600_context
*rctx
,
681 struct pipe_resource
*dst
, uint64_t dst_offset
,
682 struct pipe_resource
*src
, uint64_t src_offset
,
684 void evergreen_cp_dma_clear_buffer(struct r600_context
*rctx
,
685 struct pipe_resource
*dst
, uint64_t offset
,
686 unsigned size
, uint32_t clear_value
);
687 void r600_dma_copy_buffer(struct r600_context
*rctx
,
688 struct pipe_resource
*dst
,
689 struct pipe_resource
*src
,
695 * evergreen_hw_context.c
697 void evergreen_dma_copy_buffer(struct r600_context
*rctx
,
698 struct pipe_resource
*dst
,
699 struct pipe_resource
*src
,
704 /* r600_state_common.c */
705 void r600_init_common_state_functions(struct r600_context
*rctx
);
706 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
707 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
708 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
);
709 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
710 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
711 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
);
712 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
713 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
);
714 void r600_add_atom(struct r600_context
*rctx
, struct r600_atom
*atom
, unsigned id
);
715 void r600_init_atom(struct r600_context
*rctx
, struct r600_atom
*atom
, unsigned id
,
716 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
718 void r600_vertex_buffers_dirty(struct r600_context
*rctx
);
719 void r600_sampler_views_dirty(struct r600_context
*rctx
,
720 struct r600_samplerview_state
*state
);
721 void r600_sampler_states_dirty(struct r600_context
*rctx
,
722 struct r600_sampler_states
*state
);
723 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
);
724 void r600_set_sample_locations_constant_buffer(struct r600_context
*rctx
);
725 uint32_t r600_translate_stencil_op(int s_op
);
726 uint32_t r600_translate_fill(uint32_t func
);
727 unsigned r600_tex_wrap(unsigned wrap
);
728 unsigned r600_tex_filter(unsigned filter
);
729 unsigned r600_tex_mipfilter(unsigned filter
);
730 unsigned r600_tex_compare(unsigned compare
);
731 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
);
732 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
733 struct pipe_resource
*texture
,
734 const struct pipe_surface
*templ
,
735 unsigned width
, unsigned height
);
736 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
737 const unsigned char *swizzle_view
,
739 uint32_t r600_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
740 const unsigned char *swizzle_view
,
741 uint32_t *word4_p
, uint32_t *yuv_format_p
);
742 uint32_t r600_translate_colorformat(enum chip_class chip
, enum pipe_format format
);
743 uint32_t r600_colorformat_endian_swap(uint32_t colorformat
);
746 struct pipe_video_codec
*r600_uvd_create_decoder(struct pipe_context
*context
,
747 const struct pipe_video_codec
*decoder
);
749 struct pipe_video_buffer
*r600_video_buffer_create(struct pipe_context
*pipe
,
750 const struct pipe_video_buffer
*tmpl
);
753 * Helpers for building command buffers
756 #define PKT3_SET_CONFIG_REG 0x68
757 #define PKT3_SET_CONTEXT_REG 0x69
758 #define PKT3_SET_CTL_CONST 0x6F
759 #define PKT3_SET_LOOP_CONST 0x6C
761 #define R600_CONFIG_REG_OFFSET 0x08000
762 #define R600_CONTEXT_REG_OFFSET 0x28000
763 #define R600_CTL_CONST_OFFSET 0x3CFF0
764 #define R600_LOOP_CONST_OFFSET 0X0003E200
765 #define EG_LOOP_CONST_OFFSET 0x0003A200
767 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
768 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
769 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
770 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
771 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
773 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
775 /*Evergreen Compute packet3*/
776 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
778 static inline void r600_store_value(struct r600_command_buffer
*cb
, unsigned value
)
780 cb
->buf
[cb
->num_dw
++] = value
;
783 static inline void r600_store_array(struct r600_command_buffer
*cb
, unsigned num
, unsigned *ptr
)
785 assert(cb
->num_dw
+num
<= cb
->max_num_dw
);
786 memcpy(&cb
->buf
[cb
->num_dw
], ptr
, num
* sizeof(ptr
[0]));
790 static inline void r600_store_config_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
792 assert(reg
< R600_CONTEXT_REG_OFFSET
);
793 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
794 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
795 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
799 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
802 static inline void r600_store_context_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
804 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
805 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
806 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0) | cb
->pkt_flags
;
807 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
811 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
814 static inline void r600_store_ctl_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
816 assert(reg
>= R600_CTL_CONST_OFFSET
);
817 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
818 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0) | cb
->pkt_flags
;
819 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
822 static inline void r600_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
824 assert(reg
>= R600_LOOP_CONST_OFFSET
);
825 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
826 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0);
827 cb
->buf
[cb
->num_dw
++] = (reg
- R600_LOOP_CONST_OFFSET
) >> 2;
831 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
834 static inline void eg_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
836 assert(reg
>= EG_LOOP_CONST_OFFSET
);
837 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
838 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0) | cb
->pkt_flags
;
839 cb
->buf
[cb
->num_dw
++] = (reg
- EG_LOOP_CONST_OFFSET
) >> 2;
842 static inline void r600_store_config_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
844 r600_store_config_reg_seq(cb
, reg
, 1);
845 r600_store_value(cb
, value
);
848 static inline void r600_store_context_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
850 r600_store_context_reg_seq(cb
, reg
, 1);
851 r600_store_value(cb
, value
);
854 static inline void r600_store_ctl_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
856 r600_store_ctl_const_seq(cb
, reg
, 1);
857 r600_store_value(cb
, value
);
860 static inline void r600_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
862 r600_store_loop_const_seq(cb
, reg
, 1);
863 r600_store_value(cb
, value
);
866 static inline void eg_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
868 eg_store_loop_const_seq(cb
, reg
, 1);
869 r600_store_value(cb
, value
);
872 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
);
873 void r600_release_command_buffer(struct r600_command_buffer
*cb
);
875 static inline void r600_write_compute_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
877 r600_write_context_reg_seq(cs
, reg
, num
);
878 /* Set the compute bit on the packet header */
879 cs
->buf
[cs
->cdw
- 2] |= RADEON_CP_PACKET3_COMPUTE_MODE
;
882 static inline void r600_write_ctl_const_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
884 assert(reg
>= R600_CTL_CONST_OFFSET
);
885 assert(cs
->cdw
+2+num
<= cs
->max_dw
);
886 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0);
887 cs
->buf
[cs
->cdw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
890 static inline void r600_write_compute_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
892 r600_write_compute_context_reg_seq(cs
, reg
, 1);
893 radeon_emit(cs
, value
);
896 static inline void r600_write_context_reg_flag(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
, unsigned flag
)
898 if (flag
& RADEON_CP_PACKET3_COMPUTE_MODE
) {
899 r600_write_compute_context_reg(cs
, reg
, value
);
901 r600_write_context_reg(cs
, reg
, value
);
905 static inline void r600_write_ctl_const(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
907 r600_write_ctl_const_seq(cs
, reg
, 1);
908 radeon_emit(cs
, value
);
914 static inline uint32_t S_FIXED(float value
, uint32_t frac_bits
)
916 return value
* (1 << frac_bits
);
918 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
920 /* 12.4 fixed-point */
921 static inline unsigned r600_pack_float_12p4(float x
)
924 x
>= 4096 ? 0xffff : x
* 16;
927 /* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */
928 static inline bool r600_can_read_depth(struct r600_texture
*rtex
)
930 return rtex
->resource
.b
.b
.nr_samples
<= 1 &&
931 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
932 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
);
935 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
936 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
937 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
939 static inline unsigned r600_conv_prim_to_gs_out(unsigned mode
)
941 static const int prim_conv
[] = {
942 V_028A6C_OUTPRIM_TYPE_POINTLIST
,
943 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
944 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
945 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
946 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
947 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
948 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
949 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
950 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
951 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
952 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
953 V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
954 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
955 V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
956 V_028A6C_OUTPRIM_TYPE_TRISTRIP
958 assert(mode
< Elements(prim_conv
));
960 return prim_conv
[mode
];