broadcom/vc5: Increase simulator memory for tex-miplevel-selection.
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "r600_pipe_common.h"
30 #include "r600_cs.h"
31 #include "r600_public.h"
32 #include "pipe/p_defines.h"
33
34 #include "util/u_suballoc.h"
35 #include "util/list.h"
36 #include "util/u_transfer.h"
37 #include "util/u_memory.h"
38
39 #include "tgsi/tgsi_scan.h"
40
41 #define R600_NUM_ATOMS 53
42
43 #define R600_MAX_IMAGES 8
44 /*
45 * ranges reserved for images on evergreen
46 * first set for the immediate buffers,
47 * second for the actual resources for RESQ.
48 */
49 #define R600_IMAGE_IMMED_RESOURCE_OFFSET 160
50 #define R600_IMAGE_REAL_RESOURCE_OFFSET 168
51
52 /* read caches */
53 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
54 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
55 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
56 /* read-write caches */
57 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
58 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
59 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
60 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
61 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
62 /* engine synchronization */
63 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
64 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
65 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
66
67 /* the number of CS dwords for flushing and drawing */
68 #define R600_MAX_FLUSH_CS_DWORDS 18
69 #define R600_MAX_DRAW_CS_DWORDS 58
70 #define R600_MAX_PFP_SYNC_ME_DWORDS 16
71
72 #define R600_MAX_USER_CONST_BUFFERS 13
73 #define R600_MAX_DRIVER_CONST_BUFFERS 3
74 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
75
76 #define EG_MAX_ATOMIC_BUFFERS 8
77
78 /* start driver buffers after user buffers */
79 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
80 #define R600_UCP_SIZE (4*4*8)
81 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
82
83 #define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
84 /*
85 * Note GS doesn't use a constant buffer binding, just a resource index,
86 * so it's fine to have it exist at index 16.
87 */
88 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
89 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
90 * of 16 const buffers.
91 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
92 *
93 * In order to support d3d 11 mandated minimum of 15 user const buffers
94 * we'd have to squash all use cases into one driver buffer.
95 */
96 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
97
98 /* HW stages */
99 #define R600_HW_STAGE_PS 0
100 #define R600_HW_STAGE_VS 1
101 #define R600_HW_STAGE_GS 2
102 #define R600_HW_STAGE_ES 3
103 #define EG_HW_STAGE_LS 4
104 #define EG_HW_STAGE_HS 5
105
106 #define R600_NUM_HW_STAGES 4
107 #define EG_NUM_HW_STAGES 6
108
109 struct r600_context;
110 struct r600_bytecode;
111 union r600_shader_key;
112
113 /* This is an atom containing GPU commands that never change.
114 * This is supposed to be copied directly into the CS. */
115 struct r600_command_buffer {
116 uint32_t *buf;
117 unsigned num_dw;
118 unsigned max_num_dw;
119 unsigned pkt_flags;
120 };
121
122 struct r600_db_state {
123 struct r600_atom atom;
124 struct r600_surface *rsurf;
125 };
126
127 struct r600_db_misc_state {
128 struct r600_atom atom;
129 bool occlusion_queries_disabled;
130 bool flush_depthstencil_through_cb;
131 bool flush_depth_inplace;
132 bool flush_stencil_inplace;
133 bool copy_depth, copy_stencil;
134 unsigned copy_sample;
135 unsigned log_samples;
136 unsigned db_shader_control;
137 bool htile_clear;
138 uint8_t ps_conservative_z;
139 };
140
141 struct r600_cb_misc_state {
142 struct r600_atom atom;
143 unsigned cb_color_control; /* this comes from blend state */
144 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
145 unsigned nr_cbufs;
146 unsigned nr_ps_color_outputs;
147 unsigned nr_image_rats;
148 bool multiwrite;
149 bool dual_src_blend;
150 };
151
152 struct r600_clip_misc_state {
153 struct r600_atom atom;
154 unsigned pa_cl_clip_cntl; /* from rasterizer */
155 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
156 unsigned clip_plane_enable; /* from rasterizer */
157 unsigned clip_dist_write; /* from vertex shader */
158 boolean clip_disable; /* from vertex shader */
159 boolean vs_out_viewport; /* from vertex shader */
160 };
161
162 struct r600_alphatest_state {
163 struct r600_atom atom;
164 unsigned sx_alpha_test_control; /* this comes from dsa state */
165 unsigned sx_alpha_ref; /* this comes from dsa state */
166 bool bypass;
167 bool cb0_export_16bpc; /* from set_framebuffer_state */
168 };
169
170 struct r600_vgt_state {
171 struct r600_atom atom;
172 uint32_t vgt_multi_prim_ib_reset_en;
173 uint32_t vgt_multi_prim_ib_reset_indx;
174 uint32_t vgt_indx_offset;
175 bool last_draw_was_indirect;
176 };
177
178 struct r600_blend_color {
179 struct r600_atom atom;
180 struct pipe_blend_color state;
181 };
182
183 struct r600_clip_state {
184 struct r600_atom atom;
185 struct pipe_clip_state state;
186 };
187
188 struct r600_cs_shader_state {
189 struct r600_atom atom;
190 unsigned kernel_index;
191 unsigned pc;
192 struct r600_pipe_compute *shader;
193 };
194
195 struct r600_framebuffer {
196 struct r600_atom atom;
197 struct pipe_framebuffer_state state;
198 unsigned compressed_cb_mask;
199 unsigned nr_samples;
200 bool export_16bpc;
201 bool cb0_is_integer;
202 bool is_msaa_resolve;
203 bool dual_src_blend;
204 bool do_update_surf_dirtiness;
205 };
206
207 struct r600_sample_mask {
208 struct r600_atom atom;
209 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
210 };
211
212 struct r600_config_state {
213 struct r600_atom atom;
214 unsigned sq_gpr_resource_mgmt_1;
215 unsigned sq_gpr_resource_mgmt_2;
216 unsigned sq_gpr_resource_mgmt_3;
217 bool dyn_gpr_enabled;
218 };
219
220 struct r600_stencil_ref
221 {
222 ubyte ref_value[2];
223 ubyte valuemask[2];
224 ubyte writemask[2];
225 };
226
227 struct r600_stencil_ref_state {
228 struct r600_atom atom;
229 struct r600_stencil_ref state;
230 struct pipe_stencil_ref pipe_state;
231 };
232
233 struct r600_shader_stages_state {
234 struct r600_atom atom;
235 unsigned geom_enable;
236 };
237
238 struct r600_gs_rings_state {
239 struct r600_atom atom;
240 unsigned enable;
241 struct pipe_constant_buffer esgs_ring;
242 struct pipe_constant_buffer gsvs_ring;
243 };
244
245 /* This must start from 16. */
246 /* features */
247 #define DBG_NO_CP_DMA (1 << 30)
248 /* shader backend */
249 #define DBG_NO_SB (1 << 21)
250 #define DBG_SB_CS (1 << 22)
251 #define DBG_SB_DRY_RUN (1 << 23)
252 #define DBG_SB_STAT (1 << 24)
253 #define DBG_SB_DUMP (1 << 25)
254 #define DBG_SB_NO_FALLBACK (1 << 26)
255 #define DBG_SB_DISASM (1 << 27)
256 #define DBG_SB_SAFEMATH (1 << 28)
257
258 struct r600_screen {
259 struct r600_common_screen b;
260 bool has_msaa;
261 bool has_compressed_msaa_texturing;
262 bool has_atomics;
263
264 /*for compute global memory binding, we allocate stuff here, instead of
265 * buffers.
266 * XXX: Not sure if this is the best place for global_pool. Also,
267 * it's not thread safe, so it won't work with multiple contexts. */
268 struct compute_memory_pool *global_pool;
269 };
270
271 struct r600_pipe_sampler_view {
272 struct pipe_sampler_view base;
273 struct list_head list;
274 struct r600_resource *tex_resource;
275 uint32_t tex_resource_words[8];
276 bool skip_mip_address_reloc;
277 bool is_stencil_sampler;
278 };
279
280 struct r600_rasterizer_state {
281 struct r600_command_buffer buffer;
282 boolean flatshade;
283 boolean two_side;
284 unsigned sprite_coord_enable;
285 unsigned clip_plane_enable;
286 unsigned pa_sc_line_stipple;
287 unsigned pa_cl_clip_cntl;
288 unsigned pa_su_sc_mode_cntl;
289 float offset_units;
290 float offset_scale;
291 bool offset_enable;
292 bool offset_units_unscaled;
293 bool scissor_enable;
294 bool multisample_enable;
295 bool clip_halfz;
296 bool rasterizer_discard;
297 };
298
299 struct r600_poly_offset_state {
300 struct r600_atom atom;
301 enum pipe_format zs_format;
302 float offset_units;
303 float offset_scale;
304 bool offset_units_unscaled;
305 };
306
307 struct r600_blend_state {
308 struct r600_command_buffer buffer;
309 struct r600_command_buffer buffer_no_blend;
310 unsigned cb_target_mask;
311 unsigned cb_color_control;
312 unsigned cb_color_control_no_blend;
313 bool dual_src_blend;
314 bool alpha_to_one;
315 };
316
317 struct r600_dsa_state {
318 struct r600_command_buffer buffer;
319 unsigned alpha_ref;
320 ubyte valuemask[2];
321 ubyte writemask[2];
322 unsigned zwritemask;
323 unsigned sx_alpha_test_control;
324 };
325
326 struct r600_pipe_shader;
327
328 struct r600_pipe_shader_selector {
329 struct r600_pipe_shader *current;
330
331 struct tgsi_token *tokens;
332 struct pipe_stream_output_info so;
333 struct tgsi_shader_info info;
334
335 unsigned num_shaders;
336
337 enum pipe_shader_type type;
338
339 /* geometry shader properties */
340 enum pipe_prim_type gs_output_prim;
341 unsigned gs_max_out_vertices;
342 unsigned gs_num_invocations;
343
344 /* TCS/VS */
345 uint64_t lds_patch_outputs_written_mask;
346 uint64_t lds_outputs_written_mask;
347 unsigned nr_ps_max_color_exports;
348 };
349
350 struct r600_pipe_sampler_state {
351 uint32_t tex_sampler_words[3];
352 union pipe_color_union border_color;
353 bool border_color_use;
354 bool seamless_cube_map;
355 };
356
357 /* needed for blitter save */
358 #define NUM_TEX_UNITS 16
359
360 struct r600_seamless_cube_map {
361 struct r600_atom atom;
362 bool enabled;
363 };
364
365 struct r600_samplerview_state {
366 struct r600_atom atom;
367 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
368 uint32_t enabled_mask;
369 uint32_t dirty_mask;
370 uint32_t compressed_depthtex_mask; /* which textures are depth */
371 uint32_t compressed_colortex_mask;
372 boolean dirty_buffer_constants;
373 };
374
375 struct r600_sampler_states {
376 struct r600_atom atom;
377 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
378 uint32_t enabled_mask;
379 uint32_t dirty_mask;
380 uint32_t has_bordercolor_mask; /* which states contain the border color */
381 };
382
383 struct r600_textures_info {
384 struct r600_samplerview_state views;
385 struct r600_sampler_states states;
386 bool is_array_sampler[NUM_TEX_UNITS];
387 };
388
389 struct r600_shader_driver_constants_info {
390 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
391 uint32_t *constants;
392 uint32_t alloc_size;
393 bool vs_ucp_dirty;
394 bool texture_const_dirty;
395 bool ps_sample_pos_dirty;
396 };
397
398 struct r600_constbuf_state
399 {
400 struct r600_atom atom;
401 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
402 uint32_t enabled_mask;
403 uint32_t dirty_mask;
404 };
405
406 struct r600_vertexbuf_state
407 {
408 struct r600_atom atom;
409 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
410 uint32_t enabled_mask; /* non-NULL buffers */
411 uint32_t dirty_mask;
412 };
413
414 /* CSO (constant state object, in other words, immutable state). */
415 struct r600_cso_state
416 {
417 struct r600_atom atom;
418 void *cso; /* e.g. r600_blend_state */
419 struct r600_command_buffer *cb;
420 };
421
422 struct r600_fetch_shader {
423 struct r600_resource *buffer;
424 unsigned offset;
425 };
426
427 struct r600_shader_state {
428 struct r600_atom atom;
429 struct r600_pipe_shader *shader;
430 };
431
432 struct r600_atomic_buffer_state {
433 uint32_t enabled_mask;
434 uint32_t dirty_mask;
435 struct pipe_shader_buffer buffer[EG_MAX_ATOMIC_BUFFERS];
436 };
437
438 struct r600_image_view {
439 struct pipe_image_view base;
440 uint32_t cb_color_base;
441 uint32_t cb_color_pitch;
442 uint32_t cb_color_slice;
443 uint32_t cb_color_view;
444 uint32_t cb_color_info;
445 uint32_t cb_color_attrib;
446 uint32_t cb_color_dim;
447 uint32_t cb_color_fmask;
448 uint32_t cb_color_fmask_slice;
449 uint32_t immed_resource_words[8];
450 uint32_t resource_words[8];
451 bool skip_mip_address_reloc;
452 uint32_t buf_size;
453 };
454
455 struct r600_image_state {
456 struct r600_atom atom;
457 uint32_t enabled_mask;
458 uint32_t dirty_mask;
459 uint32_t compressed_depthtex_mask;
460 uint32_t compressed_colortex_mask;
461 boolean dirty_buffer_constants;
462 struct r600_image_view views[R600_MAX_IMAGES];
463 };
464
465 struct r600_context {
466 struct r600_common_context b;
467 struct r600_screen *screen;
468 struct blitter_context *blitter;
469 struct u_suballocator *allocator_fetch_shader;
470
471 /* Hardware info. */
472 boolean has_vertex_cache;
473 unsigned default_gprs[EG_NUM_HW_STAGES];
474 unsigned current_gprs[EG_NUM_HW_STAGES];
475 unsigned r6xx_num_clause_temp_gprs;
476
477 /* Miscellaneous state objects. */
478 void *custom_dsa_flush;
479 void *custom_blend_resolve;
480 void *custom_blend_decompress;
481 void *custom_blend_fastclear;
482 /* With rasterizer discard, there doesn't have to be a pixel shader.
483 * In that case, we bind this one: */
484 void *dummy_pixel_shader;
485 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
486 * bug where valid CMASK and FMASK are required to be present to avoid
487 * a hardlock in certain operations but aren't actually used
488 * for anything useful. */
489 struct r600_resource *dummy_fmask;
490 struct r600_resource *dummy_cmask;
491
492 /* State binding slots are here. */
493 struct r600_atom *atoms[R600_NUM_ATOMS];
494 /* Dirty atom bitmask for fast tests */
495 uint64_t dirty_atoms;
496 /* States for CS initialization. */
497 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
498 /** Compute specific registers initializations. The start_cs_cmd atom
499 * must be emitted before start_compute_cs_cmd. */
500 struct r600_command_buffer start_compute_cs_cmd;
501 /* Register states. */
502 struct r600_alphatest_state alphatest_state;
503 struct r600_cso_state blend_state;
504 struct r600_blend_color blend_color;
505 struct r600_cb_misc_state cb_misc_state;
506 struct r600_clip_misc_state clip_misc_state;
507 struct r600_clip_state clip_state;
508 struct r600_db_misc_state db_misc_state;
509 struct r600_db_state db_state;
510 struct r600_cso_state dsa_state;
511 struct r600_framebuffer framebuffer;
512 struct r600_poly_offset_state poly_offset_state;
513 struct r600_cso_state rasterizer_state;
514 struct r600_sample_mask sample_mask;
515 struct r600_seamless_cube_map seamless_cube_map;
516 struct r600_config_state config_state;
517 struct r600_stencil_ref_state stencil_ref;
518 struct r600_vgt_state vgt_state;
519 struct r600_atomic_buffer_state atomic_buffer_state;
520 /* only have images on fragment shader */
521 struct r600_image_state fragment_images;
522 /* Shaders and shader resources. */
523 struct r600_cso_state vertex_fetch_shader;
524 struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES];
525 struct r600_cs_shader_state cs_shader_state;
526 struct r600_shader_stages_state shader_stages;
527 struct r600_gs_rings_state gs_rings;
528 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
529 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
530
531 struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES];
532
533 /** Vertex buffers for fetch shaders */
534 struct r600_vertexbuf_state vertex_buffer_state;
535 /** Vertex buffers for compute shaders */
536 struct r600_vertexbuf_state cs_vertex_buffer_state;
537
538 /* Additional context states. */
539 unsigned compute_cb_target_mask;
540 struct r600_pipe_shader_selector *ps_shader;
541 struct r600_pipe_shader_selector *vs_shader;
542 struct r600_pipe_shader_selector *gs_shader;
543
544 struct r600_pipe_shader_selector *tcs_shader;
545 struct r600_pipe_shader_selector *tes_shader;
546
547 struct r600_pipe_shader_selector *fixed_func_tcs_shader;
548
549 struct r600_rasterizer_state *rasterizer;
550 bool alpha_to_one;
551 bool force_blend_disable;
552 bool gs_tri_strip_adj_fix;
553 boolean dual_src_blend;
554 unsigned zwritemask;
555 int ps_iter_samples;
556
557 /* The list of all texture buffer objects in this context.
558 * This list is walked when a buffer is invalidated/reallocated and
559 * the GPU addresses are updated. */
560 struct list_head texture_buffers;
561
562 /* Last draw state (-1 = unset). */
563 enum pipe_prim_type last_primitive_type; /* Last primitive type used in draw_vbo. */
564 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
565 enum pipe_prim_type last_rast_prim;
566 unsigned last_start_instance;
567
568 void *sb_context;
569 struct r600_isa *isa;
570 float sample_positions[4 * 16];
571 float tess_state[8];
572 bool tess_state_dirty;
573 struct r600_pipe_shader_selector *last_ls;
574 struct r600_pipe_shader_selector *last_tcs;
575 unsigned last_num_tcs_input_cp;
576 unsigned lds_alloc;
577
578 /* Debug state. */
579 bool is_debug;
580 struct radeon_saved_cs last_gfx;
581 struct r600_resource *last_trace_buf;
582 struct r600_resource *trace_buf;
583 unsigned trace_id;
584
585 struct pipe_resource *append_fence;
586 uint32_t append_fence_id;
587 };
588
589 static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
590 struct r600_command_buffer *cb)
591 {
592 assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw);
593 memcpy(cs->current.buf + cs->current.cdw, cb->buf, 4 * cb->num_dw);
594 cs->current.cdw += cb->num_dw;
595 }
596
597 static inline void r600_set_atom_dirty(struct r600_context *rctx,
598 struct r600_atom *atom,
599 bool dirty)
600 {
601 uint64_t mask;
602
603 assert(atom->id != 0);
604 assert(atom->id < sizeof(mask) * 8);
605 mask = 1ull << atom->id;
606 if (dirty)
607 rctx->dirty_atoms |= mask;
608 else
609 rctx->dirty_atoms &= ~mask;
610 }
611
612 static inline void r600_mark_atom_dirty(struct r600_context *rctx,
613 struct r600_atom *atom)
614 {
615 r600_set_atom_dirty(rctx, atom, true);
616 }
617
618 static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
619 {
620 atom->emit(&rctx->b, atom);
621 r600_set_atom_dirty(rctx, atom, false);
622 }
623
624 static inline void r600_set_cso_state(struct r600_context *rctx,
625 struct r600_cso_state *state, void *cso)
626 {
627 state->cso = cso;
628 r600_set_atom_dirty(rctx, &state->atom, cso != NULL);
629 }
630
631 static inline void r600_set_cso_state_with_cb(struct r600_context *rctx,
632 struct r600_cso_state *state, void *cso,
633 struct r600_command_buffer *cb)
634 {
635 state->cb = cb;
636 state->atom.num_dw = cb ? cb->num_dw : 0;
637 r600_set_cso_state(rctx, state, cso);
638 }
639
640 /* compute_memory_pool.c */
641 struct compute_memory_pool;
642 void compute_memory_pool_delete(struct compute_memory_pool* pool);
643 struct compute_memory_pool* compute_memory_pool_new(
644 struct r600_screen *rscreen);
645
646 /* evergreen_state.c */
647 struct pipe_sampler_view *
648 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
649 struct pipe_resource *texture,
650 const struct pipe_sampler_view *state,
651 unsigned width0, unsigned height0,
652 unsigned force_level);
653 void evergreen_init_common_regs(struct r600_context *ctx,
654 struct r600_command_buffer *cb,
655 enum chip_class ctx_chip_class,
656 enum radeon_family ctx_family,
657 int ctx_drm_minor);
658 void cayman_init_common_regs(struct r600_command_buffer *cb,
659 enum chip_class ctx_chip_class,
660 enum radeon_family ctx_family,
661 int ctx_drm_minor);
662
663 void evergreen_init_state_functions(struct r600_context *rctx);
664 void evergreen_init_atom_start_cs(struct r600_context *rctx);
665 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
666 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
667 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
668 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
669 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
670 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
671 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
672 void *evergreen_create_resolve_blend(struct r600_context *rctx);
673 void *evergreen_create_decompress_blend(struct r600_context *rctx);
674 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
675 boolean evergreen_is_format_supported(struct pipe_screen *screen,
676 enum pipe_format format,
677 enum pipe_texture_target target,
678 unsigned sample_count,
679 unsigned usage);
680 void evergreen_init_color_surface(struct r600_context *rctx,
681 struct r600_surface *surf);
682 void evergreen_init_color_surface_rat(struct r600_context *rctx,
683 struct r600_surface *surf);
684 void evergreen_update_db_shader_control(struct r600_context * rctx);
685 bool evergreen_adjust_gprs(struct r600_context *rctx);
686 /* r600_blit.c */
687 void r600_init_blit_functions(struct r600_context *rctx);
688 void r600_decompress_depth_textures(struct r600_context *rctx,
689 struct r600_samplerview_state *textures);
690 void r600_decompress_depth_images(struct r600_context *rctx,
691 struct r600_image_state *images);
692 void r600_decompress_color_textures(struct r600_context *rctx,
693 struct r600_samplerview_state *textures);
694 void r600_decompress_color_images(struct r600_context *rctx,
695 struct r600_image_state *images);
696 void r600_resource_copy_region(struct pipe_context *ctx,
697 struct pipe_resource *dst,
698 unsigned dst_level,
699 unsigned dstx, unsigned dsty, unsigned dstz,
700 struct pipe_resource *src,
701 unsigned src_level,
702 const struct pipe_box *src_box);
703
704 /* r600_shader.c */
705 int r600_pipe_shader_create(struct pipe_context *ctx,
706 struct r600_pipe_shader *shader,
707 union r600_shader_key key);
708
709 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
710
711 /* r600_state.c */
712 struct pipe_sampler_view *
713 r600_create_sampler_view_custom(struct pipe_context *ctx,
714 struct pipe_resource *texture,
715 const struct pipe_sampler_view *state,
716 unsigned width_first_level, unsigned height_first_level);
717 void r600_init_state_functions(struct r600_context *rctx);
718 void r600_init_atom_start_cs(struct r600_context *rctx);
719 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
720 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
721 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
722 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
723 void *r600_create_db_flush_dsa(struct r600_context *rctx);
724 void *r600_create_resolve_blend(struct r600_context *rctx);
725 void *r700_create_resolve_blend(struct r600_context *rctx);
726 void *r600_create_decompress_blend(struct r600_context *rctx);
727 bool r600_adjust_gprs(struct r600_context *rctx);
728 boolean r600_is_format_supported(struct pipe_screen *screen,
729 enum pipe_format format,
730 enum pipe_texture_target target,
731 unsigned sample_count,
732 unsigned usage);
733 void r600_update_db_shader_control(struct r600_context * rctx);
734
735 /* r600_hw_context.c */
736 void r600_context_gfx_flush(void *context, unsigned flags,
737 struct pipe_fence_handle **fence);
738 void r600_begin_new_cs(struct r600_context *ctx);
739 void r600_flush_emit(struct r600_context *ctx);
740 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
741 void r600_emit_pfp_sync_me(struct r600_context *rctx);
742 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
743 struct pipe_resource *dst, uint64_t dst_offset,
744 struct pipe_resource *src, uint64_t src_offset,
745 unsigned size);
746 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
747 struct pipe_resource *dst, uint64_t offset,
748 unsigned size, uint32_t clear_value,
749 enum r600_coherency coher);
750 void r600_dma_copy_buffer(struct r600_context *rctx,
751 struct pipe_resource *dst,
752 struct pipe_resource *src,
753 uint64_t dst_offset,
754 uint64_t src_offset,
755 uint64_t size);
756
757 /*
758 * evergreen_hw_context.c
759 */
760 void evergreen_dma_copy_buffer(struct r600_context *rctx,
761 struct pipe_resource *dst,
762 struct pipe_resource *src,
763 uint64_t dst_offset,
764 uint64_t src_offset,
765 uint64_t size);
766 void evergreen_setup_tess_constants(struct r600_context *rctx,
767 const struct pipe_draw_info *info,
768 unsigned *num_patches);
769 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
770 const struct pipe_draw_info *info,
771 unsigned num_patches);
772 void evergreen_set_ls_hs_config(struct r600_context *rctx,
773 struct radeon_winsys_cs *cs,
774 uint32_t ls_hs_config);
775 void evergreen_set_lds_alloc(struct r600_context *rctx,
776 struct radeon_winsys_cs *cs,
777 uint32_t lds_alloc);
778
779 /* r600_state_common.c */
780 void r600_init_common_state_functions(struct r600_context *rctx);
781 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
782 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
783 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
784 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
785 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
786 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
787 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
788 void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
789 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
790 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
791 unsigned num_dw);
792 void r600_vertex_buffers_dirty(struct r600_context *rctx);
793 void r600_sampler_views_dirty(struct r600_context *rctx,
794 struct r600_samplerview_state *state);
795 void r600_sampler_states_dirty(struct r600_context *rctx,
796 struct r600_sampler_states *state);
797 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
798 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
799 uint32_t r600_translate_stencil_op(int s_op);
800 uint32_t r600_translate_fill(uint32_t func);
801 unsigned r600_tex_wrap(unsigned wrap);
802 unsigned r600_tex_mipfilter(unsigned filter);
803 unsigned r600_tex_compare(unsigned compare);
804 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
805 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
806 const unsigned char *swizzle_view,
807 boolean vtx);
808 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
809 const unsigned char *swizzle_view,
810 uint32_t *word4_p, uint32_t *yuv_format_p,
811 bool do_endian_swap);
812 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format,
813 bool do_endian_swap);
814 uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap);
815
816 /* r600_uvd.c */
817 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
818 const struct pipe_video_codec *decoder);
819
820 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
821 const struct pipe_video_buffer *tmpl);
822
823 /*
824 * Helpers for building command buffers
825 */
826
827 #define PKT3_SET_CONFIG_REG 0x68
828 #define PKT3_SET_CONTEXT_REG 0x69
829 #define PKT3_SET_CTL_CONST 0x6F
830 #define PKT3_SET_LOOP_CONST 0x6C
831
832 #define R600_CONFIG_REG_OFFSET 0x08000
833 #define R600_CONTEXT_REG_OFFSET 0x28000
834 #define R600_CTL_CONST_OFFSET 0x3CFF0
835 #define R600_LOOP_CONST_OFFSET 0X0003E200
836 #define EG_LOOP_CONST_OFFSET 0x0003A200
837
838 #define PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30)
839 #define PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16)
840 #define PKT3_IT_OPCODE_S(x) (((unsigned)(x) & 0xFF) << 8)
841 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
842 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
843
844 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
845
846 /*Evergreen Compute packet3*/
847 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
848
849 static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value)
850 {
851 cb->buf[cb->num_dw++] = value;
852 }
853
854 static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
855 {
856 assert(cb->num_dw+num <= cb->max_num_dw);
857 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
858 cb->num_dw += num;
859 }
860
861 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
862 {
863 assert(reg < R600_CONTEXT_REG_OFFSET);
864 assert(cb->num_dw+2+num <= cb->max_num_dw);
865 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
866 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
867 }
868
869 /**
870 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
871 * shaders.
872 */
873 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
874 {
875 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
876 assert(cb->num_dw+2+num <= cb->max_num_dw);
877 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
878 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
879 }
880
881 /**
882 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
883 * shaders.
884 */
885 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
886 {
887 assert(reg >= R600_CTL_CONST_OFFSET);
888 assert(cb->num_dw+2+num <= cb->max_num_dw);
889 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
890 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
891 }
892
893 static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
894 {
895 assert(reg >= R600_LOOP_CONST_OFFSET);
896 assert(cb->num_dw+2+num <= cb->max_num_dw);
897 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
898 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
899 }
900
901 /**
902 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
903 * shaders.
904 */
905 static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
906 {
907 assert(reg >= EG_LOOP_CONST_OFFSET);
908 assert(cb->num_dw+2+num <= cb->max_num_dw);
909 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
910 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
911 }
912
913 static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
914 {
915 r600_store_config_reg_seq(cb, reg, 1);
916 r600_store_value(cb, value);
917 }
918
919 static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
920 {
921 r600_store_context_reg_seq(cb, reg, 1);
922 r600_store_value(cb, value);
923 }
924
925 static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
926 {
927 r600_store_ctl_const_seq(cb, reg, 1);
928 r600_store_value(cb, value);
929 }
930
931 static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
932 {
933 r600_store_loop_const_seq(cb, reg, 1);
934 r600_store_value(cb, value);
935 }
936
937 static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
938 {
939 eg_store_loop_const_seq(cb, reg, 1);
940 r600_store_value(cb, value);
941 }
942
943 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
944 void r600_release_command_buffer(struct r600_command_buffer *cb);
945
946 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
947 {
948 radeon_set_context_reg_seq(cs, reg, num);
949 /* Set the compute bit on the packet header */
950 cs->current.buf[cs->current.cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
951 }
952
953 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
954 {
955 assert(reg >= R600_CTL_CONST_OFFSET);
956 assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
957 radeon_emit(cs, PKT3(PKT3_SET_CTL_CONST, num, 0));
958 radeon_emit(cs, (reg - R600_CTL_CONST_OFFSET) >> 2);
959 }
960
961 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
962 {
963 radeon_compute_set_context_reg_seq(cs, reg, 1);
964 radeon_emit(cs, value);
965 }
966
967 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
968 {
969 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
970 radeon_compute_set_context_reg(cs, reg, value);
971 } else {
972 radeon_set_context_reg(cs, reg, value);
973 }
974 }
975
976 static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
977 {
978 radeon_set_ctl_const_seq(cs, reg, 1);
979 radeon_emit(cs, value);
980 }
981
982 /*
983 * common helpers
984 */
985
986 /* 12.4 fixed-point */
987 static inline unsigned r600_pack_float_12p4(float x)
988 {
989 return x <= 0 ? 0 :
990 x >= 4096 ? 0xffff : x * 16;
991 }
992
993 static inline unsigned r600_get_flush_flags(enum r600_coherency coher)
994 {
995 switch (coher) {
996 default:
997 case R600_COHERENCY_NONE:
998 return 0;
999 case R600_COHERENCY_SHADER:
1000 return R600_CONTEXT_INV_CONST_CACHE |
1001 R600_CONTEXT_INV_VERTEX_CACHE |
1002 R600_CONTEXT_INV_TEX_CACHE |
1003 R600_CONTEXT_STREAMOUT_FLUSH;
1004 case R600_COHERENCY_CB_META:
1005 return R600_CONTEXT_FLUSH_AND_INV_CB |
1006 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1007 }
1008 }
1009
1010 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
1011 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
1012 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
1013
1014 unsigned r600_conv_prim_to_gs_out(unsigned mode);
1015
1016 void eg_trace_emit(struct r600_context *rctx);
1017 void eg_dump_debug_state(struct pipe_context *ctx, FILE *f,
1018 unsigned flags);
1019
1020 struct r600_shader_atomic;
1021 bool evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
1022 struct r600_shader_atomic *combined_atomics,
1023 uint8_t *atomic_used_mask_p);
1024 void evergreen_emit_atomic_buffer_save(struct r600_context *rctx,
1025 struct r600_shader_atomic *combined_atomics,
1026 uint8_t *atomic_used_mask_p);
1027
1028 #endif