2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "util/u_blitter.h"
30 #include "util/u_slab.h"
31 #include "util/u_suballoc.h"
33 #include "r600_llvm.h"
34 #include "r600_public.h"
35 #include "r600_resource.h"
37 #define R600_NUM_ATOMS 40
39 #define R600_TRACE_CS 0
41 #define R600_MAX_USER_CONST_BUFFERS 13
42 #define R600_MAX_DRIVER_CONST_BUFFERS 3
43 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
45 /* start driver buffers after user buffers */
46 #define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
47 #define R600_TXQ_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
48 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
50 #define R600_MAX_CONST_BUFFER_SIZE 4096
52 #ifdef PIPE_ARCH_BIG_ENDIAN
53 #define R600_BIG_ENDIAN 1
55 #define R600_BIG_ENDIAN 0
58 #define R600_MAP_BUFFER_ALIGNMENT 64
61 struct r600_shader_key
;
63 /* This encapsulates a state or an operation which can emitted into the GPU
64 * command stream. It's not limited to states only, it can be used for anything
65 * that wants to write commands into the CS (e.g. cache flushes). */
67 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
);
73 /* This is an atom containing GPU commands that never change.
74 * This is supposed to be copied directly into the CS. */
75 struct r600_command_buffer
{
82 struct r600_db_state
{
83 struct r600_atom atom
;
84 struct r600_surface
*rsurf
;
87 struct r600_db_misc_state
{
88 struct r600_atom atom
;
89 bool occlusion_query_enabled
;
90 bool flush_depthstencil_through_cb
;
91 bool flush_depthstencil_in_place
;
92 bool copy_depth
, copy_stencil
;
95 unsigned db_shader_control
;
99 struct r600_cb_misc_state
{
100 struct r600_atom atom
;
101 unsigned cb_color_control
; /* this comes from blend state */
102 unsigned blend_colormask
; /* 8*4 bits for 8 RGBA colorbuffers */
104 unsigned nr_ps_color_outputs
;
109 struct r600_clip_misc_state
{
110 struct r600_atom atom
;
111 unsigned pa_cl_clip_cntl
; /* from rasterizer */
112 unsigned pa_cl_vs_out_cntl
; /* from vertex shader */
113 unsigned clip_plane_enable
; /* from rasterizer */
114 unsigned clip_dist_write
; /* from vertex shader */
117 struct r600_alphatest_state
{
118 struct r600_atom atom
;
119 unsigned sx_alpha_test_control
; /* this comes from dsa state */
120 unsigned sx_alpha_ref
; /* this comes from dsa state */
122 bool cb0_export_16bpc
; /* from set_framebuffer_state */
125 struct r600_vgt_state
{
126 struct r600_atom atom
;
127 uint32_t vgt_multi_prim_ib_reset_en
;
128 uint32_t vgt_multi_prim_ib_reset_indx
;
129 uint32_t vgt_indx_offset
;
132 struct r600_blend_color
{
133 struct r600_atom atom
;
134 struct pipe_blend_color state
;
137 struct r600_clip_state
{
138 struct r600_atom atom
;
139 struct pipe_clip_state state
;
142 struct r600_cs_shader_state
{
143 struct r600_atom atom
;
144 unsigned kernel_index
;
145 struct r600_pipe_compute
*shader
;
148 struct r600_framebuffer
{
149 struct r600_atom atom
;
150 struct pipe_framebuffer_state state
;
151 unsigned compressed_cb_mask
;
155 bool is_msaa_resolve
;
158 struct r600_sample_mask
{
159 struct r600_atom atom
;
160 uint16_t sample_mask
; /* there are only 8 bits on EG, 16 bits on Cayman */
163 struct r600_config_state
{
164 struct r600_atom atom
;
165 unsigned sq_gpr_resource_mgmt_1
;
168 struct r600_stencil_ref
175 struct r600_stencil_ref_state
{
176 struct r600_atom atom
;
177 struct r600_stencil_ref state
;
178 struct pipe_stencil_ref pipe_state
;
181 struct r600_viewport_state
{
182 struct r600_atom atom
;
183 struct pipe_viewport_state state
;
186 struct compute_memory_pool
;
187 void compute_memory_pool_delete(struct compute_memory_pool
* pool
);
188 struct compute_memory_pool
* compute_memory_pool_new(
189 struct r600_screen
*rscreen
);
191 struct r600_pipe_fences
{
192 struct r600_resource
*bo
;
195 /* linked list of preallocated blocks */
196 struct list_head blocks
;
197 /* linked list of freed fences */
198 struct list_head pool
;
202 enum r600_msaa_texture_mode
{
203 /* If the hw can fetch the first sample only (no decompression available).
204 * This means MSAA texturing is not fully implemented. */
205 MSAA_TEXTURE_SAMPLE_ZERO
,
207 /* If the hw can fetch decompressed MSAA textures.
208 * Supported families: R600, R700, Evergreen.
209 * Cayman cannot use this, because it cannot do the decompression. */
210 MSAA_TEXTURE_DECOMPRESSED
,
212 /* If the hw can fetch compressed MSAA textures, which means shaders can
213 * read resolved FMASK. This yields the best performance.
214 * Supported families: Evergreen, Cayman. */
215 MSAA_TEXTURE_COMPRESSED
218 typedef boolean (*r600g_dma_blit_t
)(struct pipe_context
*ctx
,
219 struct pipe_resource
*dst
,
221 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
222 struct pipe_resource
*src
,
224 const struct pipe_box
*src_box
);
227 #define DBG_TEX_DEPTH (1 << 0)
228 #define DBG_COMPUTE (1 << 1)
230 #define DBG_FS (1 << 8)
231 #define DBG_VS (1 << 9)
232 #define DBG_GS (1 << 10)
233 #define DBG_PS (1 << 11)
234 #define DBG_CS (1 << 12)
236 #define DBG_NO_HYPERZ (1 << 16)
237 #define DBG_NO_LLVM (1 << 17)
240 struct pipe_screen screen
;
241 struct radeon_winsys
*ws
;
242 unsigned debug_flags
;
244 enum chip_class chip_class
;
245 struct radeon_info info
;
249 enum r600_msaa_texture_mode msaa_texture_support
;
250 struct r600_tiling_info tiling_info
;
251 struct r600_pipe_fences fences
;
253 /*for compute global memory binding, we allocate stuff here, instead of
255 * XXX: Not sure if this is the best place for global_pool. Also,
256 * it's not thread safe, so it won't work with multiple contexts. */
257 struct compute_memory_pool
*global_pool
;
259 struct r600_resource
*trace_bo
;
263 r600g_dma_blit_t dma_blit
;
266 struct r600_pipe_sampler_view
{
267 struct pipe_sampler_view base
;
268 struct r600_resource
*tex_resource
;
269 uint32_t tex_resource_words
[8];
270 bool skip_mip_address_reloc
;
273 struct r600_rasterizer_state
{
274 struct r600_command_buffer buffer
;
277 unsigned sprite_coord_enable
;
278 unsigned clip_plane_enable
;
279 unsigned pa_sc_line_stipple
;
280 unsigned pa_cl_clip_cntl
;
285 bool multisample_enable
;
288 struct r600_poly_offset_state
{
289 struct r600_atom atom
;
290 enum pipe_format zs_format
;
295 struct r600_blend_state
{
296 struct r600_command_buffer buffer
;
297 struct r600_command_buffer buffer_no_blend
;
298 unsigned cb_target_mask
;
299 unsigned cb_color_control
;
300 unsigned cb_color_control_no_blend
;
305 struct r600_dsa_state
{
306 struct r600_command_buffer buffer
;
311 unsigned sx_alpha_test_control
;
314 struct r600_pipe_shader
;
316 struct r600_pipe_shader_selector
{
317 struct r600_pipe_shader
*current
;
319 struct tgsi_token
*tokens
;
320 struct pipe_stream_output_info so
;
322 unsigned num_shaders
;
324 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
327 unsigned nr_ps_max_color_exports
;
330 struct r600_pipe_sampler_state
{
331 uint32_t tex_sampler_words
[3];
332 union pipe_color_union border_color
;
333 bool border_color_use
;
334 bool seamless_cube_map
;
337 /* needed for blitter save */
338 #define NUM_TEX_UNITS 16
340 struct r600_seamless_cube_map
{
341 struct r600_atom atom
;
345 struct r600_samplerview_state
{
346 struct r600_atom atom
;
347 struct r600_pipe_sampler_view
*views
[NUM_TEX_UNITS
];
348 uint32_t enabled_mask
;
350 uint32_t compressed_depthtex_mask
; /* which textures are depth */
351 uint32_t compressed_colortex_mask
;
352 boolean dirty_txq_constants
;
353 boolean dirty_buffer_constants
;
356 struct r600_sampler_states
{
357 struct r600_atom atom
;
358 struct r600_pipe_sampler_state
*states
[NUM_TEX_UNITS
];
359 uint32_t enabled_mask
;
361 uint32_t has_bordercolor_mask
; /* which states contain the border color */
364 struct r600_textures_info
{
365 struct r600_samplerview_state views
;
366 struct r600_sampler_states states
;
367 bool is_array_sampler
[NUM_TEX_UNITS
];
369 /* cube array txq workaround */
370 uint32_t *txq_constants
;
371 /* buffer related workarounds */
372 uint32_t *buffer_constants
;
376 struct pipe_reference reference
;
377 unsigned index
; /* in the shared bo */
378 struct r600_resource
*sleep_bo
;
379 struct list_head head
;
382 #define FENCE_BLOCK_SIZE 16
384 struct r600_fence_block
{
385 struct r600_fence fences
[FENCE_BLOCK_SIZE
];
386 struct list_head head
;
389 #define R600_CONSTANT_ARRAY_SIZE 256
390 #define R600_RESOURCE_ARRAY_SIZE 160
392 struct r600_constbuf_state
394 struct r600_atom atom
;
395 struct pipe_constant_buffer cb
[PIPE_MAX_CONSTANT_BUFFERS
];
396 uint32_t enabled_mask
;
400 struct r600_vertexbuf_state
402 struct r600_atom atom
;
403 struct pipe_vertex_buffer vb
[PIPE_MAX_ATTRIBS
];
404 uint32_t enabled_mask
; /* non-NULL buffers */
408 /* CSO (constant state object, in other words, immutable state). */
409 struct r600_cso_state
411 struct r600_atom atom
;
412 void *cso
; /* e.g. r600_blend_state */
413 struct r600_command_buffer
*cb
;
416 struct r600_scissor_state
418 struct r600_atom atom
;
419 struct pipe_scissor_state scissor
;
420 bool enable
; /* r6xx only */
423 struct r600_fetch_shader
{
424 struct r600_resource
*buffer
;
428 struct r600_shader_state
{
429 struct r600_atom atom
;
430 struct r600_pipe_shader_selector
*shader
;
433 struct r600_streamout
{
434 struct r600_atom begin_atom
;
436 unsigned num_dw_for_end
;
438 unsigned enabled_mask
;
439 unsigned num_targets
;
440 struct r600_so_target
*targets
[PIPE_MAX_SO_BUFFERS
];
442 unsigned append_bitmask
;
447 struct radeon_winsys_cs
*cs
;
449 void (*flush
)(void *ctx
, unsigned flags
);
453 struct r600_ring gfx
;
454 struct r600_ring dma
;
457 struct r600_context
{
458 struct pipe_context context
;
459 struct r600_screen
*screen
;
460 struct radeon_winsys
*ws
;
461 struct r600_rings rings
;
462 struct blitter_context
*blitter
;
463 struct u_upload_mgr
*uploader
;
464 struct u_suballocator
*allocator_so_filled_size
;
465 struct u_suballocator
*allocator_fetch_shader
;
466 struct util_slab_mempool pool_transfers
;
469 enum radeon_family family
;
470 enum chip_class chip_class
;
471 boolean has_vertex_cache
;
472 boolean keep_tiling_flags
;
473 unsigned default_ps_gprs
, default_vs_gprs
;
474 unsigned r6xx_num_clause_temp_gprs
;
475 unsigned backend_mask
;
476 unsigned max_db
; /* for OQ */
478 /* current unaccounted memory usage */
482 /* Miscellaneous state objects. */
483 void *custom_dsa_flush
;
484 void *custom_blend_resolve
;
485 void *custom_blend_decompress
;
486 void *custom_blend_fmask_decompress
;
487 /* With rasterizer discard, there doesn't have to be a pixel shader.
488 * In that case, we bind this one: */
489 void *dummy_pixel_shader
;
490 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
491 * bug where valid CMASK and FMASK are required to be present to avoid
492 * a hardlock in certain operations but aren't actually used
493 * for anything useful. */
494 struct r600_resource
*dummy_fmask
;
495 struct r600_resource
*dummy_cmask
;
497 /* State binding slots are here. */
498 struct r600_atom
*atoms
[R600_NUM_ATOMS
];
499 /* States for CS initialization. */
500 struct r600_command_buffer start_cs_cmd
; /* invariant state mostly */
501 /** Compute specific registers initializations. The start_cs_cmd atom
502 * must be emitted before start_compute_cs_cmd. */
503 struct r600_command_buffer start_compute_cs_cmd
;
504 /* Register states. */
505 struct r600_alphatest_state alphatest_state
;
506 struct r600_cso_state blend_state
;
507 struct r600_blend_color blend_color
;
508 struct r600_cb_misc_state cb_misc_state
;
509 struct r600_clip_misc_state clip_misc_state
;
510 struct r600_clip_state clip_state
;
511 struct r600_db_misc_state db_misc_state
;
512 struct r600_db_state db_state
;
513 struct r600_cso_state dsa_state
;
514 struct r600_framebuffer framebuffer
;
515 struct r600_poly_offset_state poly_offset_state
;
516 struct r600_cso_state rasterizer_state
;
517 struct r600_sample_mask sample_mask
;
518 struct r600_scissor_state scissor
;
519 struct r600_seamless_cube_map seamless_cube_map
;
520 struct r600_config_state config_state
;
521 struct r600_stencil_ref_state stencil_ref
;
522 struct r600_vgt_state vgt_state
;
523 struct r600_viewport_state viewport
;
524 /* Shaders and shader resources. */
525 struct r600_cso_state vertex_fetch_shader
;
526 struct r600_shader_state vertex_shader
;
527 struct r600_shader_state pixel_shader
;
528 struct r600_cs_shader_state cs_shader_state
;
529 struct r600_constbuf_state constbuf_state
[PIPE_SHADER_TYPES
];
530 struct r600_textures_info samplers
[PIPE_SHADER_TYPES
];
531 /** Vertex buffers for fetch shaders */
532 struct r600_vertexbuf_state vertex_buffer_state
;
533 /** Vertex buffers for compute shaders */
534 struct r600_vertexbuf_state cs_vertex_buffer_state
;
535 struct r600_streamout streamout
;
537 /* Additional context states. */
539 unsigned compute_cb_target_mask
;
540 struct r600_pipe_shader_selector
*ps_shader
;
541 struct r600_pipe_shader_selector
*vs_shader
;
542 struct r600_rasterizer_state
*rasterizer
;
544 bool force_blend_disable
;
545 boolean dual_src_blend
;
549 struct pipe_index_buffer index_buffer
;
551 /* Last draw state (-1 = unset). */
552 int last_primitive_type
; /* Last primitive type used in draw_vbo. */
553 int last_start_instance
;
556 /* The list of active queries. Only one query of each type can be active. */
557 int num_occlusion_queries
;
558 /* Keep track of non-timer queries, because they should be suspended
559 * during context flushing.
560 * The timer queries (TIME_ELAPSED) shouldn't be suspended. */
561 struct list_head active_nontimer_queries
;
562 unsigned num_cs_dw_nontimer_queries_suspend
;
563 /* If queries have been suspended. */
564 bool nontimer_queries_suspended
;
566 /* Render condition. */
567 struct pipe_query
*current_render_cond
;
568 unsigned current_render_cond_mode
;
569 boolean predicate_drawing
;
571 /* Deprecated state management. */
572 struct r600_range
*range
;
574 struct r600_block
**blocks
;
575 struct list_head dirty
;
576 struct list_head enable_list
;
577 unsigned pm4_dirty_cdwords
;
579 struct r600_isa
*isa
;
582 static INLINE
void r600_emit_command_buffer(struct radeon_winsys_cs
*cs
,
583 struct r600_command_buffer
*cb
)
585 assert(cs
->cdw
+ cb
->num_dw
<= RADEON_MAX_CMDBUF_DWORDS
);
586 memcpy(cs
->buf
+ cs
->cdw
, cb
->buf
, 4 * cb
->num_dw
);
587 cs
->cdw
+= cb
->num_dw
;
591 void r600_trace_emit(struct r600_context
*rctx
);
594 static INLINE
void r600_emit_atom(struct r600_context
*rctx
, struct r600_atom
*atom
)
596 atom
->emit(rctx
, atom
);
599 if (rctx
->screen
->trace_bo
) {
600 r600_trace_emit(rctx
);
605 static INLINE
void r600_set_cso_state(struct r600_cso_state
*state
, void *cso
)
608 state
->atom
.dirty
= cso
!= NULL
;
611 static INLINE
void r600_set_cso_state_with_cb(struct r600_cso_state
*state
, void *cso
,
612 struct r600_command_buffer
*cb
)
615 state
->atom
.num_dw
= cb
->num_dw
;
616 r600_set_cso_state(state
, cso
);
619 /* evergreen_state.c */
620 struct pipe_sampler_view
*
621 evergreen_create_sampler_view_custom(struct pipe_context
*ctx
,
622 struct pipe_resource
*texture
,
623 const struct pipe_sampler_view
*state
,
624 unsigned width0
, unsigned height0
);
625 void evergreen_init_common_regs(struct r600_command_buffer
*cb
,
626 enum chip_class ctx_chip_class
,
627 enum radeon_family ctx_family
,
629 void cayman_init_common_regs(struct r600_command_buffer
*cb
,
630 enum chip_class ctx_chip_class
,
631 enum radeon_family ctx_family
,
634 void evergreen_init_state_functions(struct r600_context
*rctx
);
635 void evergreen_init_atom_start_cs(struct r600_context
*rctx
);
636 void evergreen_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
637 void evergreen_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
638 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
);
639 void *evergreen_create_resolve_blend(struct r600_context
*rctx
);
640 void *evergreen_create_decompress_blend(struct r600_context
*rctx
);
641 void *evergreen_create_fmask_decompress_blend(struct r600_context
*rctx
);
642 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
643 enum pipe_format format
,
644 enum pipe_texture_target target
,
645 unsigned sample_count
,
647 void evergreen_init_color_surface(struct r600_context
*rctx
,
648 struct r600_surface
*surf
);
649 void evergreen_init_color_surface_rat(struct r600_context
*rctx
,
650 struct r600_surface
*surf
);
651 void evergreen_update_db_shader_control(struct r600_context
* rctx
);
654 void r600_copy_buffer(struct pipe_context
*ctx
, struct pipe_resource
*dst
, unsigned dstx
,
655 struct pipe_resource
*src
, const struct pipe_box
*src_box
);
656 void r600_init_blit_functions(struct r600_context
*rctx
);
657 void r600_blit_decompress_depth(struct pipe_context
*ctx
,
658 struct r600_texture
*texture
,
659 struct r600_texture
*staging
,
660 unsigned first_level
, unsigned last_level
,
661 unsigned first_layer
, unsigned last_layer
,
662 unsigned first_sample
, unsigned last_sample
);
663 void r600_decompress_depth_textures(struct r600_context
*rctx
,
664 struct r600_samplerview_state
*textures
);
665 void r600_decompress_color_textures(struct r600_context
*rctx
,
666 struct r600_samplerview_state
*textures
);
669 bool r600_init_resource(struct r600_screen
*rscreen
,
670 struct r600_resource
*res
,
671 unsigned size
, unsigned alignment
,
672 bool use_reusable_pool
, unsigned usage
);
673 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
674 const struct pipe_resource
*templ
,
678 boolean
r600_rings_is_buffer_referenced(struct r600_context
*ctx
,
679 struct radeon_winsys_cs_handle
*buf
,
680 enum radeon_bo_usage usage
);
681 void *r600_buffer_mmap_sync_with_rings(struct r600_context
*ctx
,
682 struct r600_resource
*resource
,
686 void r600_init_query_functions(struct r600_context
*rctx
);
687 void r600_suspend_nontimer_queries(struct r600_context
*ctx
);
688 void r600_resume_nontimer_queries(struct r600_context
*ctx
);
690 /* r600_resource.c */
691 void r600_init_context_resource_functions(struct r600_context
*r600
);
694 int r600_pipe_shader_create(struct pipe_context
*ctx
,
695 struct r600_pipe_shader
*shader
,
696 struct r600_shader_key key
);
698 int r600_compute_shader_create(struct pipe_context
* ctx
,
699 LLVMModuleRef mod
, struct r600_bytecode
* bytecode
);
701 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
704 struct pipe_sampler_view
*
705 r600_create_sampler_view_custom(struct pipe_context
*ctx
,
706 struct pipe_resource
*texture
,
707 const struct pipe_sampler_view
*state
,
708 unsigned width_first_level
, unsigned height_first_level
);
709 void r600_init_state_functions(struct r600_context
*rctx
);
710 void r600_init_atom_start_cs(struct r600_context
*rctx
);
711 void r600_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
712 void r600_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
713 void *r600_create_db_flush_dsa(struct r600_context
*rctx
);
714 void *r600_create_resolve_blend(struct r600_context
*rctx
);
715 void *r700_create_resolve_blend(struct r600_context
*rctx
);
716 void *r600_create_decompress_blend(struct r600_context
*rctx
);
717 bool r600_adjust_gprs(struct r600_context
*rctx
);
718 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
719 enum pipe_format format
,
720 enum pipe_texture_target target
,
721 unsigned sample_count
,
723 void r600_update_db_shader_control(struct r600_context
* rctx
);
726 void r600_init_screen_texture_functions(struct pipe_screen
*screen
);
727 void r600_init_surface_functions(struct r600_context
*r600
);
728 uint32_t r600_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
729 const unsigned char *swizzle_view
,
730 uint32_t *word4_p
, uint32_t *yuv_format_p
);
731 unsigned r600_texture_get_offset(struct r600_texture
*rtex
,
732 unsigned level
, unsigned layer
);
733 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
734 struct pipe_resource
*texture
,
735 const struct pipe_surface
*templ
,
736 unsigned width
, unsigned height
);
738 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
739 const unsigned char *swizzle_view
,
742 /* r600_hw_context.c */
743 void r600_emit_streamout_begin(struct r600_context
*ctx
, struct r600_atom
*atom
);
744 void r600_emit_streamout_end(struct r600_context
*ctx
);
746 /* r600_state_common.c */
747 void r600_init_common_state_functions(struct r600_context
*rctx
);
748 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
749 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
750 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
);
751 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
752 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
753 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
);
754 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
755 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
);
756 void r600_init_atom(struct r600_context
*rctx
, struct r600_atom
*atom
, unsigned id
,
757 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
759 void r600_vertex_buffers_dirty(struct r600_context
*rctx
);
760 void r600_sampler_views_dirty(struct r600_context
*rctx
,
761 struct r600_samplerview_state
*state
);
762 void r600_sampler_states_dirty(struct r600_context
*rctx
,
763 struct r600_sampler_states
*state
);
764 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
);
765 void r600_streamout_buffers_dirty(struct r600_context
*rctx
);
766 void r600_draw_rectangle(struct blitter_context
*blitter
,
767 int x1
, int y1
, int x2
, int y2
, float depth
,
768 enum blitter_attrib_type type
, const union pipe_color_union
*attrib
);
769 uint32_t r600_translate_stencil_op(int s_op
);
770 uint32_t r600_translate_fill(uint32_t func
);
771 unsigned r600_tex_wrap(unsigned wrap
);
772 unsigned r600_tex_filter(unsigned filter
);
773 unsigned r600_tex_mipfilter(unsigned filter
);
774 unsigned r600_tex_compare(unsigned compare
);
775 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
);
778 * Helpers for building command buffers
781 #define PKT3_SET_CONFIG_REG 0x68
782 #define PKT3_SET_CONTEXT_REG 0x69
783 #define PKT3_SET_CTL_CONST 0x6F
784 #define PKT3_SET_LOOP_CONST 0x6C
786 #define R600_CONFIG_REG_OFFSET 0x08000
787 #define R600_CONTEXT_REG_OFFSET 0x28000
788 #define R600_CTL_CONST_OFFSET 0x3CFF0
789 #define R600_LOOP_CONST_OFFSET 0X0003E200
790 #define EG_LOOP_CONST_OFFSET 0x0003A200
792 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
793 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
794 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
795 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
796 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
798 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
800 /*Evergreen Compute packet3*/
801 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
803 static INLINE
void r600_store_value(struct r600_command_buffer
*cb
, unsigned value
)
805 cb
->buf
[cb
->num_dw
++] = value
;
808 static INLINE
void r600_store_array(struct r600_command_buffer
*cb
, unsigned num
, unsigned *ptr
)
810 assert(cb
->num_dw
+num
<= cb
->max_num_dw
);
811 memcpy(&cb
->buf
[cb
->num_dw
], ptr
, num
* sizeof(ptr
[0]));
815 static INLINE
void r600_store_config_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
817 assert(reg
< R600_CONTEXT_REG_OFFSET
);
818 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
819 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
820 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
824 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
827 static INLINE
void r600_store_context_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
829 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
830 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
831 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0) | cb
->pkt_flags
;
832 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
836 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
839 static INLINE
void r600_store_ctl_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
841 assert(reg
>= R600_CTL_CONST_OFFSET
);
842 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
843 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0) | cb
->pkt_flags
;
844 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
847 static INLINE
void r600_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
849 assert(reg
>= R600_LOOP_CONST_OFFSET
);
850 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
851 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0);
852 cb
->buf
[cb
->num_dw
++] = (reg
- R600_LOOP_CONST_OFFSET
) >> 2;
856 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
859 static INLINE
void eg_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
861 assert(reg
>= EG_LOOP_CONST_OFFSET
);
862 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
863 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0) | cb
->pkt_flags
;
864 cb
->buf
[cb
->num_dw
++] = (reg
- EG_LOOP_CONST_OFFSET
) >> 2;
867 static INLINE
void r600_store_config_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
869 r600_store_config_reg_seq(cb
, reg
, 1);
870 r600_store_value(cb
, value
);
873 static INLINE
void r600_store_context_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
875 r600_store_context_reg_seq(cb
, reg
, 1);
876 r600_store_value(cb
, value
);
879 static INLINE
void r600_store_ctl_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
881 r600_store_ctl_const_seq(cb
, reg
, 1);
882 r600_store_value(cb
, value
);
885 static INLINE
void r600_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
887 r600_store_loop_const_seq(cb
, reg
, 1);
888 r600_store_value(cb
, value
);
891 static INLINE
void eg_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
893 eg_store_loop_const_seq(cb
, reg
, 1);
894 r600_store_value(cb
, value
);
897 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
);
898 void r600_release_command_buffer(struct r600_command_buffer
*cb
);
901 * Helpers for emitting state into a command stream directly.
903 static INLINE
unsigned r600_context_bo_reloc(struct r600_context
*ctx
,
904 struct r600_ring
*ring
,
905 struct r600_resource
*rbo
,
906 enum radeon_bo_usage usage
)
909 /* make sure that all previous ring use are flushed so everything
910 * look serialized from driver pov
912 if (!ring
->flushing
) {
913 if (ring
== &ctx
->rings
.gfx
) {
914 if (ctx
->rings
.dma
.cs
) {
916 ctx
->rings
.dma
.flush(ctx
, RADEON_FLUSH_ASYNC
);
920 ctx
->rings
.gfx
.flush(ctx
, RADEON_FLUSH_ASYNC
);
923 return ctx
->ws
->cs_add_reloc(ring
->cs
, rbo
->cs_buf
, usage
, rbo
->domains
) * 4;
926 static INLINE
void r600_write_value(struct radeon_winsys_cs
*cs
, unsigned value
)
928 cs
->buf
[cs
->cdw
++] = value
;
931 static INLINE
void r600_write_array(struct radeon_winsys_cs
*cs
, unsigned num
, unsigned *ptr
)
933 assert(cs
->cdw
+num
<= RADEON_MAX_CMDBUF_DWORDS
);
934 memcpy(&cs
->buf
[cs
->cdw
], ptr
, num
* sizeof(ptr
[0]));
938 static INLINE
void r600_write_config_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
940 assert(reg
< R600_CONTEXT_REG_OFFSET
);
941 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
942 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
943 cs
->buf
[cs
->cdw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
946 static INLINE
void r600_write_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
948 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
949 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
950 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0);
951 cs
->buf
[cs
->cdw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
954 static INLINE
void r600_write_compute_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
956 r600_write_context_reg_seq(cs
, reg
, num
);
957 /* Set the compute bit on the packet header */
958 cs
->buf
[cs
->cdw
- 2] |= RADEON_CP_PACKET3_COMPUTE_MODE
;
961 static INLINE
void r600_write_ctl_const_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
963 assert(reg
>= R600_CTL_CONST_OFFSET
);
964 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
965 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0);
966 cs
->buf
[cs
->cdw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
969 static INLINE
void r600_write_config_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
971 r600_write_config_reg_seq(cs
, reg
, 1);
972 r600_write_value(cs
, value
);
975 static INLINE
void r600_write_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
977 r600_write_context_reg_seq(cs
, reg
, 1);
978 r600_write_value(cs
, value
);
981 static INLINE
void r600_write_compute_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
983 r600_write_compute_context_reg_seq(cs
, reg
, 1);
984 r600_write_value(cs
, value
);
987 static INLINE
void r600_write_ctl_const(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
989 r600_write_ctl_const_seq(cs
, reg
, 1);
990 r600_write_value(cs
, value
);
996 static INLINE
uint32_t S_FIXED(float value
, uint32_t frac_bits
)
998 return value
* (1 << frac_bits
);
1000 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
1002 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
1004 if (filter
<= 1) return 0;
1005 if (filter
<= 2) return 1;
1006 if (filter
<= 4) return 2;
1007 if (filter
<= 8) return 3;
1008 /* else */ return 4;
1011 /* 12.4 fixed-point */
1012 static INLINE
unsigned r600_pack_float_12p4(float x
)
1015 x
>= 4096 ? 0xffff : x
* 16;
1018 static INLINE
uint64_t r600_resource_va(struct pipe_screen
*screen
, struct pipe_resource
*resource
)
1020 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
1021 struct r600_resource
*rresource
= (struct r600_resource
*)resource
;
1023 return rscreen
->ws
->buffer_get_virtual_address(rresource
->cs_buf
);
1026 static INLINE
void r600_context_add_resource_size(struct pipe_context
*ctx
, struct pipe_resource
*r
)
1028 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1029 struct r600_resource
*rr
= (struct r600_resource
*)r
;
1036 * The idea is to compute a gross estimate of memory requirement of
1037 * each draw call. After each draw call, memory will be precisely
1038 * accounted. So the uncertainty is only on the current draw call.
1039 * In practice this gave very good estimate (+/- 10% of the target
1042 if (rr
->domains
& RADEON_DOMAIN_GTT
) {
1043 rctx
->gtt
+= rr
->buf
->size
;
1045 if (rr
->domains
& RADEON_DOMAIN_VRAM
) {
1046 rctx
->vram
+= rr
->buf
->size
;