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[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "util/u_blitter.h"
30 #include "util/u_slab.h"
31 #include "util/u_suballoc.h"
32 #include "util/u_double_list.h"
33 #include "util/u_transfer.h"
34 #include "r600_llvm.h"
35 #include "r600_public.h"
36 #include "r600_resource.h"
37
38 #define R600_NUM_ATOMS 41
39
40 /* the number of CS dwords for flushing and drawing */
41 #define R600_MAX_FLUSH_CS_DWORDS 16
42 #define R600_MAX_DRAW_CS_DWORDS 34
43 #define R600_TRACE_CS_DWORDS 7
44
45 #define R600_MAX_USER_CONST_BUFFERS 13
46 #define R600_MAX_DRIVER_CONST_BUFFERS 3
47 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
48
49 /* start driver buffers after user buffers */
50 #define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
51 #define R600_TXQ_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
52 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
53
54 #define R600_MAX_CONST_BUFFER_SIZE 4096
55
56 #ifdef PIPE_ARCH_BIG_ENDIAN
57 #define R600_BIG_ENDIAN 1
58 #else
59 #define R600_BIG_ENDIAN 0
60 #endif
61
62 #define R600_MAP_BUFFER_ALIGNMENT 64
63
64 #define R600_ERR(fmt, args...) \
65 fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
66
67 #define R600_CONTEXT_INVAL_READ_CACHES (1 << 0)
68 #define R600_CONTEXT_STREAMOUT_FLUSH (1 << 1)
69 #define R600_CONTEXT_WAIT_3D_IDLE (1 << 2)
70 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (1 << 3)
71 #define R600_CONTEXT_FLUSH_AND_INV (1 << 4)
72 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (1 << 5)
73 #define R600_CONTEXT_PS_PARTIAL_FLUSH (1 << 6)
74 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (1 << 7)
75
76 #define R600_QUERY_DRAW_CALLS (PIPE_QUERY_DRIVER_SPECIFIC + 0)
77 #define R600_QUERY_REQUESTED_VRAM (PIPE_QUERY_DRIVER_SPECIFIC + 1)
78 #define R600_QUERY_REQUESTED_GTT (PIPE_QUERY_DRIVER_SPECIFIC + 2)
79 #define R600_QUERY_BUFFER_WAIT_TIME (PIPE_QUERY_DRIVER_SPECIFIC + 3)
80
81 struct r600_context;
82 struct r600_bytecode;
83 struct r600_shader_key;
84
85 /* This encapsulates a state or an operation which can emitted into the GPU
86 * command stream. It's not limited to states only, it can be used for anything
87 * that wants to write commands into the CS (e.g. cache flushes). */
88 struct r600_atom {
89 void (*emit)(struct r600_context *ctx, struct r600_atom *state);
90 unsigned id;
91 unsigned num_dw;
92 bool dirty;
93 };
94
95 /* This is an atom containing GPU commands that never change.
96 * This is supposed to be copied directly into the CS. */
97 struct r600_command_buffer {
98 uint32_t *buf;
99 unsigned num_dw;
100 unsigned max_num_dw;
101 unsigned pkt_flags;
102 };
103
104 struct r600_db_state {
105 struct r600_atom atom;
106 struct r600_surface *rsurf;
107 };
108
109 struct r600_db_misc_state {
110 struct r600_atom atom;
111 bool occlusion_query_enabled;
112 bool flush_depthstencil_through_cb;
113 bool flush_depthstencil_in_place;
114 bool copy_depth, copy_stencil;
115 unsigned copy_sample;
116 unsigned log_samples;
117 unsigned db_shader_control;
118 bool htile_clear;
119 };
120
121 struct r600_cb_misc_state {
122 struct r600_atom atom;
123 unsigned cb_color_control; /* this comes from blend state */
124 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
125 unsigned nr_cbufs;
126 unsigned nr_ps_color_outputs;
127 bool multiwrite;
128 bool dual_src_blend;
129 };
130
131 struct r600_clip_misc_state {
132 struct r600_atom atom;
133 unsigned pa_cl_clip_cntl; /* from rasterizer */
134 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
135 unsigned clip_plane_enable; /* from rasterizer */
136 unsigned clip_dist_write; /* from vertex shader */
137 };
138
139 struct r600_alphatest_state {
140 struct r600_atom atom;
141 unsigned sx_alpha_test_control; /* this comes from dsa state */
142 unsigned sx_alpha_ref; /* this comes from dsa state */
143 bool bypass;
144 bool cb0_export_16bpc; /* from set_framebuffer_state */
145 };
146
147 struct r600_vgt_state {
148 struct r600_atom atom;
149 uint32_t vgt_multi_prim_ib_reset_en;
150 uint32_t vgt_multi_prim_ib_reset_indx;
151 uint32_t vgt_indx_offset;
152 };
153
154 struct r600_blend_color {
155 struct r600_atom atom;
156 struct pipe_blend_color state;
157 };
158
159 struct r600_clip_state {
160 struct r600_atom atom;
161 struct pipe_clip_state state;
162 };
163
164 struct r600_cs_shader_state {
165 struct r600_atom atom;
166 unsigned kernel_index;
167 struct r600_pipe_compute *shader;
168 };
169
170 struct r600_framebuffer {
171 struct r600_atom atom;
172 struct pipe_framebuffer_state state;
173 unsigned compressed_cb_mask;
174 unsigned nr_samples;
175 bool export_16bpc;
176 bool cb0_is_integer;
177 bool is_msaa_resolve;
178 };
179
180 struct r600_sample_mask {
181 struct r600_atom atom;
182 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
183 };
184
185 struct r600_config_state {
186 struct r600_atom atom;
187 unsigned sq_gpr_resource_mgmt_1;
188 };
189
190 struct r600_stencil_ref
191 {
192 ubyte ref_value[2];
193 ubyte valuemask[2];
194 ubyte writemask[2];
195 };
196
197 struct r600_stencil_ref_state {
198 struct r600_atom atom;
199 struct r600_stencil_ref state;
200 struct pipe_stencil_ref pipe_state;
201 };
202
203 struct r600_viewport_state {
204 struct r600_atom atom;
205 struct pipe_viewport_state state;
206 };
207
208 struct r600_pipe_fences {
209 struct r600_resource *bo;
210 unsigned *data;
211 unsigned next_index;
212 /* linked list of preallocated blocks */
213 struct list_head blocks;
214 /* linked list of freed fences */
215 struct list_head pool;
216 pipe_mutex mutex;
217 };
218
219 enum r600_msaa_texture_mode {
220 /* If the hw can fetch the first sample only (no decompression available).
221 * This means MSAA texturing is not fully implemented. */
222 MSAA_TEXTURE_SAMPLE_ZERO,
223
224 /* If the hw can fetch decompressed MSAA textures.
225 * Supported families: R600, R700, Evergreen.
226 * Cayman cannot use this, because it cannot do the decompression. */
227 MSAA_TEXTURE_DECOMPRESSED,
228
229 /* If the hw can fetch compressed MSAA textures, which means shaders can
230 * read resolved FMASK. This yields the best performance.
231 * Supported families: Evergreen, Cayman. */
232 MSAA_TEXTURE_COMPRESSED
233 };
234
235 typedef boolean (*r600g_dma_blit_t)(struct pipe_context *ctx,
236 struct pipe_resource *dst,
237 unsigned dst_level,
238 unsigned dst_x, unsigned dst_y, unsigned dst_z,
239 struct pipe_resource *src,
240 unsigned src_level,
241 const struct pipe_box *src_box);
242
243 /* logging */
244 #define DBG_TEX_DEPTH (1 << 0)
245 #define DBG_COMPUTE (1 << 1)
246 #define DBG_VM (1 << 2)
247 #define DBG_TRACE_CS (1 << 3)
248 /* shaders */
249 #define DBG_FS (1 << 8)
250 #define DBG_VS (1 << 9)
251 #define DBG_GS (1 << 10)
252 #define DBG_PS (1 << 11)
253 #define DBG_CS (1 << 12)
254 /* features */
255 #define DBG_NO_HYPERZ (1 << 16)
256 #define DBG_NO_LLVM (1 << 17)
257 #define DBG_NO_CP_DMA (1 << 18)
258 #define DBG_NO_ASYNC_DMA (1 << 19)
259 #define DBG_NO_DISCARD_RANGE (1 << 20)
260 /* shader backend */
261 #define DBG_SB (1 << 21)
262 #define DBG_SB_CS (1 << 22)
263 #define DBG_SB_DRY_RUN (1 << 23)
264 #define DBG_SB_STAT (1 << 24)
265 #define DBG_SB_DUMP (1 << 25)
266 #define DBG_SB_NO_FALLBACK (1 << 26)
267 #define DBG_SB_DISASM (1 << 27)
268
269 struct r600_tiling_info {
270 unsigned num_channels;
271 unsigned num_banks;
272 unsigned group_bytes;
273 };
274
275 struct r600_screen {
276 struct pipe_screen screen;
277 struct radeon_winsys *ws;
278 unsigned debug_flags;
279 unsigned family;
280 enum chip_class chip_class;
281 struct radeon_info info;
282 bool has_streamout;
283 bool has_msaa;
284 bool has_cp_dma;
285 enum r600_msaa_texture_mode msaa_texture_support;
286 struct r600_tiling_info tiling_info;
287 struct r600_pipe_fences fences;
288
289 /*for compute global memory binding, we allocate stuff here, instead of
290 * buffers.
291 * XXX: Not sure if this is the best place for global_pool. Also,
292 * it's not thread safe, so it won't work with multiple contexts. */
293 struct compute_memory_pool *global_pool;
294 struct r600_resource *trace_bo;
295 uint32_t *trace_ptr;
296 unsigned cs_count;
297 r600g_dma_blit_t dma_blit;
298
299 /* Auxiliary context. Mainly used to initialize resources.
300 * It must be locked prior to using and flushed before unlocking. */
301 struct pipe_context *aux_context;
302 pipe_mutex aux_context_lock;
303 };
304
305 struct r600_pipe_sampler_view {
306 struct pipe_sampler_view base;
307 struct r600_resource *tex_resource;
308 uint32_t tex_resource_words[8];
309 bool skip_mip_address_reloc;
310 };
311
312 struct r600_rasterizer_state {
313 struct r600_command_buffer buffer;
314 boolean flatshade;
315 boolean two_side;
316 unsigned sprite_coord_enable;
317 unsigned clip_plane_enable;
318 unsigned pa_sc_line_stipple;
319 unsigned pa_cl_clip_cntl;
320 float offset_units;
321 float offset_scale;
322 bool offset_enable;
323 bool scissor_enable;
324 bool multisample_enable;
325 };
326
327 struct r600_poly_offset_state {
328 struct r600_atom atom;
329 enum pipe_format zs_format;
330 float offset_units;
331 float offset_scale;
332 };
333
334 struct r600_blend_state {
335 struct r600_command_buffer buffer;
336 struct r600_command_buffer buffer_no_blend;
337 unsigned cb_target_mask;
338 unsigned cb_color_control;
339 unsigned cb_color_control_no_blend;
340 bool dual_src_blend;
341 bool alpha_to_one;
342 };
343
344 struct r600_dsa_state {
345 struct r600_command_buffer buffer;
346 unsigned alpha_ref;
347 ubyte valuemask[2];
348 ubyte writemask[2];
349 unsigned zwritemask;
350 unsigned sx_alpha_test_control;
351 };
352
353 struct r600_pipe_shader;
354
355 struct r600_pipe_shader_selector {
356 struct r600_pipe_shader *current;
357
358 struct tgsi_token *tokens;
359 struct pipe_stream_output_info so;
360
361 unsigned num_shaders;
362
363 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
364 unsigned type;
365
366 unsigned nr_ps_max_color_exports;
367 };
368
369 struct r600_pipe_sampler_state {
370 uint32_t tex_sampler_words[3];
371 union pipe_color_union border_color;
372 bool border_color_use;
373 bool seamless_cube_map;
374 };
375
376 /* needed for blitter save */
377 #define NUM_TEX_UNITS 16
378
379 struct r600_seamless_cube_map {
380 struct r600_atom atom;
381 bool enabled;
382 };
383
384 struct r600_samplerview_state {
385 struct r600_atom atom;
386 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
387 uint32_t enabled_mask;
388 uint32_t dirty_mask;
389 uint32_t compressed_depthtex_mask; /* which textures are depth */
390 uint32_t compressed_colortex_mask;
391 boolean dirty_txq_constants;
392 boolean dirty_buffer_constants;
393 };
394
395 struct r600_sampler_states {
396 struct r600_atom atom;
397 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
398 uint32_t enabled_mask;
399 uint32_t dirty_mask;
400 uint32_t has_bordercolor_mask; /* which states contain the border color */
401 };
402
403 struct r600_textures_info {
404 struct r600_samplerview_state views;
405 struct r600_sampler_states states;
406 bool is_array_sampler[NUM_TEX_UNITS];
407
408 /* cube array txq workaround */
409 uint32_t *txq_constants;
410 /* buffer related workarounds */
411 uint32_t *buffer_constants;
412 };
413
414 struct r600_fence {
415 struct pipe_reference reference;
416 unsigned index; /* in the shared bo */
417 struct r600_resource *sleep_bo;
418 struct list_head head;
419 };
420
421 #define FENCE_BLOCK_SIZE 16
422
423 struct r600_fence_block {
424 struct r600_fence fences[FENCE_BLOCK_SIZE];
425 struct list_head head;
426 };
427
428 #define R600_CONSTANT_ARRAY_SIZE 256
429 #define R600_RESOURCE_ARRAY_SIZE 160
430
431 struct r600_constbuf_state
432 {
433 struct r600_atom atom;
434 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
435 uint32_t enabled_mask;
436 uint32_t dirty_mask;
437 };
438
439 struct r600_vertexbuf_state
440 {
441 struct r600_atom atom;
442 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
443 uint32_t enabled_mask; /* non-NULL buffers */
444 uint32_t dirty_mask;
445 };
446
447 /* CSO (constant state object, in other words, immutable state). */
448 struct r600_cso_state
449 {
450 struct r600_atom atom;
451 void *cso; /* e.g. r600_blend_state */
452 struct r600_command_buffer *cb;
453 };
454
455 struct r600_scissor_state
456 {
457 struct r600_atom atom;
458 struct pipe_scissor_state scissor;
459 bool enable; /* r6xx only */
460 };
461
462 struct r600_fetch_shader {
463 struct r600_resource *buffer;
464 unsigned offset;
465 };
466
467 struct r600_shader_state {
468 struct r600_atom atom;
469 struct r600_pipe_shader_selector *shader;
470 };
471
472 struct r600_query_buffer {
473 /* The buffer where query results are stored. */
474 struct r600_resource *buf;
475 /* Offset of the next free result after current query data */
476 unsigned results_end;
477 /* If a query buffer is full, a new buffer is created and the old one
478 * is put in here. When we calculate the result, we sum up the samples
479 * from all buffers. */
480 struct r600_query_buffer *previous;
481 };
482
483 struct r600_query {
484 /* The query buffer and how many results are in it. */
485 struct r600_query_buffer buffer;
486 /* The type of query */
487 unsigned type;
488 /* Size of the result in memory for both begin_query and end_query,
489 * this can be one or two numbers, or it could even be a size of a structure. */
490 unsigned result_size;
491 /* The number of dwords for begin_query or end_query. */
492 unsigned num_cs_dw;
493 /* linked list of queries */
494 struct list_head list;
495 /* for custom non-GPU queries */
496 uint64_t begin_result;
497 uint64_t end_result;
498 };
499
500 struct r600_so_target {
501 struct pipe_stream_output_target b;
502
503 /* The buffer where BUFFER_FILLED_SIZE is stored. */
504 struct r600_resource *buf_filled_size;
505 unsigned buf_filled_size_offset;
506
507 unsigned stride_in_dw;
508 unsigned so_index;
509 };
510
511 struct r600_streamout {
512 struct r600_atom begin_atom;
513 bool begin_emitted;
514 unsigned num_dw_for_end;
515
516 unsigned enabled_mask;
517 unsigned num_targets;
518 struct r600_so_target *targets[PIPE_MAX_SO_BUFFERS];
519
520 unsigned append_bitmask;
521 bool suspended;
522 };
523
524 struct r600_ring {
525 struct radeon_winsys_cs *cs;
526 bool flushing;
527 void (*flush)(void *ctx, unsigned flags);
528 };
529
530 struct r600_rings {
531 struct r600_ring gfx;
532 struct r600_ring dma;
533 };
534
535 struct r600_context {
536 struct pipe_context context;
537 struct r600_screen *screen;
538 struct radeon_winsys *ws;
539 struct r600_rings rings;
540 struct blitter_context *blitter;
541 struct u_upload_mgr *uploader;
542 struct u_suballocator *allocator_so_filled_size;
543 struct u_suballocator *allocator_fetch_shader;
544 struct util_slab_mempool pool_transfers;
545
546 /* Hardware info. */
547 enum radeon_family family;
548 enum chip_class chip_class;
549 boolean has_vertex_cache;
550 boolean keep_tiling_flags;
551 unsigned default_ps_gprs, default_vs_gprs;
552 unsigned r6xx_num_clause_temp_gprs;
553 unsigned backend_mask;
554 unsigned max_db; /* for OQ */
555
556 /* current unaccounted memory usage */
557 uint64_t vram;
558 uint64_t gtt;
559
560 /* Miscellaneous state objects. */
561 void *custom_dsa_flush;
562 void *custom_blend_resolve;
563 void *custom_blend_decompress;
564 void *custom_blend_fmask_decompress;
565 /* With rasterizer discard, there doesn't have to be a pixel shader.
566 * In that case, we bind this one: */
567 void *dummy_pixel_shader;
568 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
569 * bug where valid CMASK and FMASK are required to be present to avoid
570 * a hardlock in certain operations but aren't actually used
571 * for anything useful. */
572 struct r600_resource *dummy_fmask;
573 struct r600_resource *dummy_cmask;
574
575 /* State binding slots are here. */
576 struct r600_atom *atoms[R600_NUM_ATOMS];
577 /* States for CS initialization. */
578 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
579 /** Compute specific registers initializations. The start_cs_cmd atom
580 * must be emitted before start_compute_cs_cmd. */
581 struct r600_command_buffer start_compute_cs_cmd;
582 /* Register states. */
583 struct r600_alphatest_state alphatest_state;
584 struct r600_cso_state blend_state;
585 struct r600_blend_color blend_color;
586 struct r600_cb_misc_state cb_misc_state;
587 struct r600_clip_misc_state clip_misc_state;
588 struct r600_clip_state clip_state;
589 struct r600_db_misc_state db_misc_state;
590 struct r600_db_state db_state;
591 struct r600_cso_state dsa_state;
592 struct r600_framebuffer framebuffer;
593 struct r600_poly_offset_state poly_offset_state;
594 struct r600_cso_state rasterizer_state;
595 struct r600_sample_mask sample_mask;
596 struct r600_scissor_state scissor;
597 struct r600_seamless_cube_map seamless_cube_map;
598 struct r600_config_state config_state;
599 struct r600_stencil_ref_state stencil_ref;
600 struct r600_vgt_state vgt_state;
601 struct r600_viewport_state viewport;
602 /* Shaders and shader resources. */
603 struct r600_cso_state vertex_fetch_shader;
604 struct r600_shader_state vertex_shader;
605 struct r600_shader_state pixel_shader;
606 struct r600_cs_shader_state cs_shader_state;
607 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
608 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
609 /** Vertex buffers for fetch shaders */
610 struct r600_vertexbuf_state vertex_buffer_state;
611 /** Vertex buffers for compute shaders */
612 struct r600_vertexbuf_state cs_vertex_buffer_state;
613 struct r600_streamout streamout;
614
615 /* Additional context states. */
616 unsigned flags;
617 unsigned compute_cb_target_mask;
618 struct r600_pipe_shader_selector *ps_shader;
619 struct r600_pipe_shader_selector *vs_shader;
620 struct r600_rasterizer_state *rasterizer;
621 bool alpha_to_one;
622 bool force_blend_disable;
623 boolean dual_src_blend;
624 unsigned zwritemask;
625
626 /* Index buffer. */
627 struct pipe_index_buffer index_buffer;
628
629 /* Last draw state (-1 = unset). */
630 int last_primitive_type; /* Last primitive type used in draw_vbo. */
631 int last_start_instance;
632
633 /* Queries. */
634 /* The list of active queries. Only one query of each type can be active. */
635 int num_occlusion_queries;
636 int num_pipelinestat_queries;
637 /* Keep track of non-timer queries, because they should be suspended
638 * during context flushing.
639 * The timer queries (TIME_ELAPSED) shouldn't be suspended. */
640 struct list_head active_nontimer_queries;
641 unsigned num_cs_dw_nontimer_queries_suspend;
642 /* If queries have been suspended. */
643 bool nontimer_queries_suspended;
644 unsigned num_draw_calls;
645
646 /* Render condition. */
647 struct pipe_query *current_render_cond;
648 unsigned current_render_cond_mode;
649 boolean predicate_drawing;
650
651 void *sb_context;
652 struct r600_isa *isa;
653 };
654
655 static INLINE void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
656 struct r600_command_buffer *cb)
657 {
658 assert(cs->cdw + cb->num_dw <= RADEON_MAX_CMDBUF_DWORDS);
659 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->num_dw);
660 cs->cdw += cb->num_dw;
661 }
662
663 void r600_trace_emit(struct r600_context *rctx);
664
665 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
666 {
667 atom->emit(rctx, atom);
668 atom->dirty = false;
669 if (rctx->screen->trace_bo) {
670 r600_trace_emit(rctx);
671 }
672 }
673
674 static INLINE void r600_set_cso_state(struct r600_cso_state *state, void *cso)
675 {
676 state->cso = cso;
677 state->atom.dirty = cso != NULL;
678 }
679
680 static INLINE void r600_set_cso_state_with_cb(struct r600_cso_state *state, void *cso,
681 struct r600_command_buffer *cb)
682 {
683 state->cb = cb;
684 state->atom.num_dw = cb->num_dw;
685 r600_set_cso_state(state, cso);
686 }
687
688 /* compute_memory_pool.c */
689 struct compute_memory_pool;
690 void compute_memory_pool_delete(struct compute_memory_pool* pool);
691 struct compute_memory_pool* compute_memory_pool_new(
692 struct r600_screen *rscreen);
693
694 /* evergreen_state.c */
695 struct pipe_sampler_view *
696 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
697 struct pipe_resource *texture,
698 const struct pipe_sampler_view *state,
699 unsigned width0, unsigned height0);
700 void evergreen_init_common_regs(struct r600_command_buffer *cb,
701 enum chip_class ctx_chip_class,
702 enum radeon_family ctx_family,
703 int ctx_drm_minor);
704 void cayman_init_common_regs(struct r600_command_buffer *cb,
705 enum chip_class ctx_chip_class,
706 enum radeon_family ctx_family,
707 int ctx_drm_minor);
708
709 void evergreen_init_state_functions(struct r600_context *rctx);
710 void evergreen_init_atom_start_cs(struct r600_context *rctx);
711 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
712 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
713 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
714 void *evergreen_create_resolve_blend(struct r600_context *rctx);
715 void *evergreen_create_decompress_blend(struct r600_context *rctx);
716 void *evergreen_create_fmask_decompress_blend(struct r600_context *rctx);
717 boolean evergreen_is_format_supported(struct pipe_screen *screen,
718 enum pipe_format format,
719 enum pipe_texture_target target,
720 unsigned sample_count,
721 unsigned usage);
722 void evergreen_init_color_surface(struct r600_context *rctx,
723 struct r600_surface *surf);
724 void evergreen_init_color_surface_rat(struct r600_context *rctx,
725 struct r600_surface *surf);
726 void evergreen_update_db_shader_control(struct r600_context * rctx);
727
728 /* r600_blit.c */
729 void r600_copy_buffer(struct pipe_context *ctx, struct pipe_resource *dst, unsigned dstx,
730 struct pipe_resource *src, const struct pipe_box *src_box);
731 void r600_screen_clear_buffer(struct r600_screen *rscreen, struct pipe_resource *dst,
732 unsigned offset, unsigned size, unsigned char value);
733 void r600_init_blit_functions(struct r600_context *rctx);
734 void r600_blit_decompress_depth(struct pipe_context *ctx,
735 struct r600_texture *texture,
736 struct r600_texture *staging,
737 unsigned first_level, unsigned last_level,
738 unsigned first_layer, unsigned last_layer,
739 unsigned first_sample, unsigned last_sample);
740 void r600_decompress_depth_textures(struct r600_context *rctx,
741 struct r600_samplerview_state *textures);
742 void r600_decompress_color_textures(struct r600_context *rctx,
743 struct r600_samplerview_state *textures);
744
745 /* r600_buffer.c */
746 bool r600_init_resource(struct r600_screen *rscreen,
747 struct r600_resource *res,
748 unsigned size, unsigned alignment,
749 bool use_reusable_pool, unsigned usage);
750 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
751 const struct pipe_resource *templ,
752 unsigned alignment);
753
754 /* r600_pipe.c */
755 boolean r600_rings_is_buffer_referenced(struct r600_context *ctx,
756 struct radeon_winsys_cs_handle *buf,
757 enum radeon_bo_usage usage);
758 void *r600_buffer_mmap_sync_with_rings(struct r600_context *ctx,
759 struct r600_resource *resource,
760 unsigned usage);
761 const char * r600_llvm_gpu_string(enum radeon_family family);
762
763
764 /* r600_query.c */
765 void r600_init_query_functions(struct r600_context *rctx);
766 void r600_suspend_nontimer_queries(struct r600_context *ctx);
767 void r600_resume_nontimer_queries(struct r600_context *ctx);
768
769 /* r600_resource.c */
770 void r600_init_context_resource_functions(struct r600_context *r600);
771
772 /* r600_shader.c */
773 int r600_pipe_shader_create(struct pipe_context *ctx,
774 struct r600_pipe_shader *shader,
775 struct r600_shader_key key);
776 #ifdef HAVE_OPENCL
777 int r600_compute_shader_create(struct pipe_context * ctx,
778 LLVMModuleRef mod, struct r600_bytecode * bytecode);
779 #endif
780 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
781
782 /* r600_state.c */
783 struct pipe_sampler_view *
784 r600_create_sampler_view_custom(struct pipe_context *ctx,
785 struct pipe_resource *texture,
786 const struct pipe_sampler_view *state,
787 unsigned width_first_level, unsigned height_first_level);
788 void r600_init_state_functions(struct r600_context *rctx);
789 void r600_init_atom_start_cs(struct r600_context *rctx);
790 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
791 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
792 void *r600_create_db_flush_dsa(struct r600_context *rctx);
793 void *r600_create_resolve_blend(struct r600_context *rctx);
794 void *r700_create_resolve_blend(struct r600_context *rctx);
795 void *r600_create_decompress_blend(struct r600_context *rctx);
796 bool r600_adjust_gprs(struct r600_context *rctx);
797 boolean r600_is_format_supported(struct pipe_screen *screen,
798 enum pipe_format format,
799 enum pipe_texture_target target,
800 unsigned sample_count,
801 unsigned usage);
802 void r600_update_db_shader_control(struct r600_context * rctx);
803
804 /* r600_texture.c */
805 void r600_init_screen_texture_functions(struct pipe_screen *screen);
806 void r600_init_surface_functions(struct r600_context *r600);
807 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
808 const unsigned char *swizzle_view,
809 uint32_t *word4_p, uint32_t *yuv_format_p);
810 unsigned r600_texture_get_offset(struct r600_texture *rtex,
811 unsigned level, unsigned layer);
812 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
813 struct pipe_resource *texture,
814 const struct pipe_surface *templ,
815 unsigned width, unsigned height);
816
817 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
818 const unsigned char *swizzle_view,
819 boolean vtx);
820
821 /* r600_hw_context.c */
822 void r600_get_backend_mask(struct r600_context *ctx);
823 void r600_context_flush(struct r600_context *ctx, unsigned flags);
824 void r600_begin_new_cs(struct r600_context *ctx);
825 void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence,
826 unsigned offset, unsigned value);
827 void r600_flush_emit(struct r600_context *ctx);
828 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
829 void r600_need_dma_space(struct r600_context *ctx, unsigned num_dw);
830 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
831 struct pipe_resource *dst, uint64_t dst_offset,
832 struct pipe_resource *src, uint64_t src_offset,
833 unsigned size);
834 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
835 struct pipe_resource *dst, uint64_t offset,
836 unsigned size, uint32_t clear_value);
837 void r600_dma_copy(struct r600_context *rctx,
838 struct pipe_resource *dst,
839 struct pipe_resource *src,
840 uint64_t dst_offset,
841 uint64_t src_offset,
842 uint64_t size);
843 boolean r600_dma_blit(struct pipe_context *ctx,
844 struct pipe_resource *dst,
845 unsigned dst_level,
846 unsigned dst_x, unsigned dst_y, unsigned dst_z,
847 struct pipe_resource *src,
848 unsigned src_level,
849 const struct pipe_box *src_box);
850 void r600_emit_streamout_begin(struct r600_context *ctx, struct r600_atom *atom);
851 void r600_emit_streamout_end(struct r600_context *ctx);
852
853 /*
854 * evergreen_hw_context.c
855 */
856 void evergreen_flush_vgt_streamout(struct r600_context *ctx);
857 void evergreen_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit);
858 void evergreen_dma_copy(struct r600_context *rctx,
859 struct pipe_resource *dst,
860 struct pipe_resource *src,
861 uint64_t dst_offset,
862 uint64_t src_offset,
863 uint64_t size);
864 boolean evergreen_dma_blit(struct pipe_context *ctx,
865 struct pipe_resource *dst,
866 unsigned dst_level,
867 unsigned dst_x, unsigned dst_y, unsigned dst_z,
868 struct pipe_resource *src,
869 unsigned src_level,
870 const struct pipe_box *src_box);
871
872 /* r600_state_common.c */
873 void r600_init_common_state_functions(struct r600_context *rctx);
874 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
875 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
876 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
877 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
878 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
879 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
880 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom);
881 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
882 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
883 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
884 unsigned num_dw);
885 void r600_vertex_buffers_dirty(struct r600_context *rctx);
886 void r600_sampler_views_dirty(struct r600_context *rctx,
887 struct r600_samplerview_state *state);
888 void r600_sampler_states_dirty(struct r600_context *rctx,
889 struct r600_sampler_states *state);
890 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
891 void r600_streamout_buffers_dirty(struct r600_context *rctx);
892 void r600_draw_rectangle(struct blitter_context *blitter,
893 int x1, int y1, int x2, int y2, float depth,
894 enum blitter_attrib_type type, const union pipe_color_union *attrib);
895 uint32_t r600_translate_stencil_op(int s_op);
896 uint32_t r600_translate_fill(uint32_t func);
897 unsigned r600_tex_wrap(unsigned wrap);
898 unsigned r600_tex_filter(unsigned filter);
899 unsigned r600_tex_mipfilter(unsigned filter);
900 unsigned r600_tex_compare(unsigned compare);
901 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
902
903 /* r600_uvd.c */
904 struct pipe_video_decoder *r600_uvd_create_decoder(struct pipe_context *context,
905 enum pipe_video_profile profile,
906 enum pipe_video_entrypoint entrypoint,
907 enum pipe_video_chroma_format chroma_format,
908 unsigned width, unsigned height,
909 unsigned max_references, bool expect_chunked_decode);
910
911 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
912 const struct pipe_video_buffer *tmpl);
913
914 int r600_uvd_get_video_param(struct pipe_screen *screen,
915 enum pipe_video_profile profile,
916 enum pipe_video_cap param);
917
918 /*
919 * Helpers for building command buffers
920 */
921
922 #define PKT3_SET_CONFIG_REG 0x68
923 #define PKT3_SET_CONTEXT_REG 0x69
924 #define PKT3_SET_CTL_CONST 0x6F
925 #define PKT3_SET_LOOP_CONST 0x6C
926
927 #define R600_CONFIG_REG_OFFSET 0x08000
928 #define R600_CONTEXT_REG_OFFSET 0x28000
929 #define R600_CTL_CONST_OFFSET 0x3CFF0
930 #define R600_LOOP_CONST_OFFSET 0X0003E200
931 #define EG_LOOP_CONST_OFFSET 0x0003A200
932
933 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
934 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
935 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
936 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
937 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
938
939 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
940
941 /*Evergreen Compute packet3*/
942 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
943
944 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
945 {
946 cb->buf[cb->num_dw++] = value;
947 }
948
949 static INLINE void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
950 {
951 assert(cb->num_dw+num <= cb->max_num_dw);
952 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
953 cb->num_dw += num;
954 }
955
956 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
957 {
958 assert(reg < R600_CONTEXT_REG_OFFSET);
959 assert(cb->num_dw+2+num <= cb->max_num_dw);
960 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
961 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
962 }
963
964 /**
965 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
966 * shaders.
967 */
968 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
969 {
970 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
971 assert(cb->num_dw+2+num <= cb->max_num_dw);
972 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
973 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
974 }
975
976 /**
977 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
978 * shaders.
979 */
980 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
981 {
982 assert(reg >= R600_CTL_CONST_OFFSET);
983 assert(cb->num_dw+2+num <= cb->max_num_dw);
984 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
985 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
986 }
987
988 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
989 {
990 assert(reg >= R600_LOOP_CONST_OFFSET);
991 assert(cb->num_dw+2+num <= cb->max_num_dw);
992 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
993 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
994 }
995
996 /**
997 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
998 * shaders.
999 */
1000 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
1001 {
1002 assert(reg >= EG_LOOP_CONST_OFFSET);
1003 assert(cb->num_dw+2+num <= cb->max_num_dw);
1004 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
1005 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
1006 }
1007
1008 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
1009 {
1010 r600_store_config_reg_seq(cb, reg, 1);
1011 r600_store_value(cb, value);
1012 }
1013
1014 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
1015 {
1016 r600_store_context_reg_seq(cb, reg, 1);
1017 r600_store_value(cb, value);
1018 }
1019
1020 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
1021 {
1022 r600_store_ctl_const_seq(cb, reg, 1);
1023 r600_store_value(cb, value);
1024 }
1025
1026 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
1027 {
1028 r600_store_loop_const_seq(cb, reg, 1);
1029 r600_store_value(cb, value);
1030 }
1031
1032 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
1033 {
1034 eg_store_loop_const_seq(cb, reg, 1);
1035 r600_store_value(cb, value);
1036 }
1037
1038 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
1039 void r600_release_command_buffer(struct r600_command_buffer *cb);
1040
1041 /*
1042 * Helpers for emitting state into a command stream directly.
1043 */
1044 static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx,
1045 struct r600_ring *ring,
1046 struct r600_resource *rbo,
1047 enum radeon_bo_usage usage)
1048 {
1049 assert(usage);
1050 /* make sure that all previous ring use are flushed so everything
1051 * look serialized from driver pov
1052 */
1053 if (!ring->flushing) {
1054 if (ring == &ctx->rings.gfx) {
1055 if (ctx->rings.dma.cs) {
1056 /* flush dma ring */
1057 ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
1058 }
1059 } else {
1060 /* flush gfx ring */
1061 ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
1062 }
1063 }
1064 return ctx->ws->cs_add_reloc(ring->cs, rbo->cs_buf, usage, rbo->domains) * 4;
1065 }
1066
1067 static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
1068 {
1069 cs->buf[cs->cdw++] = value;
1070 }
1071
1072 static INLINE void r600_write_array(struct radeon_winsys_cs *cs, unsigned num, unsigned *ptr)
1073 {
1074 assert(cs->cdw+num <= RADEON_MAX_CMDBUF_DWORDS);
1075 memcpy(&cs->buf[cs->cdw], ptr, num * sizeof(ptr[0]));
1076 cs->cdw += num;
1077 }
1078
1079 static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
1080 {
1081 assert(reg < R600_CONTEXT_REG_OFFSET);
1082 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
1083 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
1084 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
1085 }
1086
1087 static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
1088 {
1089 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
1090 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
1091 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
1092 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
1093 }
1094
1095 static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
1096 {
1097 r600_write_context_reg_seq(cs, reg, num);
1098 /* Set the compute bit on the packet header */
1099 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
1100 }
1101
1102 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
1103 {
1104 assert(reg >= R600_CTL_CONST_OFFSET);
1105 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
1106 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
1107 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
1108 }
1109
1110 static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
1111 {
1112 r600_write_config_reg_seq(cs, reg, 1);
1113 r600_write_value(cs, value);
1114 }
1115
1116 static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
1117 {
1118 r600_write_context_reg_seq(cs, reg, 1);
1119 r600_write_value(cs, value);
1120 }
1121
1122 static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
1123 {
1124 r600_write_compute_context_reg_seq(cs, reg, 1);
1125 r600_write_value(cs, value);
1126 }
1127
1128 static INLINE void r600_write_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
1129 {
1130 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
1131 r600_write_compute_context_reg(cs, reg, value);
1132 } else {
1133 r600_write_context_reg(cs, reg, value);
1134 }
1135
1136 }
1137 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
1138 {
1139 r600_write_ctl_const_seq(cs, reg, 1);
1140 r600_write_value(cs, value);
1141 }
1142
1143 /*
1144 * common helpers
1145 */
1146 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
1147 {
1148 return value * (1 << frac_bits);
1149 }
1150 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
1151
1152 static inline unsigned r600_tex_aniso_filter(unsigned filter)
1153 {
1154 if (filter <= 1) return 0;
1155 if (filter <= 2) return 1;
1156 if (filter <= 4) return 2;
1157 if (filter <= 8) return 3;
1158 /* else */ return 4;
1159 }
1160
1161 /* 12.4 fixed-point */
1162 static INLINE unsigned r600_pack_float_12p4(float x)
1163 {
1164 return x <= 0 ? 0 :
1165 x >= 4096 ? 0xffff : x * 16;
1166 }
1167
1168 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
1169 {
1170 struct r600_screen *rscreen = (struct r600_screen*)screen;
1171 struct r600_resource *rresource = (struct r600_resource*)resource;
1172
1173 return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
1174 }
1175
1176 static INLINE void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
1177 {
1178 struct r600_context *rctx = (struct r600_context *)ctx;
1179 struct r600_resource *rr = (struct r600_resource *)r;
1180
1181 if (r == NULL) {
1182 return;
1183 }
1184
1185 /*
1186 * The idea is to compute a gross estimate of memory requirement of
1187 * each draw call. After each draw call, memory will be precisely
1188 * accounted. So the uncertainty is only on the current draw call.
1189 * In practice this gave very good estimate (+/- 10% of the target
1190 * memory limit).
1191 */
1192 if (rr->domains & RADEON_DOMAIN_GTT) {
1193 rctx->gtt += rr->buf->size;
1194 }
1195 if (rr->domains & RADEON_DOMAIN_VRAM) {
1196 rctx->vram += rr->buf->size;
1197 }
1198 }
1199
1200 #endif