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r600g: merge the TXQ and BUFFER constant buffers (v1.1)
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "radeon/r600_pipe_common.h"
30 #include "radeon/r600_cs.h"
31
32 #include "r600_llvm.h"
33 #include "r600_public.h"
34
35 #include "util/u_suballoc.h"
36 #include "util/u_double_list.h"
37 #include "util/u_transfer.h"
38
39 #define R600_NUM_ATOMS 73
40
41 /* the number of CS dwords for flushing and drawing */
42 #define R600_MAX_FLUSH_CS_DWORDS 16
43 #define R600_MAX_DRAW_CS_DWORDS 40
44 #define R600_TRACE_CS_DWORDS 7
45
46 #define R600_MAX_USER_CONST_BUFFERS 13
47 #define R600_MAX_DRIVER_CONST_BUFFERS 3
48 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
49
50 /* start driver buffers after user buffers */
51 #define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
52 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
53 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
54 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
55 * of 16 const buffers.
56 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
57 *
58 * In order to support d3d 11 mandated minimum of 15 user const buffers
59 * we'd have to squash all use cases into one driver buffer.
60 */
61 #define R600_SAMPLE_POSITIONS_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
62
63 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
64
65 #ifdef PIPE_ARCH_BIG_ENDIAN
66 #define R600_BIG_ENDIAN 1
67 #else
68 #define R600_BIG_ENDIAN 0
69 #endif
70
71 struct r600_context;
72 struct r600_bytecode;
73 struct r600_shader_key;
74
75 /* This is an atom containing GPU commands that never change.
76 * This is supposed to be copied directly into the CS. */
77 struct r600_command_buffer {
78 uint32_t *buf;
79 unsigned num_dw;
80 unsigned max_num_dw;
81 unsigned pkt_flags;
82 };
83
84 struct r600_db_state {
85 struct r600_atom atom;
86 struct r600_surface *rsurf;
87 };
88
89 struct r600_db_misc_state {
90 struct r600_atom atom;
91 bool occlusion_query_enabled;
92 bool flush_depthstencil_through_cb;
93 bool flush_depthstencil_in_place;
94 bool copy_depth, copy_stencil;
95 unsigned copy_sample;
96 unsigned log_samples;
97 unsigned db_shader_control;
98 bool htile_clear;
99 };
100
101 struct r600_cb_misc_state {
102 struct r600_atom atom;
103 unsigned cb_color_control; /* this comes from blend state */
104 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
105 unsigned nr_cbufs;
106 unsigned nr_ps_color_outputs;
107 bool multiwrite;
108 bool dual_src_blend;
109 };
110
111 struct r600_clip_misc_state {
112 struct r600_atom atom;
113 unsigned pa_cl_clip_cntl; /* from rasterizer */
114 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
115 unsigned clip_plane_enable; /* from rasterizer */
116 unsigned clip_dist_write; /* from vertex shader */
117 boolean clip_disable; /* from vertex shader */
118 };
119
120 struct r600_alphatest_state {
121 struct r600_atom atom;
122 unsigned sx_alpha_test_control; /* this comes from dsa state */
123 unsigned sx_alpha_ref; /* this comes from dsa state */
124 bool bypass;
125 bool cb0_export_16bpc; /* from set_framebuffer_state */
126 };
127
128 struct r600_vgt_state {
129 struct r600_atom atom;
130 uint32_t vgt_multi_prim_ib_reset_en;
131 uint32_t vgt_multi_prim_ib_reset_indx;
132 uint32_t vgt_indx_offset;
133 };
134
135 struct r600_blend_color {
136 struct r600_atom atom;
137 struct pipe_blend_color state;
138 };
139
140 struct r600_clip_state {
141 struct r600_atom atom;
142 struct pipe_clip_state state;
143 };
144
145 struct r600_cs_shader_state {
146 struct r600_atom atom;
147 unsigned kernel_index;
148 unsigned pc;
149 struct r600_pipe_compute *shader;
150 };
151
152 struct r600_framebuffer {
153 struct r600_atom atom;
154 struct pipe_framebuffer_state state;
155 unsigned compressed_cb_mask;
156 unsigned nr_samples;
157 bool export_16bpc;
158 bool cb0_is_integer;
159 bool is_msaa_resolve;
160 };
161
162 struct r600_sample_mask {
163 struct r600_atom atom;
164 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
165 };
166
167 struct r600_config_state {
168 struct r600_atom atom;
169 unsigned sq_gpr_resource_mgmt_1;
170 unsigned sq_gpr_resource_mgmt_2;
171 };
172
173 struct r600_stencil_ref
174 {
175 ubyte ref_value[2];
176 ubyte valuemask[2];
177 ubyte writemask[2];
178 };
179
180 struct r600_stencil_ref_state {
181 struct r600_atom atom;
182 struct r600_stencil_ref state;
183 struct pipe_stencil_ref pipe_state;
184 };
185
186 struct r600_viewport_state {
187 struct r600_atom atom;
188 struct pipe_viewport_state state;
189 int idx;
190 };
191
192 struct r600_shader_stages_state {
193 struct r600_atom atom;
194 unsigned geom_enable;
195 };
196
197 struct r600_gs_rings_state {
198 struct r600_atom atom;
199 unsigned enable;
200 struct pipe_constant_buffer esgs_ring;
201 struct pipe_constant_buffer gsvs_ring;
202 };
203
204 /* This must start from 16. */
205 /* features */
206 #define DBG_LLVM (1 << 29)
207 #define DBG_NO_CP_DMA (1 << 30)
208 /* shader backend */
209 #define DBG_NO_SB (1 << 21)
210 #define DBG_SB_CS (1 << 22)
211 #define DBG_SB_DRY_RUN (1 << 23)
212 #define DBG_SB_STAT (1 << 24)
213 #define DBG_SB_DUMP (1 << 25)
214 #define DBG_SB_NO_FALLBACK (1 << 26)
215 #define DBG_SB_DISASM (1 << 27)
216 #define DBG_SB_SAFEMATH (1 << 28)
217
218 struct r600_screen {
219 struct r600_common_screen b;
220 bool has_msaa;
221 bool has_compressed_msaa_texturing;
222
223 /*for compute global memory binding, we allocate stuff here, instead of
224 * buffers.
225 * XXX: Not sure if this is the best place for global_pool. Also,
226 * it's not thread safe, so it won't work with multiple contexts. */
227 struct compute_memory_pool *global_pool;
228 };
229
230 struct r600_pipe_sampler_view {
231 struct pipe_sampler_view base;
232 struct list_head list;
233 struct r600_resource *tex_resource;
234 uint32_t tex_resource_words[8];
235 bool skip_mip_address_reloc;
236 };
237
238 struct r600_rasterizer_state {
239 struct r600_command_buffer buffer;
240 boolean flatshade;
241 boolean two_side;
242 unsigned sprite_coord_enable;
243 unsigned clip_plane_enable;
244 unsigned pa_sc_line_stipple;
245 unsigned pa_cl_clip_cntl;
246 unsigned pa_su_sc_mode_cntl;
247 float offset_units;
248 float offset_scale;
249 bool offset_enable;
250 bool scissor_enable;
251 bool multisample_enable;
252 };
253
254 struct r600_poly_offset_state {
255 struct r600_atom atom;
256 enum pipe_format zs_format;
257 float offset_units;
258 float offset_scale;
259 };
260
261 struct r600_blend_state {
262 struct r600_command_buffer buffer;
263 struct r600_command_buffer buffer_no_blend;
264 unsigned cb_target_mask;
265 unsigned cb_color_control;
266 unsigned cb_color_control_no_blend;
267 bool dual_src_blend;
268 bool alpha_to_one;
269 };
270
271 struct r600_dsa_state {
272 struct r600_command_buffer buffer;
273 unsigned alpha_ref;
274 ubyte valuemask[2];
275 ubyte writemask[2];
276 unsigned zwritemask;
277 unsigned sx_alpha_test_control;
278 };
279
280 struct r600_pipe_shader;
281
282 struct r600_pipe_shader_selector {
283 struct r600_pipe_shader *current;
284
285 struct tgsi_token *tokens;
286 struct pipe_stream_output_info so;
287
288 unsigned num_shaders;
289
290 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
291 unsigned type;
292
293 unsigned nr_ps_max_color_exports;
294 };
295
296 struct r600_pipe_sampler_state {
297 uint32_t tex_sampler_words[3];
298 union pipe_color_union border_color;
299 bool border_color_use;
300 bool seamless_cube_map;
301 };
302
303 /* needed for blitter save */
304 #define NUM_TEX_UNITS 16
305
306 struct r600_seamless_cube_map {
307 struct r600_atom atom;
308 bool enabled;
309 };
310
311 struct r600_samplerview_state {
312 struct r600_atom atom;
313 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
314 uint32_t enabled_mask;
315 uint32_t dirty_mask;
316 uint32_t compressed_depthtex_mask; /* which textures are depth */
317 uint32_t compressed_colortex_mask;
318 boolean dirty_txq_constants;
319 boolean dirty_buffer_constants;
320 };
321
322 struct r600_sampler_states {
323 struct r600_atom atom;
324 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
325 uint32_t enabled_mask;
326 uint32_t dirty_mask;
327 uint32_t has_bordercolor_mask; /* which states contain the border color */
328 };
329
330 struct r600_textures_info {
331 struct r600_samplerview_state views;
332 struct r600_sampler_states states;
333 bool is_array_sampler[NUM_TEX_UNITS];
334
335 /* cube array txq workaround */
336 uint32_t *txq_constants;
337 /* buffer related workarounds */
338 uint32_t *buffer_constants;
339 };
340
341 struct r600_constbuf_state
342 {
343 struct r600_atom atom;
344 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
345 uint32_t enabled_mask;
346 uint32_t dirty_mask;
347 };
348
349 struct r600_vertexbuf_state
350 {
351 struct r600_atom atom;
352 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
353 uint32_t enabled_mask; /* non-NULL buffers */
354 uint32_t dirty_mask;
355 };
356
357 /* CSO (constant state object, in other words, immutable state). */
358 struct r600_cso_state
359 {
360 struct r600_atom atom;
361 void *cso; /* e.g. r600_blend_state */
362 struct r600_command_buffer *cb;
363 };
364
365 struct r600_scissor_state
366 {
367 struct r600_atom atom;
368 struct pipe_scissor_state scissor;
369 bool enable; /* r6xx only */
370 int idx;
371 };
372
373 struct r600_fetch_shader {
374 struct r600_resource *buffer;
375 unsigned offset;
376 };
377
378 struct r600_shader_state {
379 struct r600_atom atom;
380 struct r600_pipe_shader *shader;
381 };
382
383 struct r600_context {
384 struct r600_common_context b;
385 struct r600_screen *screen;
386 struct blitter_context *blitter;
387 struct u_suballocator *allocator_fetch_shader;
388
389 /* Hardware info. */
390 boolean has_vertex_cache;
391 boolean keep_tiling_flags;
392 unsigned default_ps_gprs, default_vs_gprs;
393 unsigned r6xx_num_clause_temp_gprs;
394
395 /* Miscellaneous state objects. */
396 void *custom_dsa_flush;
397 void *custom_blend_resolve;
398 void *custom_blend_decompress;
399 void *custom_blend_fastclear;
400 /* With rasterizer discard, there doesn't have to be a pixel shader.
401 * In that case, we bind this one: */
402 void *dummy_pixel_shader;
403 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
404 * bug where valid CMASK and FMASK are required to be present to avoid
405 * a hardlock in certain operations but aren't actually used
406 * for anything useful. */
407 struct r600_resource *dummy_fmask;
408 struct r600_resource *dummy_cmask;
409
410 /* State binding slots are here. */
411 struct r600_atom *atoms[R600_NUM_ATOMS];
412 /* States for CS initialization. */
413 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
414 /** Compute specific registers initializations. The start_cs_cmd atom
415 * must be emitted before start_compute_cs_cmd. */
416 struct r600_command_buffer start_compute_cs_cmd;
417 /* Register states. */
418 struct r600_alphatest_state alphatest_state;
419 struct r600_cso_state blend_state;
420 struct r600_blend_color blend_color;
421 struct r600_cb_misc_state cb_misc_state;
422 struct r600_clip_misc_state clip_misc_state;
423 struct r600_clip_state clip_state;
424 struct r600_db_misc_state db_misc_state;
425 struct r600_db_state db_state;
426 struct r600_cso_state dsa_state;
427 struct r600_framebuffer framebuffer;
428 struct r600_poly_offset_state poly_offset_state;
429 struct r600_cso_state rasterizer_state;
430 struct r600_sample_mask sample_mask;
431 struct r600_scissor_state scissor[16];
432 struct r600_seamless_cube_map seamless_cube_map;
433 struct r600_config_state config_state;
434 struct r600_stencil_ref_state stencil_ref;
435 struct r600_vgt_state vgt_state;
436 struct r600_viewport_state viewport[16];
437 /* Shaders and shader resources. */
438 struct r600_cso_state vertex_fetch_shader;
439 struct r600_shader_state vertex_shader;
440 struct r600_shader_state pixel_shader;
441 struct r600_shader_state geometry_shader;
442 struct r600_shader_state export_shader;
443 struct r600_cs_shader_state cs_shader_state;
444 struct r600_shader_stages_state shader_stages;
445 struct r600_gs_rings_state gs_rings;
446 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
447 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
448 /** Vertex buffers for fetch shaders */
449 struct r600_vertexbuf_state vertex_buffer_state;
450 /** Vertex buffers for compute shaders */
451 struct r600_vertexbuf_state cs_vertex_buffer_state;
452
453 /* Additional context states. */
454 unsigned compute_cb_target_mask;
455 struct r600_pipe_shader_selector *ps_shader;
456 struct r600_pipe_shader_selector *vs_shader;
457 struct r600_pipe_shader_selector *gs_shader;
458 struct r600_rasterizer_state *rasterizer;
459 bool alpha_to_one;
460 bool force_blend_disable;
461 boolean dual_src_blend;
462 unsigned zwritemask;
463 int ps_iter_samples;
464
465 /* Index buffer. */
466 struct pipe_index_buffer index_buffer;
467
468 /* Last draw state (-1 = unset). */
469 int last_primitive_type; /* Last primitive type used in draw_vbo. */
470 int last_start_instance;
471
472 void *sb_context;
473 struct r600_isa *isa;
474 };
475
476 static INLINE void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
477 struct r600_command_buffer *cb)
478 {
479 assert(cs->cdw + cb->num_dw <= RADEON_MAX_CMDBUF_DWORDS);
480 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->num_dw);
481 cs->cdw += cb->num_dw;
482 }
483
484 void r600_trace_emit(struct r600_context *rctx);
485
486 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
487 {
488 atom->emit(&rctx->b, atom);
489 atom->dirty = false;
490 if (rctx->screen->b.trace_bo) {
491 r600_trace_emit(rctx);
492 }
493 }
494
495 static INLINE void r600_set_cso_state(struct r600_cso_state *state, void *cso)
496 {
497 state->cso = cso;
498 state->atom.dirty = cso != NULL;
499 }
500
501 static INLINE void r600_set_cso_state_with_cb(struct r600_cso_state *state, void *cso,
502 struct r600_command_buffer *cb)
503 {
504 state->cb = cb;
505 state->atom.num_dw = cb ? cb->num_dw : 0;
506 r600_set_cso_state(state, cso);
507 }
508
509 /* compute_memory_pool.c */
510 struct compute_memory_pool;
511 void compute_memory_pool_delete(struct compute_memory_pool* pool);
512 struct compute_memory_pool* compute_memory_pool_new(
513 struct r600_screen *rscreen);
514
515 /* evergreen_compute.c */
516 void evergreen_set_cs_sampler_view(struct pipe_context *ctx_,
517 unsigned start_slot, unsigned count,
518 struct pipe_sampler_view **views);
519
520 /* evergreen_state.c */
521 struct pipe_sampler_view *
522 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
523 struct pipe_resource *texture,
524 const struct pipe_sampler_view *state,
525 unsigned width0, unsigned height0,
526 unsigned force_level);
527 void evergreen_init_common_regs(struct r600_command_buffer *cb,
528 enum chip_class ctx_chip_class,
529 enum radeon_family ctx_family,
530 int ctx_drm_minor);
531 void cayman_init_common_regs(struct r600_command_buffer *cb,
532 enum chip_class ctx_chip_class,
533 enum radeon_family ctx_family,
534 int ctx_drm_minor);
535
536 void evergreen_init_state_functions(struct r600_context *rctx);
537 void evergreen_init_atom_start_cs(struct r600_context *rctx);
538 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
539 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
540 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
541 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
542 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
543 void *evergreen_create_resolve_blend(struct r600_context *rctx);
544 void *evergreen_create_decompress_blend(struct r600_context *rctx);
545 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
546 boolean evergreen_is_format_supported(struct pipe_screen *screen,
547 enum pipe_format format,
548 enum pipe_texture_target target,
549 unsigned sample_count,
550 unsigned usage);
551 void evergreen_init_color_surface(struct r600_context *rctx,
552 struct r600_surface *surf);
553 void evergreen_init_color_surface_rat(struct r600_context *rctx,
554 struct r600_surface *surf);
555 void evergreen_update_db_shader_control(struct r600_context * rctx);
556
557 /* r600_blit.c */
558 void r600_init_blit_functions(struct r600_context *rctx);
559 void r600_decompress_depth_textures(struct r600_context *rctx,
560 struct r600_samplerview_state *textures);
561 void r600_decompress_color_textures(struct r600_context *rctx,
562 struct r600_samplerview_state *textures);
563 void r600_resource_copy_region(struct pipe_context *ctx,
564 struct pipe_resource *dst,
565 unsigned dst_level,
566 unsigned dstx, unsigned dsty, unsigned dstz,
567 struct pipe_resource *src,
568 unsigned src_level,
569 const struct pipe_box *src_box);
570
571 /* r600_shader.c */
572 int r600_pipe_shader_create(struct pipe_context *ctx,
573 struct r600_pipe_shader *shader,
574 struct r600_shader_key key);
575
576 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
577
578 /* r600_state.c */
579 struct pipe_sampler_view *
580 r600_create_sampler_view_custom(struct pipe_context *ctx,
581 struct pipe_resource *texture,
582 const struct pipe_sampler_view *state,
583 unsigned width_first_level, unsigned height_first_level);
584 void r600_init_state_functions(struct r600_context *rctx);
585 void r600_init_atom_start_cs(struct r600_context *rctx);
586 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
587 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
588 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
589 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
590 void *r600_create_db_flush_dsa(struct r600_context *rctx);
591 void *r600_create_resolve_blend(struct r600_context *rctx);
592 void *r700_create_resolve_blend(struct r600_context *rctx);
593 void *r600_create_decompress_blend(struct r600_context *rctx);
594 bool r600_adjust_gprs(struct r600_context *rctx);
595 boolean r600_is_format_supported(struct pipe_screen *screen,
596 enum pipe_format format,
597 enum pipe_texture_target target,
598 unsigned sample_count,
599 unsigned usage);
600 void r600_update_db_shader_control(struct r600_context * rctx);
601
602 /* r600_hw_context.c */
603 void r600_context_gfx_flush(void *context, unsigned flags,
604 struct pipe_fence_handle **fence);
605 void r600_begin_new_cs(struct r600_context *ctx);
606 void r600_flush_emit(struct r600_context *ctx);
607 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
608 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
609 struct pipe_resource *dst, uint64_t dst_offset,
610 struct pipe_resource *src, uint64_t src_offset,
611 unsigned size);
612 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
613 struct pipe_resource *dst, uint64_t offset,
614 unsigned size, uint32_t clear_value);
615 void r600_dma_copy_buffer(struct r600_context *rctx,
616 struct pipe_resource *dst,
617 struct pipe_resource *src,
618 uint64_t dst_offset,
619 uint64_t src_offset,
620 uint64_t size);
621
622 /*
623 * evergreen_hw_context.c
624 */
625 void evergreen_dma_copy_buffer(struct r600_context *rctx,
626 struct pipe_resource *dst,
627 struct pipe_resource *src,
628 uint64_t dst_offset,
629 uint64_t src_offset,
630 uint64_t size);
631
632 /* r600_state_common.c */
633 void r600_init_common_state_functions(struct r600_context *rctx);
634 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
635 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
636 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
637 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
638 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
639 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
640 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom);
641 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
642 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
643 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
644 unsigned num_dw);
645 void r600_vertex_buffers_dirty(struct r600_context *rctx);
646 void r600_sampler_views_dirty(struct r600_context *rctx,
647 struct r600_samplerview_state *state);
648 void r600_sampler_states_dirty(struct r600_context *rctx,
649 struct r600_sampler_states *state);
650 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
651 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
652 uint32_t r600_translate_stencil_op(int s_op);
653 uint32_t r600_translate_fill(uint32_t func);
654 unsigned r600_tex_wrap(unsigned wrap);
655 unsigned r600_tex_filter(unsigned filter);
656 unsigned r600_tex_mipfilter(unsigned filter);
657 unsigned r600_tex_compare(unsigned compare);
658 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
659 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
660 struct pipe_resource *texture,
661 const struct pipe_surface *templ,
662 unsigned width, unsigned height);
663 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
664 const unsigned char *swizzle_view,
665 boolean vtx);
666 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
667 const unsigned char *swizzle_view,
668 uint32_t *word4_p, uint32_t *yuv_format_p);
669 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format);
670 uint32_t r600_colorformat_endian_swap(uint32_t colorformat);
671
672 /* r600_uvd.c */
673 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
674 const struct pipe_video_codec *decoder);
675
676 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
677 const struct pipe_video_buffer *tmpl);
678
679 /*
680 * Helpers for building command buffers
681 */
682
683 #define PKT3_SET_CONFIG_REG 0x68
684 #define PKT3_SET_CONTEXT_REG 0x69
685 #define PKT3_SET_CTL_CONST 0x6F
686 #define PKT3_SET_LOOP_CONST 0x6C
687
688 #define R600_CONFIG_REG_OFFSET 0x08000
689 #define R600_CONTEXT_REG_OFFSET 0x28000
690 #define R600_CTL_CONST_OFFSET 0x3CFF0
691 #define R600_LOOP_CONST_OFFSET 0X0003E200
692 #define EG_LOOP_CONST_OFFSET 0x0003A200
693
694 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
695 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
696 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
697 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
698 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
699
700 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
701
702 /*Evergreen Compute packet3*/
703 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
704
705 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
706 {
707 cb->buf[cb->num_dw++] = value;
708 }
709
710 static INLINE void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
711 {
712 assert(cb->num_dw+num <= cb->max_num_dw);
713 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
714 cb->num_dw += num;
715 }
716
717 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
718 {
719 assert(reg < R600_CONTEXT_REG_OFFSET);
720 assert(cb->num_dw+2+num <= cb->max_num_dw);
721 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
722 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
723 }
724
725 /**
726 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
727 * shaders.
728 */
729 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
730 {
731 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
732 assert(cb->num_dw+2+num <= cb->max_num_dw);
733 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
734 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
735 }
736
737 /**
738 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
739 * shaders.
740 */
741 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
742 {
743 assert(reg >= R600_CTL_CONST_OFFSET);
744 assert(cb->num_dw+2+num <= cb->max_num_dw);
745 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
746 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
747 }
748
749 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
750 {
751 assert(reg >= R600_LOOP_CONST_OFFSET);
752 assert(cb->num_dw+2+num <= cb->max_num_dw);
753 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
754 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
755 }
756
757 /**
758 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
759 * shaders.
760 */
761 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
762 {
763 assert(reg >= EG_LOOP_CONST_OFFSET);
764 assert(cb->num_dw+2+num <= cb->max_num_dw);
765 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
766 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
767 }
768
769 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
770 {
771 r600_store_config_reg_seq(cb, reg, 1);
772 r600_store_value(cb, value);
773 }
774
775 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
776 {
777 r600_store_context_reg_seq(cb, reg, 1);
778 r600_store_value(cb, value);
779 }
780
781 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
782 {
783 r600_store_ctl_const_seq(cb, reg, 1);
784 r600_store_value(cb, value);
785 }
786
787 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
788 {
789 r600_store_loop_const_seq(cb, reg, 1);
790 r600_store_value(cb, value);
791 }
792
793 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
794 {
795 eg_store_loop_const_seq(cb, reg, 1);
796 r600_store_value(cb, value);
797 }
798
799 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
800 void r600_release_command_buffer(struct r600_command_buffer *cb);
801
802 static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
803 {
804 r600_write_context_reg_seq(cs, reg, num);
805 /* Set the compute bit on the packet header */
806 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
807 }
808
809 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
810 {
811 assert(reg >= R600_CTL_CONST_OFFSET);
812 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
813 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
814 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
815 }
816
817 static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
818 {
819 r600_write_compute_context_reg_seq(cs, reg, 1);
820 radeon_emit(cs, value);
821 }
822
823 static INLINE void r600_write_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
824 {
825 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
826 r600_write_compute_context_reg(cs, reg, value);
827 } else {
828 r600_write_context_reg(cs, reg, value);
829 }
830 }
831
832 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
833 {
834 r600_write_ctl_const_seq(cs, reg, 1);
835 radeon_emit(cs, value);
836 }
837
838 /*
839 * common helpers
840 */
841 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
842 {
843 return value * (1 << frac_bits);
844 }
845 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
846
847 /* 12.4 fixed-point */
848 static INLINE unsigned r600_pack_float_12p4(float x)
849 {
850 return x <= 0 ? 0 :
851 x >= 4096 ? 0xffff : x * 16;
852 }
853
854 /* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */
855 static INLINE bool r600_can_read_depth(struct r600_texture *rtex)
856 {
857 return rtex->resource.b.b.nr_samples <= 1 &&
858 (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
859 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT);
860 }
861
862 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
863 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
864 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
865
866 static INLINE unsigned r600_conv_prim_to_gs_out(unsigned mode)
867 {
868 static const int prim_conv[] = {
869 V_028A6C_OUTPRIM_TYPE_POINTLIST,
870 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
871 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
872 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
873 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
874 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
875 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
876 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
877 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
878 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
879 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
880 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
881 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
882 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
883 V_028A6C_OUTPRIM_TYPE_TRISTRIP
884 };
885 assert(mode < Elements(prim_conv));
886
887 return prim_conv[mode];
888 }
889
890 #endif