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Merge branch 'gallium-userbuf'
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "util/u_slab.h"
30 #include "r600.h"
31 #include "r600_shader.h"
32 #include "r600_resource.h"
33
34 #define R600_MAX_CONST_BUFFERS 2
35 #define R600_MAX_CONST_BUFFER_SIZE 4096
36
37 #ifdef PIPE_ARCH_BIG_ENDIAN
38 #define R600_BIG_ENDIAN 1
39 #else
40 #define R600_BIG_ENDIAN 0
41 #endif
42
43 enum r600_atom_flags {
44 /* When set, atoms are added at the beginning of the dirty list
45 * instead of the end. */
46 EMIT_EARLY = (1 << 0)
47 };
48
49 /* This encapsulates a state or an operation which can emitted into the GPU
50 * command stream. It's not limited to states only, it can be used for anything
51 * that wants to write commands into the CS (e.g. cache flushes). */
52 struct r600_atom {
53 void (*emit)(struct r600_context *ctx, struct r600_atom *state);
54
55 unsigned num_dw;
56 enum r600_atom_flags flags;
57 bool dirty;
58
59 struct list_head head;
60 };
61
62 /* This is an atom containing GPU commands that never change.
63 * This is supposed to be copied directly into the CS. */
64 struct r600_command_buffer {
65 struct r600_atom atom;
66 uint32_t *buf;
67 unsigned max_num_dw;
68 };
69
70 struct r600_surface_sync_cmd {
71 struct r600_atom atom;
72 unsigned flush_flags; /* CP_COHER_CNTL */
73 };
74
75 struct r600_db_misc_state {
76 struct r600_atom atom;
77 bool occlusion_query_enabled;
78 bool flush_depthstencil_enabled;
79 };
80
81 enum r600_pipe_state_id {
82 R600_PIPE_STATE_BLEND = 0,
83 R600_PIPE_STATE_BLEND_COLOR,
84 R600_PIPE_STATE_CONFIG,
85 R600_PIPE_STATE_SEAMLESS_CUBEMAP,
86 R600_PIPE_STATE_CLIP,
87 R600_PIPE_STATE_SCISSOR,
88 R600_PIPE_STATE_VIEWPORT,
89 R600_PIPE_STATE_RASTERIZER,
90 R600_PIPE_STATE_VGT,
91 R600_PIPE_STATE_FRAMEBUFFER,
92 R600_PIPE_STATE_DSA,
93 R600_PIPE_STATE_STENCIL_REF,
94 R600_PIPE_STATE_PS_SHADER,
95 R600_PIPE_STATE_VS_SHADER,
96 R600_PIPE_STATE_CONSTANT,
97 R600_PIPE_STATE_SAMPLER,
98 R600_PIPE_STATE_RESOURCE,
99 R600_PIPE_STATE_POLYGON_OFFSET,
100 R600_PIPE_STATE_FETCH_SHADER,
101 R600_PIPE_NSTATES
102 };
103
104 struct r600_pipe_fences {
105 struct r600_resource *bo;
106 unsigned *data;
107 unsigned next_index;
108 /* linked list of preallocated blocks */
109 struct list_head blocks;
110 /* linked list of freed fences */
111 struct list_head pool;
112 pipe_mutex mutex;
113 };
114
115 struct r600_screen {
116 struct pipe_screen screen;
117 struct radeon_winsys *ws;
118 unsigned family;
119 enum chip_class chip_class;
120 struct radeon_info info;
121 struct r600_tiling_info tiling_info;
122 struct util_slab_mempool pool_buffers;
123 struct r600_pipe_fences fences;
124
125 unsigned num_contexts;
126 bool use_surface_alloc;
127 int glsl_feature_level;
128
129 /* for thread-safe write accessing to num_contexts */
130 pipe_mutex mutex_num_contexts;
131 };
132
133 struct r600_pipe_sampler_view {
134 struct pipe_sampler_view base;
135 struct r600_pipe_resource_state state;
136 };
137
138 struct r600_pipe_rasterizer {
139 struct r600_pipe_state rstate;
140 boolean flatshade;
141 boolean two_side;
142 unsigned sprite_coord_enable;
143 unsigned clip_plane_enable;
144 unsigned pa_sc_line_stipple;
145 unsigned pa_cl_clip_cntl;
146 float offset_units;
147 float offset_scale;
148 bool scissor_enable;
149 };
150
151 struct r600_pipe_blend {
152 struct r600_pipe_state rstate;
153 unsigned cb_target_mask;
154 unsigned cb_color_control;
155 bool dual_src_blend;
156 };
157
158 struct r600_pipe_dsa {
159 struct r600_pipe_state rstate;
160 unsigned alpha_ref;
161 ubyte valuemask[2];
162 ubyte writemask[2];
163 bool is_flush;
164 unsigned sx_alpha_test_control;
165 };
166
167 struct r600_vertex_element
168 {
169 unsigned count;
170 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS];
171 struct r600_resource *fetch_shader;
172 unsigned fs_size;
173 struct r600_pipe_state rstate;
174 };
175
176 struct r600_pipe_shader {
177 struct r600_shader shader;
178 struct r600_pipe_state rstate;
179 struct r600_resource *bo;
180 struct r600_resource *bo_fetch;
181 struct r600_vertex_element vertex_elements;
182 struct tgsi_token *tokens;
183 unsigned sprite_coord_enable;
184 unsigned flatshade;
185 unsigned pa_cl_vs_out_cntl;
186 unsigned ps_cb_shader_mask;
187 struct pipe_stream_output_info so;
188 };
189
190 struct r600_pipe_sampler_state {
191 struct r600_pipe_state rstate;
192 boolean seamless_cube_map;
193 };
194
195 /* needed for blitter save */
196 #define NUM_TEX_UNITS 16
197
198 struct r600_textures_info {
199 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
200 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS];
201 unsigned n_views;
202 unsigned n_samplers;
203 bool samplers_dirty;
204 bool is_array_sampler[NUM_TEX_UNITS];
205 };
206
207 struct r600_fence {
208 struct pipe_reference reference;
209 unsigned index; /* in the shared bo */
210 struct r600_resource *sleep_bo;
211 struct list_head head;
212 };
213
214 #define FENCE_BLOCK_SIZE 16
215
216 struct r600_fence_block {
217 struct r600_fence fences[FENCE_BLOCK_SIZE];
218 struct list_head head;
219 };
220
221 #define R600_CONSTANT_ARRAY_SIZE 256
222 #define R600_RESOURCE_ARRAY_SIZE 160
223
224 struct r600_stencil_ref
225 {
226 ubyte ref_value[2];
227 ubyte valuemask[2];
228 ubyte writemask[2];
229 };
230
231 struct r600_constbuf_state
232 {
233 struct r600_atom atom;
234 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
235 uint32_t enabled_mask;
236 uint32_t dirty_mask;
237 };
238
239 struct r600_context {
240 struct pipe_context context;
241 struct blitter_context *blitter;
242 enum radeon_family family;
243 enum chip_class chip_class;
244 boolean has_vertex_cache;
245 unsigned r6xx_num_clause_temp_gprs;
246 void *custom_dsa_flush;
247 struct r600_screen *screen;
248 struct radeon_winsys *ws;
249 struct r600_pipe_state *states[R600_PIPE_NSTATES];
250 struct r600_vertex_element *vertex_elements;
251 struct pipe_framebuffer_state framebuffer;
252 unsigned cb_target_mask;
253 unsigned fb_cb_shader_mask;
254 unsigned sx_alpha_test_control;
255 unsigned cb_shader_mask;
256 unsigned cb_color_control;
257 unsigned pa_sc_line_stipple;
258 unsigned pa_cl_clip_cntl;
259 /* for saving when using blitter */
260 struct pipe_stencil_ref stencil_ref;
261 struct pipe_viewport_state viewport;
262 struct pipe_clip_state clip;
263 struct r600_pipe_shader *ps_shader;
264 struct r600_pipe_shader *vs_shader;
265 struct r600_pipe_rasterizer *rasterizer;
266 struct r600_pipe_state vgt;
267 struct r600_pipe_state spi;
268 struct pipe_query *current_render_cond;
269 unsigned current_render_cond_mode;
270 struct pipe_query *saved_render_cond;
271 unsigned saved_render_cond_mode;
272 /* shader information */
273 boolean two_side;
274 unsigned sprite_coord_enable;
275 boolean export_16bpc;
276 unsigned alpha_ref;
277 boolean alpha_ref_dirty;
278 unsigned nr_cbufs;
279 struct r600_textures_info vs_samplers;
280 struct r600_textures_info ps_samplers;
281
282 struct u_upload_mgr *uploader;
283 struct util_slab_mempool pool_transfers;
284 boolean have_depth_texture, have_depth_fb;
285
286 unsigned default_ps_gprs, default_vs_gprs;
287
288 /* States based on r600_atom. */
289 struct list_head dirty_states;
290 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
291 struct r600_surface_sync_cmd surface_sync_cmd;
292 struct r600_atom r6xx_flush_and_inv_cmd;
293 struct r600_db_misc_state db_misc_state;
294 struct r600_atom vertex_buffer_state;
295 struct r600_constbuf_state vs_constbuf_state;
296 struct r600_constbuf_state ps_constbuf_state;
297
298 struct radeon_winsys_cs *cs;
299
300 struct r600_range *range;
301 unsigned nblocks;
302 struct r600_block **blocks;
303 struct list_head dirty;
304 struct list_head resource_dirty;
305 struct list_head enable_list;
306 unsigned pm4_dirty_cdwords;
307 unsigned ctx_pm4_ndwords;
308
309 /* The list of active queries. Only one query of each type can be active. */
310 int num_occlusion_queries;
311
312 /* Manage queries in two separate groups:
313 * The timer ones and the others (streamout, occlusion).
314 *
315 * We do this because we should only suspend non-timer queries for u_blitter,
316 * and later if the non-timer queries are suspended, the context flush should
317 * only suspend and resume the timer queries. */
318 struct list_head active_timer_queries;
319 unsigned num_cs_dw_timer_queries_suspend;
320 struct list_head active_nontimer_queries;
321 unsigned num_cs_dw_nontimer_queries_suspend;
322
323 unsigned num_cs_dw_streamout_end;
324
325 unsigned backend_mask;
326 unsigned max_db; /* for OQ */
327 unsigned flags;
328 boolean predicate_drawing;
329 struct r600_range ps_resources;
330 struct r600_range vs_resources;
331 int num_ps_resources, num_vs_resources;
332
333 unsigned num_so_targets;
334 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS];
335 boolean streamout_start;
336 unsigned streamout_append_bitmask;
337
338 /* There is no scissor enable bit on r6xx, so we must use a workaround.
339 * These track the current scissor state. */
340 bool scissor_enable;
341 struct pipe_scissor_state scissor_state;
342
343 /* With rasterizer discard, there doesn't have to be a pixel shader.
344 * In that case, we bind this one: */
345 void *dummy_pixel_shader;
346
347 boolean dual_src_blend;
348 unsigned color0_format;
349
350 /* Vertex and index buffers. */
351 bool vertex_buffers_dirty;
352 struct pipe_index_buffer index_buffer;
353 struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
354 unsigned nr_vertex_buffers;
355 };
356
357 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
358 {
359 atom->emit(rctx, atom);
360 atom->dirty = false;
361 if (atom->head.next && atom->head.prev)
362 LIST_DELINIT(&atom->head);
363 }
364
365 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
366 {
367 if (!state->dirty) {
368 if (state->flags & EMIT_EARLY) {
369 LIST_ADD(&state->head, &rctx->dirty_states);
370 } else {
371 LIST_ADDTAIL(&state->head, &rctx->dirty_states);
372 }
373 state->dirty = true;
374 }
375 }
376
377 /* evergreen_state.c */
378 void evergreen_init_state_functions(struct r600_context *rctx);
379 void evergreen_init_atom_start_cs(struct r600_context *rctx);
380 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
381 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
382 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
383 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
384 void evergreen_polygon_offset_update(struct r600_context *rctx);
385 boolean evergreen_is_format_supported(struct pipe_screen *screen,
386 enum pipe_format format,
387 enum pipe_texture_target target,
388 unsigned sample_count,
389 unsigned usage);
390
391 /* r600_blit.c */
392 void r600_init_blit_functions(struct r600_context *rctx);
393 void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
394 void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
395 void r600_flush_depth_textures(struct r600_context *rctx);
396
397 /* r600_buffer.c */
398 bool r600_init_resource(struct r600_screen *rscreen,
399 struct r600_resource *res,
400 unsigned size, unsigned alignment,
401 unsigned bind, unsigned usage);
402 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
403 const struct pipe_resource *templ);
404 struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
405 void *ptr, unsigned bytes,
406 unsigned bind);
407
408 /* r600_pipe.c */
409 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
410 unsigned flags);
411
412 /* r600_query.c */
413 void r600_init_query_functions(struct r600_context *rctx);
414 void r600_suspend_nontimer_queries(struct r600_context *ctx);
415 void r600_resume_nontimer_queries(struct r600_context *ctx);
416 void r600_suspend_timer_queries(struct r600_context *ctx);
417 void r600_resume_timer_queries(struct r600_context *ctx);
418
419 /* r600_resource.c */
420 void r600_init_context_resource_functions(struct r600_context *r600);
421
422 /* r600_shader.c */
423 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
424 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
425 int r600_find_vs_semantic_index(struct r600_shader *vs,
426 struct r600_shader *ps, int id);
427
428 /* r600_state.c */
429 void r600_set_scissor_state(struct r600_context *rctx,
430 const struct pipe_scissor_state *state);
431 void r600_update_sampler_states(struct r600_context *rctx);
432 void r600_init_state_functions(struct r600_context *rctx);
433 void r600_init_atom_start_cs(struct r600_context *rctx);
434 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
435 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
436 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
437 void *r600_create_db_flush_dsa(struct r600_context *rctx);
438 void r600_polygon_offset_update(struct r600_context *rctx);
439 void r600_adjust_gprs(struct r600_context *rctx);
440 boolean r600_is_format_supported(struct pipe_screen *screen,
441 enum pipe_format format,
442 enum pipe_texture_target target,
443 unsigned sample_count,
444 unsigned usage);
445
446 /* r600_texture.c */
447 void r600_init_screen_texture_functions(struct pipe_screen *screen);
448 void r600_init_surface_functions(struct r600_context *r600);
449 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
450 const unsigned char *swizzle_view,
451 uint32_t *word4_p, uint32_t *yuv_format_p);
452 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
453 unsigned level, unsigned layer);
454
455 /* r600_translate.c */
456 void r600_translate_index_buffer(struct r600_context *r600,
457 struct pipe_index_buffer *ib,
458 unsigned count);
459
460 /* r600_state_common.c */
461 void r600_init_atom(struct r600_atom *atom,
462 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
463 unsigned num_dw, enum r600_atom_flags flags);
464 void r600_init_common_atoms(struct r600_context *rctx);
465 unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
466 void r600_texture_barrier(struct pipe_context *ctx);
467 void r600_set_index_buffer(struct pipe_context *ctx,
468 const struct pipe_index_buffer *ib);
469 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
470 const struct pipe_vertex_buffer *buffers);
471 void *r600_create_vertex_elements(struct pipe_context *ctx,
472 unsigned count,
473 const struct pipe_vertex_element *elements);
474 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
475 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
476 void r600_set_blend_color(struct pipe_context *ctx,
477 const struct pipe_blend_color *state);
478 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
479 void r600_set_max_scissor(struct r600_context *rctx);
480 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
481 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
482 void r600_sampler_view_destroy(struct pipe_context *ctx,
483 struct pipe_sampler_view *state);
484 void r600_delete_state(struct pipe_context *ctx, void *state);
485 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
486 void *r600_create_shader_state(struct pipe_context *ctx,
487 const struct pipe_shader_state *state);
488 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
489 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
490 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
491 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
492 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
493 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
494 struct pipe_constant_buffer *cb);
495 struct pipe_stream_output_target *
496 r600_create_so_target(struct pipe_context *ctx,
497 struct pipe_resource *buffer,
498 unsigned buffer_offset,
499 unsigned buffer_size);
500 void r600_so_target_destroy(struct pipe_context *ctx,
501 struct pipe_stream_output_target *target);
502 void r600_set_so_targets(struct pipe_context *ctx,
503 unsigned num_targets,
504 struct pipe_stream_output_target **targets,
505 unsigned append_bitmask);
506 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
507 const struct pipe_stencil_ref *state);
508 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
509 uint32_t r600_translate_stencil_op(int s_op);
510 uint32_t r600_translate_fill(uint32_t func);
511 unsigned r600_tex_wrap(unsigned wrap);
512 unsigned r600_tex_filter(unsigned filter);
513 unsigned r600_tex_mipfilter(unsigned filter);
514 unsigned r600_tex_compare(unsigned compare);
515
516 /*
517 * Helpers for building command buffers
518 */
519
520 #define PKT3_SET_CONFIG_REG 0x68
521 #define PKT3_SET_CONTEXT_REG 0x69
522 #define PKT3_SET_CTL_CONST 0x6F
523 #define PKT3_SET_LOOP_CONST 0x6C
524
525 #define R600_CONFIG_REG_OFFSET 0x08000
526 #define R600_CONTEXT_REG_OFFSET 0x28000
527 #define R600_CTL_CONST_OFFSET 0x3CFF0
528 #define R600_LOOP_CONST_OFFSET 0X0003E200
529 #define EG_LOOP_CONST_OFFSET 0x0003A200
530
531 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
532 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
533 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
534 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
535 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
536
537 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
538 {
539 cb->buf[cb->atom.num_dw++] = value;
540 }
541
542 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
543 {
544 assert(reg < R600_CONTEXT_REG_OFFSET);
545 assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
546 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
547 cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
548 }
549
550 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
551 {
552 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
553 assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
554 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
555 cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
556 }
557
558 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
559 {
560 assert(reg >= R600_CTL_CONST_OFFSET);
561 assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
562 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
563 cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
564 }
565
566 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
567 {
568 assert(reg >= R600_LOOP_CONST_OFFSET);
569 assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
570 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
571 cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
572 }
573
574 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
575 {
576 assert(reg >= EG_LOOP_CONST_OFFSET);
577 assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
578 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
579 cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
580 }
581
582 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
583 {
584 r600_store_config_reg_seq(cb, reg, 1);
585 r600_store_value(cb, value);
586 }
587
588 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
589 {
590 r600_store_context_reg_seq(cb, reg, 1);
591 r600_store_value(cb, value);
592 }
593
594 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
595 {
596 r600_store_ctl_const_seq(cb, reg, 1);
597 r600_store_value(cb, value);
598 }
599
600 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
601 {
602 r600_store_loop_const_seq(cb, reg, 1);
603 r600_store_value(cb, value);
604 }
605
606 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
607 {
608 eg_store_loop_const_seq(cb, reg, 1);
609 r600_store_value(cb, value);
610 }
611
612 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags);
613 void r600_release_command_buffer(struct r600_command_buffer *cb);
614
615 /*
616 * Helpers for emitting state into a command stream directly.
617 */
618
619 static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo,
620 enum radeon_bo_usage usage)
621 {
622 assert(usage);
623 return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4;
624 }
625
626 static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
627 {
628 cs->buf[cs->cdw++] = value;
629 }
630
631 static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
632 {
633 assert(reg < R600_CONTEXT_REG_OFFSET);
634 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
635 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
636 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
637 }
638
639 static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
640 {
641 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
642 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
643 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
644 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
645 }
646
647 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
648 {
649 assert(reg >= R600_CTL_CONST_OFFSET);
650 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
651 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
652 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
653 }
654
655 static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
656 {
657 r600_write_config_reg_seq(cs, reg, 1);
658 r600_write_value(cs, value);
659 }
660
661 static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
662 {
663 r600_write_context_reg_seq(cs, reg, 1);
664 r600_write_value(cs, value);
665 }
666
667 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
668 {
669 r600_write_ctl_const_seq(cs, reg, 1);
670 r600_write_value(cs, value);
671 }
672
673 /*
674 * common helpers
675 */
676 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
677 {
678 return value * (1 << frac_bits);
679 }
680 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
681
682 static inline unsigned r600_tex_aniso_filter(unsigned filter)
683 {
684 if (filter <= 1) return 0;
685 if (filter <= 2) return 1;
686 if (filter <= 4) return 2;
687 if (filter <= 8) return 3;
688 /* else */ return 4;
689 }
690
691 /* 12.4 fixed-point */
692 static INLINE unsigned r600_pack_float_12p4(float x)
693 {
694 return x <= 0 ? 0 :
695 x >= 4096 ? 0xffff : x * 16;
696 }
697
698 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
699 {
700 struct r600_screen *rscreen = (struct r600_screen*)screen;
701 struct r600_resource *rresource = (struct r600_resource*)resource;
702
703 return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
704 }
705
706 #endif