2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "util/u_blitter.h"
30 #include "util/u_slab.h"
31 #include "util/u_suballoc.h"
33 #include "r600_llvm.h"
34 #include "r600_public.h"
35 #include "r600_resource.h"
36 #include "evergreen_compute.h"
38 #define R600_NUM_ATOMS 37
40 #define R600_TRACE_CS 0
42 #define R600_MAX_USER_CONST_BUFFERS 13
43 #define R600_MAX_DRIVER_CONST_BUFFERS 3
44 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
46 /* start driver buffers after user buffers */
47 #define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
48 #define R600_TXQ_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
49 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
51 #define R600_MAX_CONST_BUFFER_SIZE 4096
53 #ifdef PIPE_ARCH_BIG_ENDIAN
54 #define R600_BIG_ENDIAN 1
56 #define R600_BIG_ENDIAN 0
59 #define R600_MAP_BUFFER_ALIGNMENT 64
62 struct r600_shader_key
;
64 /* This encapsulates a state or an operation which can emitted into the GPU
65 * command stream. It's not limited to states only, it can be used for anything
66 * that wants to write commands into the CS (e.g. cache flushes). */
68 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
);
74 /* This is an atom containing GPU commands that never change.
75 * This is supposed to be copied directly into the CS. */
76 struct r600_command_buffer
{
83 struct r600_db_state
{
84 struct r600_atom atom
;
85 struct r600_surface
*rsurf
;
88 struct r600_db_misc_state
{
89 struct r600_atom atom
;
90 bool occlusion_query_enabled
;
91 bool flush_depthstencil_through_cb
;
92 bool flush_depthstencil_in_place
;
93 bool copy_depth
, copy_stencil
;
96 unsigned db_shader_control
;
100 struct r600_cb_misc_state
{
101 struct r600_atom atom
;
102 unsigned cb_color_control
; /* this comes from blend state */
103 unsigned blend_colormask
; /* 8*4 bits for 8 RGBA colorbuffers */
105 unsigned nr_ps_color_outputs
;
110 struct r600_clip_misc_state
{
111 struct r600_atom atom
;
112 unsigned pa_cl_clip_cntl
; /* from rasterizer */
113 unsigned pa_cl_vs_out_cntl
; /* from vertex shader */
114 unsigned clip_plane_enable
; /* from rasterizer */
115 unsigned clip_dist_write
; /* from vertex shader */
118 struct r600_alphatest_state
{
119 struct r600_atom atom
;
120 unsigned sx_alpha_test_control
; /* this comes from dsa state */
121 unsigned sx_alpha_ref
; /* this comes from dsa state */
123 bool cb0_export_16bpc
; /* from set_framebuffer_state */
126 struct r600_vgt_state
{
127 struct r600_atom atom
;
128 uint32_t vgt_multi_prim_ib_reset_en
;
129 uint32_t vgt_multi_prim_ib_reset_indx
;
132 struct r600_vgt2_state
{
133 struct r600_atom atom
;
134 uint32_t vgt_indx_offset
;
137 struct r600_blend_color
{
138 struct r600_atom atom
;
139 struct pipe_blend_color state
;
142 struct r600_clip_state
{
143 struct r600_atom atom
;
144 struct pipe_clip_state state
;
147 struct r600_cs_shader_state
{
148 struct r600_atom atom
;
149 unsigned kernel_index
;
150 struct r600_pipe_compute
*shader
;
153 struct r600_framebuffer
{
154 struct r600_atom atom
;
155 struct pipe_framebuffer_state state
;
156 unsigned compressed_cb_mask
;
160 bool is_msaa_resolve
;
163 struct r600_sample_mask
{
164 struct r600_atom atom
;
165 uint16_t sample_mask
; /* there are only 8 bits on EG, 16 bits on Cayman */
168 struct r600_config_state
{
169 struct r600_atom atom
;
170 unsigned sq_gpr_resource_mgmt_1
;
173 struct r600_stencil_ref
180 struct r600_stencil_ref_state
{
181 struct r600_atom atom
;
182 struct r600_stencil_ref state
;
183 struct pipe_stencil_ref pipe_state
;
186 struct r600_viewport_state
{
187 struct r600_atom atom
;
188 struct pipe_viewport_state state
;
191 struct compute_memory_pool
;
192 void compute_memory_pool_delete(struct compute_memory_pool
* pool
);
193 struct compute_memory_pool
* compute_memory_pool_new(
194 struct r600_screen
*rscreen
);
196 struct r600_pipe_fences
{
197 struct r600_resource
*bo
;
200 /* linked list of preallocated blocks */
201 struct list_head blocks
;
202 /* linked list of freed fences */
203 struct list_head pool
;
207 enum r600_msaa_texture_mode
{
208 /* If the hw can fetch the first sample only (no decompression available).
209 * This means MSAA texturing is not fully implemented. */
210 MSAA_TEXTURE_SAMPLE_ZERO
,
212 /* If the hw can fetch decompressed MSAA textures.
213 * Supported families: R600, R700, Evergreen.
214 * Cayman cannot use this, because it cannot do the decompression. */
215 MSAA_TEXTURE_DECOMPRESSED
,
217 /* If the hw can fetch compressed MSAA textures, which means shaders can
218 * read resolved FMASK. This yields the best performance.
219 * Supported families: Evergreen, Cayman. */
220 MSAA_TEXTURE_COMPRESSED
223 typedef boolean (*r600g_dma_blit_t
)(struct pipe_context
*ctx
,
224 struct pipe_resource
*dst
,
226 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
227 struct pipe_resource
*src
,
229 const struct pipe_box
*src_box
);
232 struct pipe_screen screen
;
233 struct radeon_winsys
*ws
;
235 enum chip_class chip_class
;
236 struct radeon_info info
;
239 enum r600_msaa_texture_mode msaa_texture_support
;
241 struct r600_tiling_info tiling_info
;
242 struct r600_pipe_fences fences
;
244 /*for compute global memory binding, we allocate stuff here, instead of
246 * XXX: Not sure if this is the best place for global_pool. Also,
247 * it's not thread safe, so it won't work with multiple contexts. */
248 struct compute_memory_pool
*global_pool
;
250 struct r600_resource
*trace_bo
;
254 r600g_dma_blit_t dma_blit
;
257 struct r600_pipe_sampler_view
{
258 struct pipe_sampler_view base
;
259 struct r600_resource
*tex_resource
;
260 uint32_t tex_resource_words
[8];
261 bool skip_mip_address_reloc
;
264 struct r600_rasterizer_state
{
265 struct r600_command_buffer buffer
;
268 unsigned sprite_coord_enable
;
269 unsigned clip_plane_enable
;
270 unsigned pa_sc_line_stipple
;
271 unsigned pa_cl_clip_cntl
;
276 bool multisample_enable
;
279 struct r600_poly_offset_state
{
280 struct r600_atom atom
;
281 enum pipe_format zs_format
;
286 struct r600_blend_state
{
287 struct r600_command_buffer buffer
;
288 struct r600_command_buffer buffer_no_blend
;
289 unsigned cb_target_mask
;
290 unsigned cb_color_control
;
291 unsigned cb_color_control_no_blend
;
296 struct r600_dsa_state
{
297 struct r600_command_buffer buffer
;
301 unsigned sx_alpha_test_control
;
304 struct r600_pipe_shader
;
306 struct r600_pipe_shader_selector
{
307 struct r600_pipe_shader
*current
;
309 struct tgsi_token
*tokens
;
310 struct pipe_stream_output_info so
;
312 unsigned num_shaders
;
314 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
317 unsigned nr_ps_max_color_exports
;
320 struct r600_pipe_sampler_state
{
321 uint32_t tex_sampler_words
[3];
322 union pipe_color_union border_color
;
323 bool border_color_use
;
324 bool seamless_cube_map
;
327 /* needed for blitter save */
328 #define NUM_TEX_UNITS 16
330 struct r600_seamless_cube_map
{
331 struct r600_atom atom
;
335 struct r600_samplerview_state
{
336 struct r600_atom atom
;
337 struct r600_pipe_sampler_view
*views
[NUM_TEX_UNITS
];
338 uint32_t enabled_mask
;
340 uint32_t compressed_depthtex_mask
; /* which textures are depth */
341 uint32_t compressed_colortex_mask
;
342 boolean dirty_txq_constants
;
343 boolean dirty_buffer_constants
;
346 struct r600_sampler_states
{
347 struct r600_atom atom
;
348 struct r600_pipe_sampler_state
*states
[NUM_TEX_UNITS
];
349 uint32_t enabled_mask
;
351 uint32_t has_bordercolor_mask
; /* which states contain the border color */
354 struct r600_textures_info
{
355 struct r600_samplerview_state views
;
356 struct r600_sampler_states states
;
357 bool is_array_sampler
[NUM_TEX_UNITS
];
359 /* cube array txq workaround */
360 uint32_t *txq_constants
;
361 /* buffer related workarounds */
362 uint32_t *buffer_constants
;
366 struct pipe_reference reference
;
367 unsigned index
; /* in the shared bo */
368 struct r600_resource
*sleep_bo
;
369 struct list_head head
;
372 #define FENCE_BLOCK_SIZE 16
374 struct r600_fence_block
{
375 struct r600_fence fences
[FENCE_BLOCK_SIZE
];
376 struct list_head head
;
379 #define R600_CONSTANT_ARRAY_SIZE 256
380 #define R600_RESOURCE_ARRAY_SIZE 160
382 struct r600_constbuf_state
384 struct r600_atom atom
;
385 struct pipe_constant_buffer cb
[PIPE_MAX_CONSTANT_BUFFERS
];
386 uint32_t enabled_mask
;
390 struct r600_vertexbuf_state
392 struct r600_atom atom
;
393 struct pipe_vertex_buffer vb
[PIPE_MAX_ATTRIBS
];
394 uint32_t enabled_mask
; /* non-NULL buffers */
398 /* CSO (constant state object, in other words, immutable state). */
399 struct r600_cso_state
401 struct r600_atom atom
;
402 void *cso
; /* e.g. r600_blend_state */
403 struct r600_command_buffer
*cb
;
406 struct r600_scissor_state
408 struct r600_atom atom
;
409 struct pipe_scissor_state scissor
;
410 bool enable
; /* r6xx only */
413 struct r600_fetch_shader
{
414 struct r600_resource
*buffer
;
419 struct radeon_winsys_cs
*cs
;
421 void (*flush
)(void *ctx
, unsigned flags
);
425 struct r600_ring gfx
;
426 struct r600_ring dma
;
429 struct r600_context
{
430 struct pipe_context context
;
431 struct r600_screen
*screen
;
432 struct radeon_winsys
*ws
;
433 struct r600_rings rings
;
434 struct blitter_context
*blitter
;
435 struct u_upload_mgr
*uploader
;
436 struct u_suballocator
*allocator_so_filled_size
;
437 struct u_suballocator
*allocator_fetch_shader
;
438 struct util_slab_mempool pool_transfers
;
441 enum radeon_family family
;
442 enum chip_class chip_class
;
443 boolean has_vertex_cache
;
444 boolean keep_tiling_flags
;
445 unsigned default_ps_gprs
, default_vs_gprs
;
446 unsigned r6xx_num_clause_temp_gprs
;
447 unsigned backend_mask
;
448 unsigned max_db
; /* for OQ */
450 /* current unaccounted memory usage */
454 /* Miscellaneous state objects. */
455 void *custom_dsa_flush
;
456 void *custom_blend_resolve
;
457 void *custom_blend_decompress
;
458 void *custom_blend_fmask_decompress
;
459 /* With rasterizer discard, there doesn't have to be a pixel shader.
460 * In that case, we bind this one: */
461 void *dummy_pixel_shader
;
462 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
463 * bug where valid CMASK and FMASK are required to be present to avoid
464 * a hardlock in certain operations but aren't actually used
465 * for anything useful. */
466 struct r600_resource
*dummy_fmask
;
467 struct r600_resource
*dummy_cmask
;
469 /* State binding slots are here. */
470 struct r600_atom
*atoms
[R600_NUM_ATOMS
];
471 /* States for CS initialization. */
472 struct r600_command_buffer start_cs_cmd
; /* invariant state mostly */
473 /** Compute specific registers initializations. The start_cs_cmd atom
474 * must be emitted before start_compute_cs_cmd. */
475 struct r600_command_buffer start_compute_cs_cmd
;
476 /* Register states. */
477 struct r600_alphatest_state alphatest_state
;
478 struct r600_cso_state blend_state
;
479 struct r600_blend_color blend_color
;
480 struct r600_cb_misc_state cb_misc_state
;
481 struct r600_clip_misc_state clip_misc_state
;
482 struct r600_clip_state clip_state
;
483 struct r600_db_misc_state db_misc_state
;
484 struct r600_db_state db_state
;
485 struct r600_cso_state dsa_state
;
486 struct r600_framebuffer framebuffer
;
487 struct r600_poly_offset_state poly_offset_state
;
488 struct r600_cso_state rasterizer_state
;
489 struct r600_sample_mask sample_mask
;
490 struct r600_scissor_state scissor
;
491 struct r600_seamless_cube_map seamless_cube_map
;
492 struct r600_config_state config_state
;
493 struct r600_stencil_ref_state stencil_ref
;
494 struct r600_vgt_state vgt_state
;
495 struct r600_vgt2_state vgt2_state
;
496 struct r600_viewport_state viewport
;
497 /* Shaders and shader resources. */
498 struct r600_cso_state vertex_fetch_shader
;
499 struct r600_cs_shader_state cs_shader_state
;
500 struct r600_constbuf_state constbuf_state
[PIPE_SHADER_TYPES
];
501 struct r600_textures_info samplers
[PIPE_SHADER_TYPES
];
502 /** Vertex buffers for fetch shaders */
503 struct r600_vertexbuf_state vertex_buffer_state
;
504 /** Vertex buffers for compute shaders */
505 struct r600_vertexbuf_state cs_vertex_buffer_state
;
507 /* Additional context states. */
509 unsigned compute_cb_target_mask
;
510 struct r600_pipe_shader_selector
*ps_shader
;
511 struct r600_pipe_shader_selector
*vs_shader
;
512 struct r600_rasterizer_state
*rasterizer
;
514 bool force_blend_disable
;
515 boolean dual_src_blend
;
518 struct pipe_index_buffer index_buffer
;
520 /* Last draw state (-1 = unset). */
521 int last_primitive_type
; /* Last primitive type used in draw_vbo. */
522 int last_start_instance
;
525 /* The list of active queries. Only one query of each type can be active. */
526 int num_occlusion_queries
;
527 /* Keep track of non-timer queries, because they should be suspended
528 * during context flushing.
529 * The timer queries (TIME_ELAPSED) shouldn't be suspended. */
530 struct list_head active_nontimer_queries
;
531 unsigned num_cs_dw_nontimer_queries_suspend
;
532 /* If queries have been suspended. */
533 bool nontimer_queries_suspended
;
535 /* Render condition. */
536 struct pipe_query
*current_render_cond
;
537 unsigned current_render_cond_mode
;
538 boolean predicate_drawing
;
540 /* Streamout state. */
541 unsigned num_cs_dw_streamout_end
;
542 unsigned num_so_targets
;
543 struct r600_so_target
*so_targets
[PIPE_MAX_SO_BUFFERS
];
544 boolean streamout_start
;
545 unsigned streamout_append_bitmask
;
546 bool streamout_suspended
;
548 /* Deprecated state management. */
549 struct r600_range
*range
;
551 struct r600_block
**blocks
;
552 struct list_head dirty
;
553 struct list_head enable_list
;
554 unsigned pm4_dirty_cdwords
;
556 struct r600_isa
*isa
;
559 static INLINE
void r600_emit_command_buffer(struct radeon_winsys_cs
*cs
,
560 struct r600_command_buffer
*cb
)
562 assert(cs
->cdw
+ cb
->num_dw
<= RADEON_MAX_CMDBUF_DWORDS
);
563 memcpy(cs
->buf
+ cs
->cdw
, cb
->buf
, 4 * cb
->num_dw
);
564 cs
->cdw
+= cb
->num_dw
;
568 void r600_trace_emit(struct r600_context
*rctx
);
571 static INLINE
void r600_emit_atom(struct r600_context
*rctx
, struct r600_atom
*atom
)
573 atom
->emit(rctx
, atom
);
576 if (rctx
->screen
->trace_bo
) {
577 r600_trace_emit(rctx
);
582 static INLINE
void r600_set_cso_state(struct r600_cso_state
*state
, void *cso
)
585 state
->atom
.dirty
= cso
!= NULL
;
588 static INLINE
void r600_set_cso_state_with_cb(struct r600_cso_state
*state
, void *cso
,
589 struct r600_command_buffer
*cb
)
592 state
->atom
.num_dw
= cb
->num_dw
;
593 r600_set_cso_state(state
, cso
);
596 /* evergreen_state.c */
597 struct pipe_sampler_view
*
598 evergreen_create_sampler_view_custom(struct pipe_context
*ctx
,
599 struct pipe_resource
*texture
,
600 const struct pipe_sampler_view
*state
,
601 unsigned width0
, unsigned height0
);
602 void evergreen_init_common_regs(struct r600_command_buffer
*cb
,
603 enum chip_class ctx_chip_class
,
604 enum radeon_family ctx_family
,
606 void cayman_init_common_regs(struct r600_command_buffer
*cb
,
607 enum chip_class ctx_chip_class
,
608 enum radeon_family ctx_family
,
611 void evergreen_init_state_functions(struct r600_context
*rctx
);
612 void evergreen_init_atom_start_cs(struct r600_context
*rctx
);
613 void evergreen_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
614 void evergreen_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
615 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
);
616 void *evergreen_create_resolve_blend(struct r600_context
*rctx
);
617 void *evergreen_create_decompress_blend(struct r600_context
*rctx
);
618 void *evergreen_create_fmask_decompress_blend(struct r600_context
*rctx
);
619 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
620 enum pipe_format format
,
621 enum pipe_texture_target target
,
622 unsigned sample_count
,
624 void evergreen_init_color_surface(struct r600_context
*rctx
,
625 struct r600_surface
*surf
);
626 void evergreen_init_color_surface_rat(struct r600_context
*rctx
,
627 struct r600_surface
*surf
);
628 void evergreen_update_db_shader_control(struct r600_context
* rctx
);
631 void r600_copy_buffer(struct pipe_context
*ctx
, struct pipe_resource
*dst
, unsigned dstx
,
632 struct pipe_resource
*src
, const struct pipe_box
*src_box
);
633 void r600_init_blit_functions(struct r600_context
*rctx
);
634 void r600_blit_decompress_depth(struct pipe_context
*ctx
,
635 struct r600_texture
*texture
,
636 struct r600_texture
*staging
,
637 unsigned first_level
, unsigned last_level
,
638 unsigned first_layer
, unsigned last_layer
,
639 unsigned first_sample
, unsigned last_sample
);
640 void r600_decompress_depth_textures(struct r600_context
*rctx
,
641 struct r600_samplerview_state
*textures
);
642 void r600_decompress_color_textures(struct r600_context
*rctx
,
643 struct r600_samplerview_state
*textures
);
646 bool r600_init_resource(struct r600_screen
*rscreen
,
647 struct r600_resource
*res
,
648 unsigned size
, unsigned alignment
,
649 bool use_reusable_pool
, unsigned usage
);
650 struct pipe_resource
*r600_buffer_create(struct pipe_screen
*screen
,
651 const struct pipe_resource
*templ
,
655 boolean
r600_rings_is_buffer_referenced(struct r600_context
*ctx
,
656 struct radeon_winsys_cs_handle
*buf
,
657 enum radeon_bo_usage usage
);
658 void *r600_buffer_mmap_sync_with_rings(struct r600_context
*ctx
,
659 struct r600_resource
*resource
,
663 void r600_init_query_functions(struct r600_context
*rctx
);
664 void r600_suspend_nontimer_queries(struct r600_context
*ctx
);
665 void r600_resume_nontimer_queries(struct r600_context
*ctx
);
667 /* r600_resource.c */
668 void r600_init_context_resource_functions(struct r600_context
*r600
);
671 int r600_pipe_shader_create(struct pipe_context
*ctx
,
672 struct r600_pipe_shader
*shader
,
673 struct r600_shader_key key
);
675 int r600_compute_shader_create(struct pipe_context
* ctx
,
676 LLVMModuleRef mod
, struct r600_bytecode
* bytecode
);
678 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
681 struct pipe_sampler_view
*
682 r600_create_sampler_view_custom(struct pipe_context
*ctx
,
683 struct pipe_resource
*texture
,
684 const struct pipe_sampler_view
*state
,
685 unsigned width_first_level
, unsigned height_first_level
);
686 void r600_init_state_functions(struct r600_context
*rctx
);
687 void r600_init_atom_start_cs(struct r600_context
*rctx
);
688 void r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
689 void r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
690 void *r600_create_db_flush_dsa(struct r600_context
*rctx
);
691 void *r600_create_resolve_blend(struct r600_context
*rctx
);
692 void *r700_create_resolve_blend(struct r600_context
*rctx
);
693 void *r600_create_decompress_blend(struct r600_context
*rctx
);
694 bool r600_adjust_gprs(struct r600_context
*rctx
);
695 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
696 enum pipe_format format
,
697 enum pipe_texture_target target
,
698 unsigned sample_count
,
700 void r600_update_db_shader_control(struct r600_context
* rctx
);
703 void r600_init_screen_texture_functions(struct pipe_screen
*screen
);
704 void r600_init_surface_functions(struct r600_context
*r600
);
705 uint32_t r600_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
706 const unsigned char *swizzle_view
,
707 uint32_t *word4_p
, uint32_t *yuv_format_p
);
708 unsigned r600_texture_get_offset(struct r600_texture
*rtex
,
709 unsigned level
, unsigned layer
);
710 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
711 struct pipe_resource
*texture
,
712 const struct pipe_surface
*templ
,
713 unsigned width
, unsigned height
);
715 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
716 const unsigned char *swizzle_view
,
719 /* r600_state_common.c */
720 void r600_init_common_state_functions(struct r600_context
*rctx
);
721 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
722 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
723 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
);
724 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
725 void r600_emit_vgt2_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
726 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
727 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
);
728 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
729 void r600_init_atom(struct r600_context
*rctx
, struct r600_atom
*atom
, unsigned id
,
730 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
732 void r600_vertex_buffers_dirty(struct r600_context
*rctx
);
733 void r600_sampler_views_dirty(struct r600_context
*rctx
,
734 struct r600_samplerview_state
*state
);
735 void r600_sampler_states_dirty(struct r600_context
*rctx
,
736 struct r600_sampler_states
*state
);
737 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
);
738 void r600_draw_rectangle(struct blitter_context
*blitter
,
739 int x1
, int y1
, int x2
, int y2
, float depth
,
740 enum blitter_attrib_type type
, const union pipe_color_union
*attrib
);
741 uint32_t r600_translate_stencil_op(int s_op
);
742 uint32_t r600_translate_fill(uint32_t func
);
743 unsigned r600_tex_wrap(unsigned wrap
);
744 unsigned r600_tex_filter(unsigned filter
);
745 unsigned r600_tex_mipfilter(unsigned filter
);
746 unsigned r600_tex_compare(unsigned compare
);
747 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
);
750 * Helpers for building command buffers
753 #define PKT3_SET_CONFIG_REG 0x68
754 #define PKT3_SET_CONTEXT_REG 0x69
755 #define PKT3_SET_CTL_CONST 0x6F
756 #define PKT3_SET_LOOP_CONST 0x6C
758 #define R600_CONFIG_REG_OFFSET 0x08000
759 #define R600_CONTEXT_REG_OFFSET 0x28000
760 #define R600_CTL_CONST_OFFSET 0x3CFF0
761 #define R600_LOOP_CONST_OFFSET 0X0003E200
762 #define EG_LOOP_CONST_OFFSET 0x0003A200
764 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
765 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
766 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
767 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
768 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
770 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
772 /*Evergreen Compute packet3*/
773 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
775 static INLINE
void r600_store_value(struct r600_command_buffer
*cb
, unsigned value
)
777 cb
->buf
[cb
->num_dw
++] = value
;
780 static INLINE
void r600_store_config_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
782 assert(reg
< R600_CONTEXT_REG_OFFSET
);
783 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
784 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
785 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
789 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
792 static INLINE
void r600_store_context_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
794 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
795 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
796 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0) | cb
->pkt_flags
;
797 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
801 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
804 static INLINE
void r600_store_ctl_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
806 assert(reg
>= R600_CTL_CONST_OFFSET
);
807 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
808 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0) | cb
->pkt_flags
;
809 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
812 static INLINE
void r600_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
814 assert(reg
>= R600_LOOP_CONST_OFFSET
);
815 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
816 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0);
817 cb
->buf
[cb
->num_dw
++] = (reg
- R600_LOOP_CONST_OFFSET
) >> 2;
821 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
824 static INLINE
void eg_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
826 assert(reg
>= EG_LOOP_CONST_OFFSET
);
827 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
828 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0) | cb
->pkt_flags
;
829 cb
->buf
[cb
->num_dw
++] = (reg
- EG_LOOP_CONST_OFFSET
) >> 2;
832 static INLINE
void r600_store_config_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
834 r600_store_config_reg_seq(cb
, reg
, 1);
835 r600_store_value(cb
, value
);
838 static INLINE
void r600_store_context_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
840 r600_store_context_reg_seq(cb
, reg
, 1);
841 r600_store_value(cb
, value
);
844 static INLINE
void r600_store_ctl_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
846 r600_store_ctl_const_seq(cb
, reg
, 1);
847 r600_store_value(cb
, value
);
850 static INLINE
void r600_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
852 r600_store_loop_const_seq(cb
, reg
, 1);
853 r600_store_value(cb
, value
);
856 static INLINE
void eg_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
858 eg_store_loop_const_seq(cb
, reg
, 1);
859 r600_store_value(cb
, value
);
862 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
);
863 void r600_release_command_buffer(struct r600_command_buffer
*cb
);
866 * Helpers for emitting state into a command stream directly.
868 static INLINE
unsigned r600_context_bo_reloc(struct r600_context
*ctx
,
869 struct r600_ring
*ring
,
870 struct r600_resource
*rbo
,
871 enum radeon_bo_usage usage
)
874 /* make sure that all previous ring use are flushed so everything
875 * look serialized from driver pov
877 if (!ring
->flushing
) {
878 if (ring
== &ctx
->rings
.gfx
) {
879 if (ctx
->rings
.dma
.cs
) {
881 ctx
->rings
.dma
.flush(ctx
, RADEON_FLUSH_ASYNC
);
885 ctx
->rings
.gfx
.flush(ctx
, RADEON_FLUSH_ASYNC
);
888 return ctx
->ws
->cs_add_reloc(ring
->cs
, rbo
->cs_buf
, usage
, rbo
->domains
) * 4;
891 static INLINE
void r600_write_value(struct radeon_winsys_cs
*cs
, unsigned value
)
893 cs
->buf
[cs
->cdw
++] = value
;
896 static INLINE
void r600_write_array(struct radeon_winsys_cs
*cs
, unsigned num
, unsigned *ptr
)
898 assert(cs
->cdw
+num
<= RADEON_MAX_CMDBUF_DWORDS
);
899 memcpy(&cs
->buf
[cs
->cdw
], ptr
, num
* sizeof(ptr
[0]));
903 static INLINE
void r600_write_config_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
905 assert(reg
< R600_CONTEXT_REG_OFFSET
);
906 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
907 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
908 cs
->buf
[cs
->cdw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
911 static INLINE
void r600_write_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
913 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
914 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
915 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0);
916 cs
->buf
[cs
->cdw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
919 static INLINE
void r600_write_compute_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
921 r600_write_context_reg_seq(cs
, reg
, num
);
922 /* Set the compute bit on the packet header */
923 cs
->buf
[cs
->cdw
- 2] |= RADEON_CP_PACKET3_COMPUTE_MODE
;
926 static INLINE
void r600_write_ctl_const_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
928 assert(reg
>= R600_CTL_CONST_OFFSET
);
929 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
930 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0);
931 cs
->buf
[cs
->cdw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
934 static INLINE
void r600_write_config_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
936 r600_write_config_reg_seq(cs
, reg
, 1);
937 r600_write_value(cs
, value
);
940 static INLINE
void r600_write_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
942 r600_write_context_reg_seq(cs
, reg
, 1);
943 r600_write_value(cs
, value
);
946 static INLINE
void r600_write_compute_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
948 r600_write_compute_context_reg_seq(cs
, reg
, 1);
949 r600_write_value(cs
, value
);
952 static INLINE
void r600_write_ctl_const(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
954 r600_write_ctl_const_seq(cs
, reg
, 1);
955 r600_write_value(cs
, value
);
961 static INLINE
uint32_t S_FIXED(float value
, uint32_t frac_bits
)
963 return value
* (1 << frac_bits
);
965 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
967 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
969 if (filter
<= 1) return 0;
970 if (filter
<= 2) return 1;
971 if (filter
<= 4) return 2;
972 if (filter
<= 8) return 3;
976 /* 12.4 fixed-point */
977 static INLINE
unsigned r600_pack_float_12p4(float x
)
980 x
>= 4096 ? 0xffff : x
* 16;
983 static INLINE
uint64_t r600_resource_va(struct pipe_screen
*screen
, struct pipe_resource
*resource
)
985 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
986 struct r600_resource
*rresource
= (struct r600_resource
*)resource
;
988 return rscreen
->ws
->buffer_get_virtual_address(rresource
->cs_buf
);
991 static INLINE
unsigned u_max_layer(struct pipe_resource
*r
, unsigned level
)
994 case PIPE_TEXTURE_CUBE
:
996 case PIPE_TEXTURE_3D
:
997 return u_minify(r
->depth0
, level
) - 1;
998 case PIPE_TEXTURE_1D_ARRAY
:
999 case PIPE_TEXTURE_2D_ARRAY
:
1000 case PIPE_TEXTURE_CUBE_ARRAY
:
1001 return r
->array_size
- 1;
1007 static INLINE
void r600_context_add_resource_size(struct pipe_context
*ctx
, struct pipe_resource
*r
)
1009 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1010 struct r600_resource
*rr
= (struct r600_resource
*)r
;
1017 * The idea is to compute a gross estimate of memory requirement of
1018 * each draw call. After each draw call, memory will be precisely
1019 * accounted. So the uncertainty is only on the current draw call.
1020 * In practice this gave very good estimate (+/- 10% of the target
1023 if (rr
->domains
& RADEON_DOMAIN_GTT
) {
1024 rctx
->gtt
+= rr
->buf
->size
;
1026 if (rr
->domains
& RADEON_DOMAIN_VRAM
) {
1027 rctx
->vram
+= rr
->buf
->size
;