2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "radeon/r600_pipe_common.h"
30 #include "radeon/r600_cs.h"
32 #include "r600_llvm.h"
33 #include "r600_public.h"
35 #include "util/u_suballoc.h"
36 #include "util/list.h"
37 #include "util/u_transfer.h"
39 #include "tgsi/tgsi_scan.h"
41 #define R600_NUM_ATOMS 43
43 #define R600_MAX_VIEWPORTS 16
46 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
47 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
48 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
49 /* read-write caches */
50 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
51 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
52 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
53 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
54 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
55 /* engine synchronization */
56 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
57 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
58 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
60 /* the number of CS dwords for flushing and drawing */
61 #define R600_MAX_FLUSH_CS_DWORDS 16
62 #define R600_MAX_DRAW_CS_DWORDS 52
63 #define R600_TRACE_CS_DWORDS 7
65 #define R600_MAX_USER_CONST_BUFFERS 13
66 #define R600_MAX_DRIVER_CONST_BUFFERS 2
67 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
69 /* start driver buffers after user buffers */
70 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
71 #define R600_UCP_SIZE (4*4*8)
72 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
74 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
75 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
76 * of 16 const buffers.
77 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
79 * In order to support d3d 11 mandated minimum of 15 user const buffers
80 * we'd have to squash all use cases into one driver buffer.
82 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
85 #define R600_HW_STAGE_PS 0
86 #define R600_HW_STAGE_VS 1
87 #define R600_HW_STAGE_GS 2
88 #define R600_HW_STAGE_ES 3
89 #define EG_HW_STAGE_LS 4
90 #define EG_HW_STAGE_HS 5
92 #define R600_NUM_HW_STAGES 4
93 #define EG_NUM_HW_STAGES 6
95 #ifdef PIPE_ARCH_BIG_ENDIAN
96 #define R600_BIG_ENDIAN 1
98 #define R600_BIG_ENDIAN 0
102 struct r600_bytecode
;
103 union r600_shader_key
;
105 /* This is an atom containing GPU commands that never change.
106 * This is supposed to be copied directly into the CS. */
107 struct r600_command_buffer
{
114 struct r600_db_state
{
115 struct r600_atom atom
;
116 struct r600_surface
*rsurf
;
119 struct r600_db_misc_state
{
120 struct r600_atom atom
;
121 bool occlusion_query_enabled
;
122 bool flush_depthstencil_through_cb
;
123 bool flush_depth_inplace
;
124 bool flush_stencil_inplace
;
125 bool copy_depth
, copy_stencil
;
126 unsigned copy_sample
;
127 unsigned log_samples
;
128 unsigned db_shader_control
;
130 uint8_t ps_conservative_z
;
133 struct r600_cb_misc_state
{
134 struct r600_atom atom
;
135 unsigned cb_color_control
; /* this comes from blend state */
136 unsigned blend_colormask
; /* 8*4 bits for 8 RGBA colorbuffers */
138 unsigned nr_ps_color_outputs
;
143 struct r600_clip_misc_state
{
144 struct r600_atom atom
;
145 unsigned pa_cl_clip_cntl
; /* from rasterizer */
146 unsigned pa_cl_vs_out_cntl
; /* from vertex shader */
147 unsigned clip_plane_enable
; /* from rasterizer */
148 unsigned clip_dist_write
; /* from vertex shader */
149 boolean clip_disable
; /* from vertex shader */
152 struct r600_alphatest_state
{
153 struct r600_atom atom
;
154 unsigned sx_alpha_test_control
; /* this comes from dsa state */
155 unsigned sx_alpha_ref
; /* this comes from dsa state */
157 bool cb0_export_16bpc
; /* from set_framebuffer_state */
160 struct r600_vgt_state
{
161 struct r600_atom atom
;
162 uint32_t vgt_multi_prim_ib_reset_en
;
163 uint32_t vgt_multi_prim_ib_reset_indx
;
164 uint32_t vgt_indx_offset
;
165 bool last_draw_was_indirect
;
168 struct r600_blend_color
{
169 struct r600_atom atom
;
170 struct pipe_blend_color state
;
173 struct r600_clip_state
{
174 struct r600_atom atom
;
175 struct pipe_clip_state state
;
178 struct r600_cs_shader_state
{
179 struct r600_atom atom
;
180 unsigned kernel_index
;
182 struct r600_pipe_compute
*shader
;
185 struct r600_framebuffer
{
186 struct r600_atom atom
;
187 struct pipe_framebuffer_state state
;
188 unsigned compressed_cb_mask
;
192 bool is_msaa_resolve
;
195 struct r600_sample_mask
{
196 struct r600_atom atom
;
197 uint16_t sample_mask
; /* there are only 8 bits on EG, 16 bits on Cayman */
200 struct r600_config_state
{
201 struct r600_atom atom
;
202 unsigned sq_gpr_resource_mgmt_1
;
203 unsigned sq_gpr_resource_mgmt_2
;
206 struct r600_stencil_ref
213 struct r600_stencil_ref_state
{
214 struct r600_atom atom
;
215 struct r600_stencil_ref state
;
216 struct pipe_stencil_ref pipe_state
;
219 struct r600_viewport_state
{
220 struct r600_atom atom
;
221 struct pipe_viewport_state state
[R600_MAX_VIEWPORTS
];
225 struct r600_shader_stages_state
{
226 struct r600_atom atom
;
227 unsigned geom_enable
;
230 struct r600_gs_rings_state
{
231 struct r600_atom atom
;
233 struct pipe_constant_buffer esgs_ring
;
234 struct pipe_constant_buffer gsvs_ring
;
237 /* This must start from 16. */
239 #define DBG_LLVM (1 << 29)
240 #define DBG_NO_CP_DMA (1 << 30)
242 #define DBG_NO_SB (1 << 21)
243 #define DBG_SB_CS (1 << 22)
244 #define DBG_SB_DRY_RUN (1 << 23)
245 #define DBG_SB_STAT (1 << 24)
246 #define DBG_SB_DUMP (1 << 25)
247 #define DBG_SB_NO_FALLBACK (1 << 26)
248 #define DBG_SB_DISASM (1 << 27)
249 #define DBG_SB_SAFEMATH (1 << 28)
252 struct r600_common_screen b
;
254 bool has_compressed_msaa_texturing
;
256 /*for compute global memory binding, we allocate stuff here, instead of
258 * XXX: Not sure if this is the best place for global_pool. Also,
259 * it's not thread safe, so it won't work with multiple contexts. */
260 struct compute_memory_pool
*global_pool
;
263 struct r600_pipe_sampler_view
{
264 struct pipe_sampler_view base
;
265 struct list_head list
;
266 struct r600_resource
*tex_resource
;
267 uint32_t tex_resource_words
[8];
268 bool skip_mip_address_reloc
;
269 bool is_stencil_sampler
;
272 struct r600_rasterizer_state
{
273 struct r600_command_buffer buffer
;
276 unsigned sprite_coord_enable
;
277 unsigned clip_plane_enable
;
278 unsigned pa_sc_line_stipple
;
279 unsigned pa_cl_clip_cntl
;
280 unsigned pa_su_sc_mode_cntl
;
285 bool multisample_enable
;
288 struct r600_poly_offset_state
{
289 struct r600_atom atom
;
290 enum pipe_format zs_format
;
295 struct r600_blend_state
{
296 struct r600_command_buffer buffer
;
297 struct r600_command_buffer buffer_no_blend
;
298 unsigned cb_target_mask
;
299 unsigned cb_color_control
;
300 unsigned cb_color_control_no_blend
;
305 struct r600_dsa_state
{
306 struct r600_command_buffer buffer
;
311 unsigned sx_alpha_test_control
;
314 struct r600_pipe_shader
;
316 struct r600_pipe_shader_selector
{
317 struct r600_pipe_shader
*current
;
319 struct tgsi_token
*tokens
;
320 struct pipe_stream_output_info so
;
321 struct tgsi_shader_info info
;
323 unsigned num_shaders
;
325 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
328 /* geometry shader properties */
329 unsigned gs_output_prim
;
330 unsigned gs_max_out_vertices
;
331 unsigned gs_num_invocations
;
333 unsigned nr_ps_max_color_exports
;
336 struct r600_pipe_sampler_state
{
337 uint32_t tex_sampler_words
[3];
338 union pipe_color_union border_color
;
339 bool border_color_use
;
340 bool seamless_cube_map
;
343 /* needed for blitter save */
344 #define NUM_TEX_UNITS 16
346 struct r600_seamless_cube_map
{
347 struct r600_atom atom
;
351 struct r600_samplerview_state
{
352 struct r600_atom atom
;
353 struct r600_pipe_sampler_view
*views
[NUM_TEX_UNITS
];
354 uint32_t enabled_mask
;
356 uint32_t compressed_depthtex_mask
; /* which textures are depth */
357 uint32_t compressed_colortex_mask
;
358 boolean dirty_buffer_constants
;
361 struct r600_sampler_states
{
362 struct r600_atom atom
;
363 struct r600_pipe_sampler_state
*states
[NUM_TEX_UNITS
];
364 uint32_t enabled_mask
;
366 uint32_t has_bordercolor_mask
; /* which states contain the border color */
369 struct r600_textures_info
{
370 struct r600_samplerview_state views
;
371 struct r600_sampler_states states
;
372 bool is_array_sampler
[NUM_TEX_UNITS
];
375 struct r600_shader_driver_constants_info
{
376 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
380 bool texture_const_dirty
;
381 bool ps_sample_pos_dirty
;
384 struct r600_constbuf_state
386 struct r600_atom atom
;
387 struct pipe_constant_buffer cb
[PIPE_MAX_CONSTANT_BUFFERS
];
388 uint32_t enabled_mask
;
392 struct r600_vertexbuf_state
394 struct r600_atom atom
;
395 struct pipe_vertex_buffer vb
[PIPE_MAX_ATTRIBS
];
396 uint32_t enabled_mask
; /* non-NULL buffers */
400 /* CSO (constant state object, in other words, immutable state). */
401 struct r600_cso_state
403 struct r600_atom atom
;
404 void *cso
; /* e.g. r600_blend_state */
405 struct r600_command_buffer
*cb
;
408 struct r600_scissor_state
410 struct r600_atom atom
;
411 struct pipe_scissor_state scissor
[R600_MAX_VIEWPORTS
];
413 bool enable
; /* r6xx only */
416 struct r600_fetch_shader
{
417 struct r600_resource
*buffer
;
421 struct r600_shader_state
{
422 struct r600_atom atom
;
423 struct r600_pipe_shader
*shader
;
426 struct r600_context
{
427 struct r600_common_context b
;
428 struct r600_screen
*screen
;
429 struct blitter_context
*blitter
;
430 struct u_suballocator
*allocator_fetch_shader
;
433 boolean has_vertex_cache
;
434 boolean keep_tiling_flags
;
435 unsigned default_gprs
[EG_NUM_HW_STAGES
];
436 unsigned r6xx_num_clause_temp_gprs
;
438 /* Miscellaneous state objects. */
439 void *custom_dsa_flush
;
440 void *custom_blend_resolve
;
441 void *custom_blend_decompress
;
442 void *custom_blend_fastclear
;
443 /* With rasterizer discard, there doesn't have to be a pixel shader.
444 * In that case, we bind this one: */
445 void *dummy_pixel_shader
;
446 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
447 * bug where valid CMASK and FMASK are required to be present to avoid
448 * a hardlock in certain operations but aren't actually used
449 * for anything useful. */
450 struct r600_resource
*dummy_fmask
;
451 struct r600_resource
*dummy_cmask
;
453 /* State binding slots are here. */
454 struct r600_atom
*atoms
[R600_NUM_ATOMS
];
455 /* Dirty atom bitmask for fast tests */
456 uint64_t dirty_atoms
;
457 /* States for CS initialization. */
458 struct r600_command_buffer start_cs_cmd
; /* invariant state mostly */
459 /** Compute specific registers initializations. The start_cs_cmd atom
460 * must be emitted before start_compute_cs_cmd. */
461 struct r600_command_buffer start_compute_cs_cmd
;
462 /* Register states. */
463 struct r600_alphatest_state alphatest_state
;
464 struct r600_cso_state blend_state
;
465 struct r600_blend_color blend_color
;
466 struct r600_cb_misc_state cb_misc_state
;
467 struct r600_clip_misc_state clip_misc_state
;
468 struct r600_clip_state clip_state
;
469 struct r600_db_misc_state db_misc_state
;
470 struct r600_db_state db_state
;
471 struct r600_cso_state dsa_state
;
472 struct r600_framebuffer framebuffer
;
473 struct r600_poly_offset_state poly_offset_state
;
474 struct r600_cso_state rasterizer_state
;
475 struct r600_sample_mask sample_mask
;
476 struct r600_scissor_state scissor
;
477 struct r600_seamless_cube_map seamless_cube_map
;
478 struct r600_config_state config_state
;
479 struct r600_stencil_ref_state stencil_ref
;
480 struct r600_vgt_state vgt_state
;
481 struct r600_viewport_state viewport
;
482 /* Shaders and shader resources. */
483 struct r600_cso_state vertex_fetch_shader
;
484 struct r600_shader_state vertex_shader
;
485 struct r600_shader_state pixel_shader
;
486 struct r600_shader_state geometry_shader
;
487 struct r600_shader_state export_shader
;
488 struct r600_cs_shader_state cs_shader_state
;
489 struct r600_shader_stages_state shader_stages
;
490 struct r600_gs_rings_state gs_rings
;
491 struct r600_constbuf_state constbuf_state
[PIPE_SHADER_TYPES
];
492 struct r600_textures_info samplers
[PIPE_SHADER_TYPES
];
494 struct r600_shader_driver_constants_info driver_consts
[PIPE_SHADER_TYPES
];
496 /** Vertex buffers for fetch shaders */
497 struct r600_vertexbuf_state vertex_buffer_state
;
498 /** Vertex buffers for compute shaders */
499 struct r600_vertexbuf_state cs_vertex_buffer_state
;
501 /* Additional context states. */
502 unsigned compute_cb_target_mask
;
503 struct r600_pipe_shader_selector
*ps_shader
;
504 struct r600_pipe_shader_selector
*vs_shader
;
505 struct r600_pipe_shader_selector
*gs_shader
;
506 struct r600_rasterizer_state
*rasterizer
;
508 bool force_blend_disable
;
509 boolean dual_src_blend
;
514 struct pipe_index_buffer index_buffer
;
516 /* Last draw state (-1 = unset). */
517 int last_primitive_type
; /* Last primitive type used in draw_vbo. */
518 int last_start_instance
;
521 struct r600_isa
*isa
;
522 float sample_positions
[4 * 16];
525 static inline void r600_emit_command_buffer(struct radeon_winsys_cs
*cs
,
526 struct r600_command_buffer
*cb
)
528 assert(cs
->cdw
+ cb
->num_dw
<= cs
->max_dw
);
529 memcpy(cs
->buf
+ cs
->cdw
, cb
->buf
, 4 * cb
->num_dw
);
530 cs
->cdw
+= cb
->num_dw
;
533 static inline void r600_set_atom_dirty(struct r600_context
*rctx
,
534 struct r600_atom
*atom
,
539 assert(atom
->id
!= 0);
540 assert(atom
->id
< sizeof(mask
) * 8);
541 mask
= 1ull << atom
->id
;
543 rctx
->dirty_atoms
|= mask
;
545 rctx
->dirty_atoms
&= ~mask
;
548 static inline void r600_mark_atom_dirty(struct r600_context
*rctx
,
549 struct r600_atom
*atom
)
551 r600_set_atom_dirty(rctx
, atom
, true);
554 void r600_trace_emit(struct r600_context
*rctx
);
556 static inline void r600_emit_atom(struct r600_context
*rctx
, struct r600_atom
*atom
)
558 atom
->emit(&rctx
->b
, atom
);
559 r600_set_atom_dirty(rctx
, atom
, false);
560 if (rctx
->screen
->b
.trace_bo
) {
561 r600_trace_emit(rctx
);
565 static inline void r600_set_cso_state(struct r600_context
*rctx
,
566 struct r600_cso_state
*state
, void *cso
)
569 r600_set_atom_dirty(rctx
, &state
->atom
, cso
!= NULL
);
572 static inline void r600_set_cso_state_with_cb(struct r600_context
*rctx
,
573 struct r600_cso_state
*state
, void *cso
,
574 struct r600_command_buffer
*cb
)
577 state
->atom
.num_dw
= cb
? cb
->num_dw
: 0;
578 r600_set_cso_state(rctx
, state
, cso
);
581 /* compute_memory_pool.c */
582 struct compute_memory_pool
;
583 void compute_memory_pool_delete(struct compute_memory_pool
* pool
);
584 struct compute_memory_pool
* compute_memory_pool_new(
585 struct r600_screen
*rscreen
);
587 /* evergreen_state.c */
588 struct pipe_sampler_view
*
589 evergreen_create_sampler_view_custom(struct pipe_context
*ctx
,
590 struct pipe_resource
*texture
,
591 const struct pipe_sampler_view
*state
,
592 unsigned width0
, unsigned height0
,
593 unsigned force_level
);
594 void evergreen_init_common_regs(struct r600_command_buffer
*cb
,
595 enum chip_class ctx_chip_class
,
596 enum radeon_family ctx_family
,
598 void cayman_init_common_regs(struct r600_command_buffer
*cb
,
599 enum chip_class ctx_chip_class
,
600 enum radeon_family ctx_family
,
603 void evergreen_init_state_functions(struct r600_context
*rctx
);
604 void evergreen_init_atom_start_cs(struct r600_context
*rctx
);
605 void evergreen_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
606 void evergreen_update_es_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
607 void evergreen_update_gs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
608 void evergreen_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
609 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
);
610 void *evergreen_create_resolve_blend(struct r600_context
*rctx
);
611 void *evergreen_create_decompress_blend(struct r600_context
*rctx
);
612 void *evergreen_create_fastclear_blend(struct r600_context
*rctx
);
613 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
614 enum pipe_format format
,
615 enum pipe_texture_target target
,
616 unsigned sample_count
,
618 void evergreen_init_color_surface(struct r600_context
*rctx
,
619 struct r600_surface
*surf
);
620 void evergreen_init_color_surface_rat(struct r600_context
*rctx
,
621 struct r600_surface
*surf
);
622 void evergreen_update_db_shader_control(struct r600_context
* rctx
);
625 void r600_init_blit_functions(struct r600_context
*rctx
);
626 void r600_decompress_depth_textures(struct r600_context
*rctx
,
627 struct r600_samplerview_state
*textures
);
628 void r600_decompress_color_textures(struct r600_context
*rctx
,
629 struct r600_samplerview_state
*textures
);
630 void r600_resource_copy_region(struct pipe_context
*ctx
,
631 struct pipe_resource
*dst
,
633 unsigned dstx
, unsigned dsty
, unsigned dstz
,
634 struct pipe_resource
*src
,
636 const struct pipe_box
*src_box
);
639 int r600_pipe_shader_create(struct pipe_context
*ctx
,
640 struct r600_pipe_shader
*shader
,
641 union r600_shader_key key
);
643 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
646 struct pipe_sampler_view
*
647 r600_create_sampler_view_custom(struct pipe_context
*ctx
,
648 struct pipe_resource
*texture
,
649 const struct pipe_sampler_view
*state
,
650 unsigned width_first_level
, unsigned height_first_level
);
651 void r600_init_state_functions(struct r600_context
*rctx
);
652 void r600_init_atom_start_cs(struct r600_context
*rctx
);
653 void r600_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
654 void r600_update_es_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
655 void r600_update_gs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
656 void r600_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
657 void *r600_create_db_flush_dsa(struct r600_context
*rctx
);
658 void *r600_create_resolve_blend(struct r600_context
*rctx
);
659 void *r700_create_resolve_blend(struct r600_context
*rctx
);
660 void *r600_create_decompress_blend(struct r600_context
*rctx
);
661 bool r600_adjust_gprs(struct r600_context
*rctx
);
662 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
663 enum pipe_format format
,
664 enum pipe_texture_target target
,
665 unsigned sample_count
,
667 void r600_update_db_shader_control(struct r600_context
* rctx
);
669 /* r600_hw_context.c */
670 void r600_context_gfx_flush(void *context
, unsigned flags
,
671 struct pipe_fence_handle
**fence
);
672 void r600_begin_new_cs(struct r600_context
*ctx
);
673 void r600_flush_emit(struct r600_context
*ctx
);
674 void r600_need_cs_space(struct r600_context
*ctx
, unsigned num_dw
, boolean count_draw_in
);
675 void r600_cp_dma_copy_buffer(struct r600_context
*rctx
,
676 struct pipe_resource
*dst
, uint64_t dst_offset
,
677 struct pipe_resource
*src
, uint64_t src_offset
,
679 void evergreen_cp_dma_clear_buffer(struct r600_context
*rctx
,
680 struct pipe_resource
*dst
, uint64_t offset
,
681 unsigned size
, uint32_t clear_value
);
682 void r600_dma_copy_buffer(struct r600_context
*rctx
,
683 struct pipe_resource
*dst
,
684 struct pipe_resource
*src
,
690 * evergreen_hw_context.c
692 void evergreen_dma_copy_buffer(struct r600_context
*rctx
,
693 struct pipe_resource
*dst
,
694 struct pipe_resource
*src
,
699 /* r600_state_common.c */
700 void r600_init_common_state_functions(struct r600_context
*rctx
);
701 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
702 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
703 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
);
704 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
705 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
706 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
);
707 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
708 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
);
709 void r600_add_atom(struct r600_context
*rctx
, struct r600_atom
*atom
, unsigned id
);
710 void r600_init_atom(struct r600_context
*rctx
, struct r600_atom
*atom
, unsigned id
,
711 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
713 void r600_vertex_buffers_dirty(struct r600_context
*rctx
);
714 void r600_sampler_views_dirty(struct r600_context
*rctx
,
715 struct r600_samplerview_state
*state
);
716 void r600_sampler_states_dirty(struct r600_context
*rctx
,
717 struct r600_sampler_states
*state
);
718 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
);
719 void r600_set_sample_locations_constant_buffer(struct r600_context
*rctx
);
720 uint32_t r600_translate_stencil_op(int s_op
);
721 uint32_t r600_translate_fill(uint32_t func
);
722 unsigned r600_tex_wrap(unsigned wrap
);
723 unsigned r600_tex_filter(unsigned filter
);
724 unsigned r600_tex_mipfilter(unsigned filter
);
725 unsigned r600_tex_compare(unsigned compare
);
726 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
);
727 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
728 struct pipe_resource
*texture
,
729 const struct pipe_surface
*templ
,
730 unsigned width
, unsigned height
);
731 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
732 const unsigned char *swizzle_view
,
734 uint32_t r600_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
735 const unsigned char *swizzle_view
,
736 uint32_t *word4_p
, uint32_t *yuv_format_p
);
737 uint32_t r600_translate_colorformat(enum chip_class chip
, enum pipe_format format
);
738 uint32_t r600_colorformat_endian_swap(uint32_t colorformat
);
741 struct pipe_video_codec
*r600_uvd_create_decoder(struct pipe_context
*context
,
742 const struct pipe_video_codec
*decoder
);
744 struct pipe_video_buffer
*r600_video_buffer_create(struct pipe_context
*pipe
,
745 const struct pipe_video_buffer
*tmpl
);
748 * Helpers for building command buffers
751 #define PKT3_SET_CONFIG_REG 0x68
752 #define PKT3_SET_CONTEXT_REG 0x69
753 #define PKT3_SET_CTL_CONST 0x6F
754 #define PKT3_SET_LOOP_CONST 0x6C
756 #define R600_CONFIG_REG_OFFSET 0x08000
757 #define R600_CONTEXT_REG_OFFSET 0x28000
758 #define R600_CTL_CONST_OFFSET 0x3CFF0
759 #define R600_LOOP_CONST_OFFSET 0X0003E200
760 #define EG_LOOP_CONST_OFFSET 0x0003A200
762 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
763 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
764 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
765 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
766 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
768 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
770 /*Evergreen Compute packet3*/
771 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
773 static inline void r600_store_value(struct r600_command_buffer
*cb
, unsigned value
)
775 cb
->buf
[cb
->num_dw
++] = value
;
778 static inline void r600_store_array(struct r600_command_buffer
*cb
, unsigned num
, unsigned *ptr
)
780 assert(cb
->num_dw
+num
<= cb
->max_num_dw
);
781 memcpy(&cb
->buf
[cb
->num_dw
], ptr
, num
* sizeof(ptr
[0]));
785 static inline void r600_store_config_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
787 assert(reg
< R600_CONTEXT_REG_OFFSET
);
788 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
789 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
790 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
794 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
797 static inline void r600_store_context_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
799 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
800 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
801 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0) | cb
->pkt_flags
;
802 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
806 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
809 static inline void r600_store_ctl_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
811 assert(reg
>= R600_CTL_CONST_OFFSET
);
812 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
813 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0) | cb
->pkt_flags
;
814 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
817 static inline void r600_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
819 assert(reg
>= R600_LOOP_CONST_OFFSET
);
820 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
821 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0);
822 cb
->buf
[cb
->num_dw
++] = (reg
- R600_LOOP_CONST_OFFSET
) >> 2;
826 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
829 static inline void eg_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
831 assert(reg
>= EG_LOOP_CONST_OFFSET
);
832 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
833 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0) | cb
->pkt_flags
;
834 cb
->buf
[cb
->num_dw
++] = (reg
- EG_LOOP_CONST_OFFSET
) >> 2;
837 static inline void r600_store_config_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
839 r600_store_config_reg_seq(cb
, reg
, 1);
840 r600_store_value(cb
, value
);
843 static inline void r600_store_context_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
845 r600_store_context_reg_seq(cb
, reg
, 1);
846 r600_store_value(cb
, value
);
849 static inline void r600_store_ctl_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
851 r600_store_ctl_const_seq(cb
, reg
, 1);
852 r600_store_value(cb
, value
);
855 static inline void r600_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
857 r600_store_loop_const_seq(cb
, reg
, 1);
858 r600_store_value(cb
, value
);
861 static inline void eg_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
863 eg_store_loop_const_seq(cb
, reg
, 1);
864 r600_store_value(cb
, value
);
867 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
);
868 void r600_release_command_buffer(struct r600_command_buffer
*cb
);
870 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
872 radeon_set_context_reg_seq(cs
, reg
, num
);
873 /* Set the compute bit on the packet header */
874 cs
->buf
[cs
->cdw
- 2] |= RADEON_CP_PACKET3_COMPUTE_MODE
;
877 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
879 assert(reg
>= R600_CTL_CONST_OFFSET
);
880 assert(cs
->cdw
+2+num
<= cs
->max_dw
);
881 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0);
882 cs
->buf
[cs
->cdw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
885 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
887 radeon_compute_set_context_reg_seq(cs
, reg
, 1);
888 radeon_emit(cs
, value
);
891 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
, unsigned flag
)
893 if (flag
& RADEON_CP_PACKET3_COMPUTE_MODE
) {
894 radeon_compute_set_context_reg(cs
, reg
, value
);
896 radeon_set_context_reg(cs
, reg
, value
);
900 static inline void radeon_set_ctl_const(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
902 radeon_set_ctl_const_seq(cs
, reg
, 1);
903 radeon_emit(cs
, value
);
909 static inline uint32_t S_FIXED(float value
, uint32_t frac_bits
)
911 return value
* (1 << frac_bits
);
913 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
915 /* 12.4 fixed-point */
916 static inline unsigned r600_pack_float_12p4(float x
)
919 x
>= 4096 ? 0xffff : x
* 16;
922 /* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */
923 static inline bool r600_can_read_depth(struct r600_texture
*rtex
)
925 return rtex
->resource
.b
.b
.nr_samples
<= 1 &&
926 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
927 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
);
930 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
931 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
932 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
934 unsigned r600_conv_prim_to_gs_out(unsigned mode
);