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gallium/u_upload_mgr: allow drivers to specify pipe_resource::flags
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "r600_pipe_common.h"
30 #include "r600_cs.h"
31 #include "r600_public.h"
32 #include "pipe/p_defines.h"
33
34 #include "util/u_suballoc.h"
35 #include "util/list.h"
36 #include "util/u_transfer.h"
37 #include "util/u_memory.h"
38
39 #include "tgsi/tgsi_scan.h"
40
41 #define R600_NUM_ATOMS 54
42
43 #define R600_MAX_IMAGES 8
44 /*
45 * ranges reserved for images on evergreen
46 * first set for the immediate buffers,
47 * second for the actual resources for RESQ.
48 */
49 #define R600_IMAGE_IMMED_RESOURCE_OFFSET 160
50 #define R600_IMAGE_REAL_RESOURCE_OFFSET 168
51
52 /* read caches */
53 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
54 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
55 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
56 /* read-write caches */
57 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
58 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
59 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
60 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
61 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
62 /* engine synchronization */
63 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
64 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
65 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
66
67 /* the number of CS dwords for flushing and drawing */
68 #define R600_MAX_FLUSH_CS_DWORDS 18
69 #define R600_MAX_DRAW_CS_DWORDS 58
70 #define R600_MAX_PFP_SYNC_ME_DWORDS 16
71
72 #define R600_MAX_USER_CONST_BUFFERS 13
73 #define R600_MAX_DRIVER_CONST_BUFFERS 3
74 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
75
76 #define EG_MAX_ATOMIC_BUFFERS 8
77
78 /* start driver buffers after user buffers */
79 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
80 #define R600_UCP_SIZE (4*4*8)
81 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
82
83 #define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
84 /*
85 * Note GS doesn't use a constant buffer binding, just a resource index,
86 * so it's fine to have it exist at index 16.
87 */
88 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
89 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
90 * of 16 const buffers.
91 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
92 *
93 * In order to support d3d 11 mandated minimum of 15 user const buffers
94 * we'd have to squash all use cases into one driver buffer.
95 */
96 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
97
98 /* HW stages */
99 #define R600_HW_STAGE_PS 0
100 #define R600_HW_STAGE_VS 1
101 #define R600_HW_STAGE_GS 2
102 #define R600_HW_STAGE_ES 3
103 #define EG_HW_STAGE_LS 4
104 #define EG_HW_STAGE_HS 5
105
106 #define R600_NUM_HW_STAGES 4
107 #define EG_NUM_HW_STAGES 6
108
109 struct r600_context;
110 struct r600_bytecode;
111 union r600_shader_key;
112
113 /* This is an atom containing GPU commands that never change.
114 * This is supposed to be copied directly into the CS. */
115 struct r600_command_buffer {
116 uint32_t *buf;
117 unsigned num_dw;
118 unsigned max_num_dw;
119 unsigned pkt_flags;
120 };
121
122 struct r600_db_state {
123 struct r600_atom atom;
124 struct r600_surface *rsurf;
125 };
126
127 struct r600_db_misc_state {
128 struct r600_atom atom;
129 bool occlusion_queries_disabled;
130 bool flush_depthstencil_through_cb;
131 bool flush_depth_inplace;
132 bool flush_stencil_inplace;
133 bool copy_depth, copy_stencil;
134 unsigned copy_sample;
135 unsigned log_samples;
136 unsigned db_shader_control;
137 bool htile_clear;
138 uint8_t ps_conservative_z;
139 };
140
141 struct r600_cb_misc_state {
142 struct r600_atom atom;
143 unsigned cb_color_control; /* this comes from blend state */
144 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
145 unsigned nr_cbufs;
146 unsigned nr_ps_color_outputs;
147 unsigned nr_image_rats;
148 unsigned nr_buffer_rats;
149 bool multiwrite;
150 bool dual_src_blend;
151 };
152
153 struct r600_clip_misc_state {
154 struct r600_atom atom;
155 unsigned pa_cl_clip_cntl; /* from rasterizer */
156 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
157 unsigned clip_plane_enable; /* from rasterizer */
158 unsigned cc_dist_mask; /* from vertex shader */
159 unsigned clip_dist_write; /* from vertex shader */
160 unsigned cull_dist_write; /* from vertex shader */
161 boolean clip_disable; /* from vertex shader */
162 boolean vs_out_viewport; /* from vertex shader */
163 };
164
165 struct r600_alphatest_state {
166 struct r600_atom atom;
167 unsigned sx_alpha_test_control; /* this comes from dsa state */
168 unsigned sx_alpha_ref; /* this comes from dsa state */
169 bool bypass;
170 bool cb0_export_16bpc; /* from set_framebuffer_state */
171 };
172
173 struct r600_vgt_state {
174 struct r600_atom atom;
175 uint32_t vgt_multi_prim_ib_reset_en;
176 uint32_t vgt_multi_prim_ib_reset_indx;
177 uint32_t vgt_indx_offset;
178 bool last_draw_was_indirect;
179 };
180
181 struct r600_blend_color {
182 struct r600_atom atom;
183 struct pipe_blend_color state;
184 };
185
186 struct r600_clip_state {
187 struct r600_atom atom;
188 struct pipe_clip_state state;
189 };
190
191 struct r600_cs_shader_state {
192 struct r600_atom atom;
193 unsigned kernel_index;
194 unsigned pc;
195 struct r600_pipe_compute *shader;
196 };
197
198 struct r600_framebuffer {
199 struct r600_atom atom;
200 struct pipe_framebuffer_state state;
201 unsigned compressed_cb_mask;
202 unsigned nr_samples;
203 bool export_16bpc;
204 bool cb0_is_integer;
205 bool is_msaa_resolve;
206 bool dual_src_blend;
207 bool do_update_surf_dirtiness;
208 };
209
210 struct r600_sample_mask {
211 struct r600_atom atom;
212 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
213 };
214
215 struct r600_config_state {
216 struct r600_atom atom;
217 unsigned sq_gpr_resource_mgmt_1;
218 unsigned sq_gpr_resource_mgmt_2;
219 unsigned sq_gpr_resource_mgmt_3;
220 bool dyn_gpr_enabled;
221 };
222
223 struct r600_stencil_ref
224 {
225 ubyte ref_value[2];
226 ubyte valuemask[2];
227 ubyte writemask[2];
228 };
229
230 struct r600_stencil_ref_state {
231 struct r600_atom atom;
232 struct r600_stencil_ref state;
233 struct pipe_stencil_ref pipe_state;
234 };
235
236 struct r600_shader_stages_state {
237 struct r600_atom atom;
238 unsigned geom_enable;
239 };
240
241 struct r600_gs_rings_state {
242 struct r600_atom atom;
243 unsigned enable;
244 struct pipe_constant_buffer esgs_ring;
245 struct pipe_constant_buffer gsvs_ring;
246 };
247
248 /* This must start from 16. */
249 /* features */
250 #define DBG_NO_CP_DMA (1 << 30)
251 /* shader backend */
252 #define DBG_NO_SB (1 << 21)
253 #define DBG_SB_CS (1 << 22)
254 #define DBG_SB_DRY_RUN (1 << 23)
255 #define DBG_SB_STAT (1 << 24)
256 #define DBG_SB_DUMP (1 << 25)
257 #define DBG_SB_NO_FALLBACK (1 << 26)
258 #define DBG_SB_DISASM (1 << 27)
259 #define DBG_SB_SAFEMATH (1 << 28)
260
261 struct r600_screen {
262 struct r600_common_screen b;
263 bool has_msaa;
264 bool has_compressed_msaa_texturing;
265 bool has_atomics;
266
267 /*for compute global memory binding, we allocate stuff here, instead of
268 * buffers.
269 * XXX: Not sure if this is the best place for global_pool. Also,
270 * it's not thread safe, so it won't work with multiple contexts. */
271 struct compute_memory_pool *global_pool;
272 };
273
274 struct r600_pipe_sampler_view {
275 struct pipe_sampler_view base;
276 struct list_head list;
277 struct r600_resource *tex_resource;
278 uint32_t tex_resource_words[8];
279 bool skip_mip_address_reloc;
280 bool is_stencil_sampler;
281 };
282
283 struct r600_rasterizer_state {
284 struct r600_command_buffer buffer;
285 boolean flatshade;
286 boolean two_side;
287 unsigned sprite_coord_enable;
288 unsigned clip_plane_enable;
289 unsigned pa_sc_line_stipple;
290 unsigned pa_cl_clip_cntl;
291 unsigned pa_su_sc_mode_cntl;
292 float offset_units;
293 float offset_scale;
294 bool offset_enable;
295 bool offset_units_unscaled;
296 bool scissor_enable;
297 bool multisample_enable;
298 bool clip_halfz;
299 bool rasterizer_discard;
300 };
301
302 struct r600_poly_offset_state {
303 struct r600_atom atom;
304 enum pipe_format zs_format;
305 float offset_units;
306 float offset_scale;
307 bool offset_units_unscaled;
308 };
309
310 struct r600_blend_state {
311 struct r600_command_buffer buffer;
312 struct r600_command_buffer buffer_no_blend;
313 unsigned cb_target_mask;
314 unsigned cb_color_control;
315 unsigned cb_color_control_no_blend;
316 bool dual_src_blend;
317 bool alpha_to_one;
318 };
319
320 struct r600_dsa_state {
321 struct r600_command_buffer buffer;
322 unsigned alpha_ref;
323 ubyte valuemask[2];
324 ubyte writemask[2];
325 unsigned zwritemask;
326 unsigned sx_alpha_test_control;
327 };
328
329 struct r600_pipe_shader;
330
331 struct r600_pipe_shader_selector {
332 struct r600_pipe_shader *current;
333
334 struct tgsi_token *tokens;
335 struct pipe_stream_output_info so;
336 struct tgsi_shader_info info;
337
338 unsigned num_shaders;
339
340 enum pipe_shader_type type;
341
342 /* geometry shader properties */
343 enum pipe_prim_type gs_output_prim;
344 unsigned gs_max_out_vertices;
345 unsigned gs_num_invocations;
346
347 /* TCS/VS */
348 uint64_t lds_patch_outputs_written_mask;
349 uint64_t lds_outputs_written_mask;
350 unsigned nr_ps_max_color_exports;
351 };
352
353 struct r600_pipe_sampler_state {
354 uint32_t tex_sampler_words[3];
355 union pipe_color_union border_color;
356 bool border_color_use;
357 bool seamless_cube_map;
358 };
359
360 /* needed for blitter save */
361 #define NUM_TEX_UNITS 16
362
363 struct r600_seamless_cube_map {
364 struct r600_atom atom;
365 bool enabled;
366 };
367
368 struct r600_samplerview_state {
369 struct r600_atom atom;
370 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
371 uint32_t enabled_mask;
372 uint32_t dirty_mask;
373 uint32_t compressed_depthtex_mask; /* which textures are depth */
374 uint32_t compressed_colortex_mask;
375 boolean dirty_buffer_constants;
376 };
377
378 struct r600_sampler_states {
379 struct r600_atom atom;
380 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
381 uint32_t enabled_mask;
382 uint32_t dirty_mask;
383 uint32_t has_bordercolor_mask; /* which states contain the border color */
384 };
385
386 struct r600_textures_info {
387 struct r600_samplerview_state views;
388 struct r600_sampler_states states;
389 bool is_array_sampler[NUM_TEX_UNITS];
390 };
391
392 struct r600_shader_driver_constants_info {
393 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
394 uint32_t *constants;
395 uint32_t alloc_size;
396 bool vs_ucp_dirty;
397 bool texture_const_dirty;
398 bool ps_sample_pos_dirty;
399 };
400
401 struct r600_constbuf_state
402 {
403 struct r600_atom atom;
404 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
405 uint32_t enabled_mask;
406 uint32_t dirty_mask;
407 };
408
409 struct r600_vertexbuf_state
410 {
411 struct r600_atom atom;
412 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
413 uint32_t enabled_mask; /* non-NULL buffers */
414 uint32_t dirty_mask;
415 };
416
417 /* CSO (constant state object, in other words, immutable state). */
418 struct r600_cso_state
419 {
420 struct r600_atom atom;
421 void *cso; /* e.g. r600_blend_state */
422 struct r600_command_buffer *cb;
423 };
424
425 struct r600_fetch_shader {
426 struct r600_resource *buffer;
427 unsigned offset;
428 };
429
430 struct r600_shader_state {
431 struct r600_atom atom;
432 struct r600_pipe_shader *shader;
433 };
434
435 struct r600_atomic_buffer_state {
436 uint32_t enabled_mask;
437 uint32_t dirty_mask;
438 struct pipe_shader_buffer buffer[EG_MAX_ATOMIC_BUFFERS];
439 };
440
441 struct r600_image_view {
442 struct pipe_image_view base;
443 uint32_t cb_color_base;
444 uint32_t cb_color_pitch;
445 uint32_t cb_color_slice;
446 uint32_t cb_color_view;
447 uint32_t cb_color_info;
448 uint32_t cb_color_attrib;
449 uint32_t cb_color_dim;
450 uint32_t cb_color_fmask;
451 uint32_t cb_color_fmask_slice;
452 uint32_t immed_resource_words[8];
453 uint32_t resource_words[8];
454 bool skip_mip_address_reloc;
455 uint32_t buf_size;
456 };
457
458 struct r600_image_state {
459 struct r600_atom atom;
460 uint32_t enabled_mask;
461 uint32_t dirty_mask;
462 uint32_t compressed_depthtex_mask;
463 uint32_t compressed_colortex_mask;
464 boolean dirty_buffer_constants;
465 struct r600_image_view views[R600_MAX_IMAGES];
466 };
467
468 struct r600_context {
469 struct r600_common_context b;
470 struct r600_screen *screen;
471 struct blitter_context *blitter;
472 struct u_suballocator *allocator_fetch_shader;
473
474 /* Hardware info. */
475 boolean has_vertex_cache;
476 unsigned default_gprs[EG_NUM_HW_STAGES];
477 unsigned current_gprs[EG_NUM_HW_STAGES];
478 unsigned r6xx_num_clause_temp_gprs;
479
480 /* Miscellaneous state objects. */
481 void *custom_dsa_flush;
482 void *custom_blend_resolve;
483 void *custom_blend_decompress;
484 void *custom_blend_fastclear;
485 /* With rasterizer discard, there doesn't have to be a pixel shader.
486 * In that case, we bind this one: */
487 void *dummy_pixel_shader;
488 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
489 * bug where valid CMASK and FMASK are required to be present to avoid
490 * a hardlock in certain operations but aren't actually used
491 * for anything useful. */
492 struct r600_resource *dummy_fmask;
493 struct r600_resource *dummy_cmask;
494
495 /* State binding slots are here. */
496 struct r600_atom *atoms[R600_NUM_ATOMS];
497 /* Dirty atom bitmask for fast tests */
498 uint64_t dirty_atoms;
499 /* States for CS initialization. */
500 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
501 /** Compute specific registers initializations. The start_cs_cmd atom
502 * must be emitted before start_compute_cs_cmd. */
503 struct r600_command_buffer start_compute_cs_cmd;
504 /* Register states. */
505 struct r600_alphatest_state alphatest_state;
506 struct r600_cso_state blend_state;
507 struct r600_blend_color blend_color;
508 struct r600_cb_misc_state cb_misc_state;
509 struct r600_clip_misc_state clip_misc_state;
510 struct r600_clip_state clip_state;
511 struct r600_db_misc_state db_misc_state;
512 struct r600_db_state db_state;
513 struct r600_cso_state dsa_state;
514 struct r600_framebuffer framebuffer;
515 struct r600_poly_offset_state poly_offset_state;
516 struct r600_cso_state rasterizer_state;
517 struct r600_sample_mask sample_mask;
518 struct r600_seamless_cube_map seamless_cube_map;
519 struct r600_config_state config_state;
520 struct r600_stencil_ref_state stencil_ref;
521 struct r600_vgt_state vgt_state;
522 struct r600_atomic_buffer_state atomic_buffer_state;
523 /* only have images on fragment shader */
524 struct r600_image_state fragment_images;
525 struct r600_image_state fragment_buffers;
526 /* Shaders and shader resources. */
527 struct r600_cso_state vertex_fetch_shader;
528 struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES];
529 struct r600_cs_shader_state cs_shader_state;
530 struct r600_shader_stages_state shader_stages;
531 struct r600_gs_rings_state gs_rings;
532 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
533 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
534
535 struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES];
536
537 /** Vertex buffers for fetch shaders */
538 struct r600_vertexbuf_state vertex_buffer_state;
539 /** Vertex buffers for compute shaders */
540 struct r600_vertexbuf_state cs_vertex_buffer_state;
541
542 /* Additional context states. */
543 unsigned compute_cb_target_mask;
544 struct r600_pipe_shader_selector *ps_shader;
545 struct r600_pipe_shader_selector *vs_shader;
546 struct r600_pipe_shader_selector *gs_shader;
547
548 struct r600_pipe_shader_selector *tcs_shader;
549 struct r600_pipe_shader_selector *tes_shader;
550
551 struct r600_pipe_shader_selector *fixed_func_tcs_shader;
552
553 struct r600_rasterizer_state *rasterizer;
554 bool alpha_to_one;
555 bool force_blend_disable;
556 bool gs_tri_strip_adj_fix;
557 boolean dual_src_blend;
558 unsigned zwritemask;
559 int ps_iter_samples;
560
561 /* The list of all texture buffer objects in this context.
562 * This list is walked when a buffer is invalidated/reallocated and
563 * the GPU addresses are updated. */
564 struct list_head texture_buffers;
565
566 /* Last draw state (-1 = unset). */
567 enum pipe_prim_type last_primitive_type; /* Last primitive type used in draw_vbo. */
568 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
569 enum pipe_prim_type last_rast_prim;
570 unsigned last_start_instance;
571
572 void *sb_context;
573 struct r600_isa *isa;
574 float sample_positions[4 * 16];
575 float tess_state[8];
576 bool tess_state_dirty;
577 struct r600_pipe_shader_selector *last_ls;
578 struct r600_pipe_shader_selector *last_tcs;
579 unsigned last_num_tcs_input_cp;
580 unsigned lds_alloc;
581
582 /* Debug state. */
583 bool is_debug;
584 struct radeon_saved_cs last_gfx;
585 struct r600_resource *last_trace_buf;
586 struct r600_resource *trace_buf;
587 unsigned trace_id;
588
589 struct pipe_resource *append_fence;
590 uint32_t append_fence_id;
591 };
592
593 static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
594 struct r600_command_buffer *cb)
595 {
596 assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw);
597 memcpy(cs->current.buf + cs->current.cdw, cb->buf, 4 * cb->num_dw);
598 cs->current.cdw += cb->num_dw;
599 }
600
601 static inline void r600_set_atom_dirty(struct r600_context *rctx,
602 struct r600_atom *atom,
603 bool dirty)
604 {
605 uint64_t mask;
606
607 assert(atom->id != 0);
608 assert(atom->id < sizeof(mask) * 8);
609 mask = 1ull << atom->id;
610 if (dirty)
611 rctx->dirty_atoms |= mask;
612 else
613 rctx->dirty_atoms &= ~mask;
614 }
615
616 static inline void r600_mark_atom_dirty(struct r600_context *rctx,
617 struct r600_atom *atom)
618 {
619 r600_set_atom_dirty(rctx, atom, true);
620 }
621
622 static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
623 {
624 atom->emit(&rctx->b, atom);
625 r600_set_atom_dirty(rctx, atom, false);
626 }
627
628 static inline void r600_set_cso_state(struct r600_context *rctx,
629 struct r600_cso_state *state, void *cso)
630 {
631 state->cso = cso;
632 r600_set_atom_dirty(rctx, &state->atom, cso != NULL);
633 }
634
635 static inline void r600_set_cso_state_with_cb(struct r600_context *rctx,
636 struct r600_cso_state *state, void *cso,
637 struct r600_command_buffer *cb)
638 {
639 state->cb = cb;
640 state->atom.num_dw = cb ? cb->num_dw : 0;
641 r600_set_cso_state(rctx, state, cso);
642 }
643
644 /* compute_memory_pool.c */
645 struct compute_memory_pool;
646 void compute_memory_pool_delete(struct compute_memory_pool* pool);
647 struct compute_memory_pool* compute_memory_pool_new(
648 struct r600_screen *rscreen);
649
650 /* evergreen_state.c */
651 struct pipe_sampler_view *
652 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
653 struct pipe_resource *texture,
654 const struct pipe_sampler_view *state,
655 unsigned width0, unsigned height0,
656 unsigned force_level);
657 void evergreen_init_common_regs(struct r600_context *ctx,
658 struct r600_command_buffer *cb,
659 enum chip_class ctx_chip_class,
660 enum radeon_family ctx_family,
661 int ctx_drm_minor);
662 void cayman_init_common_regs(struct r600_command_buffer *cb,
663 enum chip_class ctx_chip_class,
664 enum radeon_family ctx_family,
665 int ctx_drm_minor);
666
667 void evergreen_init_state_functions(struct r600_context *rctx);
668 void evergreen_init_atom_start_cs(struct r600_context *rctx);
669 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
670 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
671 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
672 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
673 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
674 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
675 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
676 void *evergreen_create_resolve_blend(struct r600_context *rctx);
677 void *evergreen_create_decompress_blend(struct r600_context *rctx);
678 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
679 boolean evergreen_is_format_supported(struct pipe_screen *screen,
680 enum pipe_format format,
681 enum pipe_texture_target target,
682 unsigned sample_count,
683 unsigned usage);
684 void evergreen_init_color_surface(struct r600_context *rctx,
685 struct r600_surface *surf);
686 void evergreen_init_color_surface_rat(struct r600_context *rctx,
687 struct r600_surface *surf);
688 void evergreen_update_db_shader_control(struct r600_context * rctx);
689 bool evergreen_adjust_gprs(struct r600_context *rctx);
690 /* r600_blit.c */
691 void r600_init_blit_functions(struct r600_context *rctx);
692 void r600_decompress_depth_textures(struct r600_context *rctx,
693 struct r600_samplerview_state *textures);
694 void r600_decompress_depth_images(struct r600_context *rctx,
695 struct r600_image_state *images);
696 void r600_decompress_color_textures(struct r600_context *rctx,
697 struct r600_samplerview_state *textures);
698 void r600_decompress_color_images(struct r600_context *rctx,
699 struct r600_image_state *images);
700 void r600_resource_copy_region(struct pipe_context *ctx,
701 struct pipe_resource *dst,
702 unsigned dst_level,
703 unsigned dstx, unsigned dsty, unsigned dstz,
704 struct pipe_resource *src,
705 unsigned src_level,
706 const struct pipe_box *src_box);
707
708 /* r600_shader.c */
709 int r600_pipe_shader_create(struct pipe_context *ctx,
710 struct r600_pipe_shader *shader,
711 union r600_shader_key key);
712
713 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
714
715 /* r600_state.c */
716 struct pipe_sampler_view *
717 r600_create_sampler_view_custom(struct pipe_context *ctx,
718 struct pipe_resource *texture,
719 const struct pipe_sampler_view *state,
720 unsigned width_first_level, unsigned height_first_level);
721 void r600_init_state_functions(struct r600_context *rctx);
722 void r600_init_atom_start_cs(struct r600_context *rctx);
723 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
724 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
725 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
726 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
727 void *r600_create_db_flush_dsa(struct r600_context *rctx);
728 void *r600_create_resolve_blend(struct r600_context *rctx);
729 void *r700_create_resolve_blend(struct r600_context *rctx);
730 void *r600_create_decompress_blend(struct r600_context *rctx);
731 bool r600_adjust_gprs(struct r600_context *rctx);
732 boolean r600_is_format_supported(struct pipe_screen *screen,
733 enum pipe_format format,
734 enum pipe_texture_target target,
735 unsigned sample_count,
736 unsigned usage);
737 void r600_update_db_shader_control(struct r600_context * rctx);
738
739 /* r600_hw_context.c */
740 void r600_context_gfx_flush(void *context, unsigned flags,
741 struct pipe_fence_handle **fence);
742 void r600_begin_new_cs(struct r600_context *ctx);
743 void r600_flush_emit(struct r600_context *ctx);
744 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
745 void r600_emit_pfp_sync_me(struct r600_context *rctx);
746 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
747 struct pipe_resource *dst, uint64_t dst_offset,
748 struct pipe_resource *src, uint64_t src_offset,
749 unsigned size);
750 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
751 struct pipe_resource *dst, uint64_t offset,
752 unsigned size, uint32_t clear_value,
753 enum r600_coherency coher);
754 void r600_dma_copy_buffer(struct r600_context *rctx,
755 struct pipe_resource *dst,
756 struct pipe_resource *src,
757 uint64_t dst_offset,
758 uint64_t src_offset,
759 uint64_t size);
760
761 /*
762 * evergreen_hw_context.c
763 */
764 void evergreen_dma_copy_buffer(struct r600_context *rctx,
765 struct pipe_resource *dst,
766 struct pipe_resource *src,
767 uint64_t dst_offset,
768 uint64_t src_offset,
769 uint64_t size);
770 void evergreen_setup_tess_constants(struct r600_context *rctx,
771 const struct pipe_draw_info *info,
772 unsigned *num_patches);
773 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
774 const struct pipe_draw_info *info,
775 unsigned num_patches);
776 void evergreen_set_ls_hs_config(struct r600_context *rctx,
777 struct radeon_winsys_cs *cs,
778 uint32_t ls_hs_config);
779 void evergreen_set_lds_alloc(struct r600_context *rctx,
780 struct radeon_winsys_cs *cs,
781 uint32_t lds_alloc);
782
783 /* r600_state_common.c */
784 void r600_init_common_state_functions(struct r600_context *rctx);
785 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
786 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
787 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
788 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
789 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
790 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
791 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
792 void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
793 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
794 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
795 unsigned num_dw);
796 void r600_vertex_buffers_dirty(struct r600_context *rctx);
797 void r600_sampler_views_dirty(struct r600_context *rctx,
798 struct r600_samplerview_state *state);
799 void r600_sampler_states_dirty(struct r600_context *rctx,
800 struct r600_sampler_states *state);
801 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
802 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
803 uint32_t r600_translate_stencil_op(int s_op);
804 uint32_t r600_translate_fill(uint32_t func);
805 unsigned r600_tex_wrap(unsigned wrap);
806 unsigned r600_tex_mipfilter(unsigned filter);
807 unsigned r600_tex_compare(unsigned compare);
808 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
809 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
810 const unsigned char *swizzle_view,
811 boolean vtx);
812 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
813 const unsigned char *swizzle_view,
814 uint32_t *word4_p, uint32_t *yuv_format_p,
815 bool do_endian_swap);
816 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format,
817 bool do_endian_swap);
818 uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap);
819
820 /* r600_uvd.c */
821 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
822 const struct pipe_video_codec *decoder);
823
824 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
825 const struct pipe_video_buffer *tmpl);
826
827 /*
828 * Helpers for building command buffers
829 */
830
831 #define PKT3_SET_CONFIG_REG 0x68
832 #define PKT3_SET_CONTEXT_REG 0x69
833 #define PKT3_SET_CTL_CONST 0x6F
834 #define PKT3_SET_LOOP_CONST 0x6C
835
836 #define R600_CONFIG_REG_OFFSET 0x08000
837 #define R600_CONTEXT_REG_OFFSET 0x28000
838 #define R600_CTL_CONST_OFFSET 0x3CFF0
839 #define R600_LOOP_CONST_OFFSET 0X0003E200
840 #define EG_LOOP_CONST_OFFSET 0x0003A200
841
842 #define PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30)
843 #define PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16)
844 #define PKT3_IT_OPCODE_S(x) (((unsigned)(x) & 0xFF) << 8)
845 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
846 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
847
848 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
849
850 /*Evergreen Compute packet3*/
851 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
852
853 static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value)
854 {
855 cb->buf[cb->num_dw++] = value;
856 }
857
858 static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
859 {
860 assert(cb->num_dw+num <= cb->max_num_dw);
861 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
862 cb->num_dw += num;
863 }
864
865 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
866 {
867 assert(reg < R600_CONTEXT_REG_OFFSET);
868 assert(cb->num_dw+2+num <= cb->max_num_dw);
869 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
870 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
871 }
872
873 /**
874 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
875 * shaders.
876 */
877 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
878 {
879 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
880 assert(cb->num_dw+2+num <= cb->max_num_dw);
881 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
882 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
883 }
884
885 /**
886 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
887 * shaders.
888 */
889 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
890 {
891 assert(reg >= R600_CTL_CONST_OFFSET);
892 assert(cb->num_dw+2+num <= cb->max_num_dw);
893 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
894 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
895 }
896
897 static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
898 {
899 assert(reg >= R600_LOOP_CONST_OFFSET);
900 assert(cb->num_dw+2+num <= cb->max_num_dw);
901 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
902 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
903 }
904
905 /**
906 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
907 * shaders.
908 */
909 static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
910 {
911 assert(reg >= EG_LOOP_CONST_OFFSET);
912 assert(cb->num_dw+2+num <= cb->max_num_dw);
913 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
914 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
915 }
916
917 static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
918 {
919 r600_store_config_reg_seq(cb, reg, 1);
920 r600_store_value(cb, value);
921 }
922
923 static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
924 {
925 r600_store_context_reg_seq(cb, reg, 1);
926 r600_store_value(cb, value);
927 }
928
929 static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
930 {
931 r600_store_ctl_const_seq(cb, reg, 1);
932 r600_store_value(cb, value);
933 }
934
935 static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
936 {
937 r600_store_loop_const_seq(cb, reg, 1);
938 r600_store_value(cb, value);
939 }
940
941 static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
942 {
943 eg_store_loop_const_seq(cb, reg, 1);
944 r600_store_value(cb, value);
945 }
946
947 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
948 void r600_release_command_buffer(struct r600_command_buffer *cb);
949
950 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
951 {
952 radeon_set_context_reg_seq(cs, reg, num);
953 /* Set the compute bit on the packet header */
954 cs->current.buf[cs->current.cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
955 }
956
957 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
958 {
959 assert(reg >= R600_CTL_CONST_OFFSET);
960 assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
961 radeon_emit(cs, PKT3(PKT3_SET_CTL_CONST, num, 0));
962 radeon_emit(cs, (reg - R600_CTL_CONST_OFFSET) >> 2);
963 }
964
965 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
966 {
967 radeon_compute_set_context_reg_seq(cs, reg, 1);
968 radeon_emit(cs, value);
969 }
970
971 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
972 {
973 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
974 radeon_compute_set_context_reg(cs, reg, value);
975 } else {
976 radeon_set_context_reg(cs, reg, value);
977 }
978 }
979
980 static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
981 {
982 radeon_set_ctl_const_seq(cs, reg, 1);
983 radeon_emit(cs, value);
984 }
985
986 /*
987 * common helpers
988 */
989
990 /* 12.4 fixed-point */
991 static inline unsigned r600_pack_float_12p4(float x)
992 {
993 return x <= 0 ? 0 :
994 x >= 4096 ? 0xffff : x * 16;
995 }
996
997 static inline unsigned r600_get_flush_flags(enum r600_coherency coher)
998 {
999 switch (coher) {
1000 default:
1001 case R600_COHERENCY_NONE:
1002 return 0;
1003 case R600_COHERENCY_SHADER:
1004 return R600_CONTEXT_INV_CONST_CACHE |
1005 R600_CONTEXT_INV_VERTEX_CACHE |
1006 R600_CONTEXT_INV_TEX_CACHE |
1007 R600_CONTEXT_STREAMOUT_FLUSH;
1008 case R600_COHERENCY_CB_META:
1009 return R600_CONTEXT_FLUSH_AND_INV_CB |
1010 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1011 }
1012 }
1013
1014 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
1015 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
1016 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
1017
1018 unsigned r600_conv_prim_to_gs_out(unsigned mode);
1019
1020 void eg_trace_emit(struct r600_context *rctx);
1021 void eg_dump_debug_state(struct pipe_context *ctx, FILE *f,
1022 unsigned flags);
1023
1024 struct r600_shader_atomic;
1025 bool evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
1026 struct r600_shader_atomic *combined_atomics,
1027 uint8_t *atomic_used_mask_p);
1028 void evergreen_emit_atomic_buffer_save(struct r600_context *rctx,
1029 struct r600_shader_atomic *combined_atomics,
1030 uint8_t *atomic_used_mask_p);
1031
1032 #endif