2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "../radeon/r600_pipe_common.h"
30 #include "../radeon/r600_cs.h"
32 #include "r600_llvm.h"
33 #include "r600_public.h"
35 #include "util/u_blitter.h"
36 #include "util/u_suballoc.h"
37 #include "util/u_double_list.h"
38 #include "util/u_transfer.h"
40 #define R600_NUM_ATOMS 72
42 /* the number of CS dwords for flushing and drawing */
43 #define R600_MAX_FLUSH_CS_DWORDS 16
44 #define R600_MAX_DRAW_CS_DWORDS 34
45 #define R600_TRACE_CS_DWORDS 7
47 #define R600_MAX_USER_CONST_BUFFERS 13
48 #define R600_MAX_DRIVER_CONST_BUFFERS 4
49 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
51 /* start driver buffers after user buffers */
52 #define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
53 #define R600_TXQ_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
54 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
55 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 3)
57 #define R600_MAX_CONST_BUFFER_SIZE 4096
59 #ifdef PIPE_ARCH_BIG_ENDIAN
60 #define R600_BIG_ENDIAN 1
62 #define R600_BIG_ENDIAN 0
67 struct r600_shader_key
;
69 /* This is an atom containing GPU commands that never change.
70 * This is supposed to be copied directly into the CS. */
71 struct r600_command_buffer
{
78 struct r600_db_state
{
79 struct r600_atom atom
;
80 struct r600_surface
*rsurf
;
83 struct r600_db_misc_state
{
84 struct r600_atom atom
;
85 bool occlusion_query_enabled
;
86 bool flush_depthstencil_through_cb
;
87 bool flush_depthstencil_in_place
;
88 bool copy_depth
, copy_stencil
;
91 unsigned db_shader_control
;
95 struct r600_cb_misc_state
{
96 struct r600_atom atom
;
97 unsigned cb_color_control
; /* this comes from blend state */
98 unsigned blend_colormask
; /* 8*4 bits for 8 RGBA colorbuffers */
100 unsigned nr_ps_color_outputs
;
105 struct r600_clip_misc_state
{
106 struct r600_atom atom
;
107 unsigned pa_cl_clip_cntl
; /* from rasterizer */
108 unsigned pa_cl_vs_out_cntl
; /* from vertex shader */
109 unsigned clip_plane_enable
; /* from rasterizer */
110 unsigned clip_dist_write
; /* from vertex shader */
113 struct r600_alphatest_state
{
114 struct r600_atom atom
;
115 unsigned sx_alpha_test_control
; /* this comes from dsa state */
116 unsigned sx_alpha_ref
; /* this comes from dsa state */
118 bool cb0_export_16bpc
; /* from set_framebuffer_state */
121 struct r600_vgt_state
{
122 struct r600_atom atom
;
123 uint32_t vgt_multi_prim_ib_reset_en
;
124 uint32_t vgt_multi_prim_ib_reset_indx
;
125 uint32_t vgt_indx_offset
;
128 struct r600_blend_color
{
129 struct r600_atom atom
;
130 struct pipe_blend_color state
;
133 struct r600_clip_state
{
134 struct r600_atom atom
;
135 struct pipe_clip_state state
;
138 struct r600_cs_shader_state
{
139 struct r600_atom atom
;
140 unsigned kernel_index
;
141 struct r600_pipe_compute
*shader
;
144 struct r600_framebuffer
{
145 struct r600_atom atom
;
146 struct pipe_framebuffer_state state
;
147 unsigned compressed_cb_mask
;
151 bool is_msaa_resolve
;
154 struct r600_sample_mask
{
155 struct r600_atom atom
;
156 uint16_t sample_mask
; /* there are only 8 bits on EG, 16 bits on Cayman */
159 struct r600_config_state
{
160 struct r600_atom atom
;
161 unsigned sq_gpr_resource_mgmt_1
;
162 unsigned sq_gpr_resource_mgmt_2
;
165 struct r600_stencil_ref
172 struct r600_stencil_ref_state
{
173 struct r600_atom atom
;
174 struct r600_stencil_ref state
;
175 struct pipe_stencil_ref pipe_state
;
178 struct r600_viewport_state
{
179 struct r600_atom atom
;
180 struct pipe_viewport_state state
;
184 struct r600_shader_stages_state
{
185 struct r600_atom atom
;
186 unsigned geom_enable
;
189 struct r600_gs_rings_state
{
190 struct r600_atom atom
;
192 struct pipe_constant_buffer esgs_ring
;
193 struct pipe_constant_buffer gsvs_ring
;
196 /* This must start from 16. */
198 #define DBG_NO_LLVM (1 << 17)
199 #define DBG_NO_CP_DMA (1 << 18)
200 #define DBG_NO_ASYNC_DMA (1 << 19)
202 #define DBG_NO_SB (1 << 21)
203 #define DBG_SB_CS (1 << 22)
204 #define DBG_SB_DRY_RUN (1 << 23)
205 #define DBG_SB_STAT (1 << 24)
206 #define DBG_SB_DUMP (1 << 25)
207 #define DBG_SB_NO_FALLBACK (1 << 26)
208 #define DBG_SB_DISASM (1 << 27)
209 #define DBG_SB_SAFEMATH (1 << 28)
212 struct r600_common_screen b
;
214 bool has_compressed_msaa_texturing
;
216 /*for compute global memory binding, we allocate stuff here, instead of
218 * XXX: Not sure if this is the best place for global_pool. Also,
219 * it's not thread safe, so it won't work with multiple contexts. */
220 struct compute_memory_pool
*global_pool
;
223 struct r600_pipe_sampler_view
{
224 struct pipe_sampler_view base
;
225 struct r600_resource
*tex_resource
;
226 uint32_t tex_resource_words
[8];
227 bool skip_mip_address_reloc
;
230 struct r600_rasterizer_state
{
231 struct r600_command_buffer buffer
;
234 unsigned sprite_coord_enable
;
235 unsigned clip_plane_enable
;
236 unsigned pa_sc_line_stipple
;
237 unsigned pa_cl_clip_cntl
;
242 bool multisample_enable
;
245 struct r600_poly_offset_state
{
246 struct r600_atom atom
;
247 enum pipe_format zs_format
;
252 struct r600_blend_state
{
253 struct r600_command_buffer buffer
;
254 struct r600_command_buffer buffer_no_blend
;
255 unsigned cb_target_mask
;
256 unsigned cb_color_control
;
257 unsigned cb_color_control_no_blend
;
262 struct r600_dsa_state
{
263 struct r600_command_buffer buffer
;
268 unsigned sx_alpha_test_control
;
271 struct r600_pipe_shader
;
273 struct r600_pipe_shader_selector
{
274 struct r600_pipe_shader
*current
;
276 struct tgsi_token
*tokens
;
277 struct pipe_stream_output_info so
;
279 unsigned num_shaders
;
281 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
284 unsigned nr_ps_max_color_exports
;
287 struct r600_pipe_sampler_state
{
288 uint32_t tex_sampler_words
[3];
289 union pipe_color_union border_color
;
290 bool border_color_use
;
291 bool seamless_cube_map
;
294 /* needed for blitter save */
295 #define NUM_TEX_UNITS 16
297 struct r600_seamless_cube_map
{
298 struct r600_atom atom
;
302 struct r600_samplerview_state
{
303 struct r600_atom atom
;
304 struct r600_pipe_sampler_view
*views
[NUM_TEX_UNITS
];
305 uint32_t enabled_mask
;
307 uint32_t compressed_depthtex_mask
; /* which textures are depth */
308 uint32_t compressed_colortex_mask
;
309 boolean dirty_txq_constants
;
310 boolean dirty_buffer_constants
;
313 struct r600_sampler_states
{
314 struct r600_atom atom
;
315 struct r600_pipe_sampler_state
*states
[NUM_TEX_UNITS
];
316 uint32_t enabled_mask
;
318 uint32_t has_bordercolor_mask
; /* which states contain the border color */
321 struct r600_textures_info
{
322 struct r600_samplerview_state views
;
323 struct r600_sampler_states states
;
324 bool is_array_sampler
[NUM_TEX_UNITS
];
326 /* cube array txq workaround */
327 uint32_t *txq_constants
;
328 /* buffer related workarounds */
329 uint32_t *buffer_constants
;
332 struct r600_constbuf_state
334 struct r600_atom atom
;
335 struct pipe_constant_buffer cb
[PIPE_MAX_CONSTANT_BUFFERS
];
336 uint32_t enabled_mask
;
340 struct r600_vertexbuf_state
342 struct r600_atom atom
;
343 struct pipe_vertex_buffer vb
[PIPE_MAX_ATTRIBS
];
344 uint32_t enabled_mask
; /* non-NULL buffers */
348 /* CSO (constant state object, in other words, immutable state). */
349 struct r600_cso_state
351 struct r600_atom atom
;
352 void *cso
; /* e.g. r600_blend_state */
353 struct r600_command_buffer
*cb
;
356 struct r600_scissor_state
358 struct r600_atom atom
;
359 struct pipe_scissor_state scissor
;
360 bool enable
; /* r6xx only */
364 struct r600_fetch_shader
{
365 struct r600_resource
*buffer
;
369 struct r600_shader_state
{
370 struct r600_atom atom
;
371 struct r600_pipe_shader
*shader
;
374 struct r600_context
{
375 struct r600_common_context b
;
376 struct r600_screen
*screen
;
377 struct blitter_context
*blitter
;
378 struct u_suballocator
*allocator_fetch_shader
;
381 boolean has_vertex_cache
;
382 boolean keep_tiling_flags
;
383 unsigned default_ps_gprs
, default_vs_gprs
;
384 unsigned r6xx_num_clause_temp_gprs
;
386 /* Miscellaneous state objects. */
387 void *custom_dsa_flush
;
388 void *custom_blend_resolve
;
389 void *custom_blend_decompress
;
390 void *custom_blend_fastclear
;
391 /* With rasterizer discard, there doesn't have to be a pixel shader.
392 * In that case, we bind this one: */
393 void *dummy_pixel_shader
;
394 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
395 * bug where valid CMASK and FMASK are required to be present to avoid
396 * a hardlock in certain operations but aren't actually used
397 * for anything useful. */
398 struct r600_resource
*dummy_fmask
;
399 struct r600_resource
*dummy_cmask
;
401 /* State binding slots are here. */
402 struct r600_atom
*atoms
[R600_NUM_ATOMS
];
403 /* States for CS initialization. */
404 struct r600_command_buffer start_cs_cmd
; /* invariant state mostly */
405 /** Compute specific registers initializations. The start_cs_cmd atom
406 * must be emitted before start_compute_cs_cmd. */
407 struct r600_command_buffer start_compute_cs_cmd
;
408 /* Register states. */
409 struct r600_alphatest_state alphatest_state
;
410 struct r600_cso_state blend_state
;
411 struct r600_blend_color blend_color
;
412 struct r600_cb_misc_state cb_misc_state
;
413 struct r600_clip_misc_state clip_misc_state
;
414 struct r600_clip_state clip_state
;
415 struct r600_db_misc_state db_misc_state
;
416 struct r600_db_state db_state
;
417 struct r600_cso_state dsa_state
;
418 struct r600_framebuffer framebuffer
;
419 struct r600_poly_offset_state poly_offset_state
;
420 struct r600_cso_state rasterizer_state
;
421 struct r600_sample_mask sample_mask
;
422 struct r600_scissor_state scissor
[16];
423 struct r600_seamless_cube_map seamless_cube_map
;
424 struct r600_config_state config_state
;
425 struct r600_stencil_ref_state stencil_ref
;
426 struct r600_vgt_state vgt_state
;
427 struct r600_viewport_state viewport
[16];
428 /* Shaders and shader resources. */
429 struct r600_cso_state vertex_fetch_shader
;
430 struct r600_shader_state vertex_shader
;
431 struct r600_shader_state pixel_shader
;
432 struct r600_shader_state geometry_shader
;
433 struct r600_shader_state export_shader
;
434 struct r600_cs_shader_state cs_shader_state
;
435 struct r600_shader_stages_state shader_stages
;
436 struct r600_gs_rings_state gs_rings
;
437 struct r600_constbuf_state constbuf_state
[PIPE_SHADER_TYPES
];
438 struct r600_textures_info samplers
[PIPE_SHADER_TYPES
];
439 /** Vertex buffers for fetch shaders */
440 struct r600_vertexbuf_state vertex_buffer_state
;
441 /** Vertex buffers for compute shaders */
442 struct r600_vertexbuf_state cs_vertex_buffer_state
;
444 /* Additional context states. */
445 unsigned compute_cb_target_mask
;
446 struct r600_pipe_shader_selector
*ps_shader
;
447 struct r600_pipe_shader_selector
*vs_shader
;
448 struct r600_pipe_shader_selector
*gs_shader
;
449 struct r600_rasterizer_state
*rasterizer
;
451 bool force_blend_disable
;
452 boolean dual_src_blend
;
456 struct pipe_index_buffer index_buffer
;
458 /* Last draw state (-1 = unset). */
459 int last_primitive_type
; /* Last primitive type used in draw_vbo. */
460 int last_start_instance
;
463 struct r600_isa
*isa
;
466 static INLINE
void r600_emit_command_buffer(struct radeon_winsys_cs
*cs
,
467 struct r600_command_buffer
*cb
)
469 assert(cs
->cdw
+ cb
->num_dw
<= RADEON_MAX_CMDBUF_DWORDS
);
470 memcpy(cs
->buf
+ cs
->cdw
, cb
->buf
, 4 * cb
->num_dw
);
471 cs
->cdw
+= cb
->num_dw
;
474 void r600_trace_emit(struct r600_context
*rctx
);
476 static INLINE
void r600_emit_atom(struct r600_context
*rctx
, struct r600_atom
*atom
)
478 atom
->emit(&rctx
->b
, atom
);
480 if (rctx
->screen
->b
.trace_bo
) {
481 r600_trace_emit(rctx
);
485 static INLINE
void r600_set_cso_state(struct r600_cso_state
*state
, void *cso
)
488 state
->atom
.dirty
= cso
!= NULL
;
491 static INLINE
void r600_set_cso_state_with_cb(struct r600_cso_state
*state
, void *cso
,
492 struct r600_command_buffer
*cb
)
495 state
->atom
.num_dw
= cb
? cb
->num_dw
: 0;
496 r600_set_cso_state(state
, cso
);
499 /* compute_memory_pool.c */
500 struct compute_memory_pool
;
501 void compute_memory_pool_delete(struct compute_memory_pool
* pool
);
502 struct compute_memory_pool
* compute_memory_pool_new(
503 struct r600_screen
*rscreen
);
505 /* evergreen_compute.c */
506 void evergreen_set_cs_sampler_view(struct pipe_context
*ctx_
,
507 unsigned start_slot
, unsigned count
,
508 struct pipe_sampler_view
**views
);
510 /* evergreen_state.c */
511 struct pipe_sampler_view
*
512 evergreen_create_sampler_view_custom(struct pipe_context
*ctx
,
513 struct pipe_resource
*texture
,
514 const struct pipe_sampler_view
*state
,
515 unsigned width0
, unsigned height0
,
516 unsigned force_level
);
517 void evergreen_init_common_regs(struct r600_command_buffer
*cb
,
518 enum chip_class ctx_chip_class
,
519 enum radeon_family ctx_family
,
521 void cayman_init_common_regs(struct r600_command_buffer
*cb
,
522 enum chip_class ctx_chip_class
,
523 enum radeon_family ctx_family
,
526 void evergreen_init_state_functions(struct r600_context
*rctx
);
527 void evergreen_init_atom_start_cs(struct r600_context
*rctx
);
528 void evergreen_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
529 void evergreen_update_es_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
530 void evergreen_update_gs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
531 void evergreen_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
532 void *evergreen_create_db_flush_dsa(struct r600_context
*rctx
);
533 void *evergreen_create_resolve_blend(struct r600_context
*rctx
);
534 void *evergreen_create_decompress_blend(struct r600_context
*rctx
);
535 void *evergreen_create_fastclear_blend(struct r600_context
*rctx
);
536 boolean
evergreen_is_format_supported(struct pipe_screen
*screen
,
537 enum pipe_format format
,
538 enum pipe_texture_target target
,
539 unsigned sample_count
,
541 void evergreen_init_color_surface(struct r600_context
*rctx
,
542 struct r600_surface
*surf
);
543 void evergreen_init_color_surface_rat(struct r600_context
*rctx
,
544 struct r600_surface
*surf
);
545 void evergreen_update_db_shader_control(struct r600_context
* rctx
);
548 void r600_init_blit_functions(struct r600_context
*rctx
);
549 void r600_decompress_depth_textures(struct r600_context
*rctx
,
550 struct r600_samplerview_state
*textures
);
551 void r600_decompress_color_textures(struct r600_context
*rctx
,
552 struct r600_samplerview_state
*textures
);
555 int r600_pipe_shader_create(struct pipe_context
*ctx
,
556 struct r600_pipe_shader
*shader
,
557 struct r600_shader_key key
);
559 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
562 struct pipe_sampler_view
*
563 r600_create_sampler_view_custom(struct pipe_context
*ctx
,
564 struct pipe_resource
*texture
,
565 const struct pipe_sampler_view
*state
,
566 unsigned width_first_level
, unsigned height_first_level
);
567 void r600_init_state_functions(struct r600_context
*rctx
);
568 void r600_init_atom_start_cs(struct r600_context
*rctx
);
569 void r600_update_ps_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
570 void r600_update_es_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
571 void r600_update_gs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
572 void r600_update_vs_state(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
);
573 void *r600_create_db_flush_dsa(struct r600_context
*rctx
);
574 void *r600_create_resolve_blend(struct r600_context
*rctx
);
575 void *r700_create_resolve_blend(struct r600_context
*rctx
);
576 void *r600_create_decompress_blend(struct r600_context
*rctx
);
577 bool r600_adjust_gprs(struct r600_context
*rctx
);
578 boolean
r600_is_format_supported(struct pipe_screen
*screen
,
579 enum pipe_format format
,
580 enum pipe_texture_target target
,
581 unsigned sample_count
,
583 void r600_update_db_shader_control(struct r600_context
* rctx
);
585 /* r600_hw_context.c */
586 void r600_context_flush(struct r600_context
*ctx
, unsigned flags
);
587 void r600_begin_new_cs(struct r600_context
*ctx
);
588 void r600_flush_emit(struct r600_context
*ctx
);
589 void r600_need_cs_space(struct r600_context
*ctx
, unsigned num_dw
, boolean count_draw_in
);
590 void r600_need_dma_space(struct r600_context
*ctx
, unsigned num_dw
);
591 void r600_cp_dma_copy_buffer(struct r600_context
*rctx
,
592 struct pipe_resource
*dst
, uint64_t dst_offset
,
593 struct pipe_resource
*src
, uint64_t src_offset
,
595 void evergreen_cp_dma_clear_buffer(struct r600_context
*rctx
,
596 struct pipe_resource
*dst
, uint64_t offset
,
597 unsigned size
, uint32_t clear_value
);
598 void r600_dma_copy(struct r600_context
*rctx
,
599 struct pipe_resource
*dst
,
600 struct pipe_resource
*src
,
606 * evergreen_hw_context.c
608 void evergreen_dma_copy(struct r600_context
*rctx
,
609 struct pipe_resource
*dst
,
610 struct pipe_resource
*src
,
615 /* r600_state_common.c */
616 void r600_init_common_state_functions(struct r600_context
*rctx
);
617 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
618 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
619 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
);
620 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
621 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
622 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
);
623 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
);
624 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
);
625 void r600_init_atom(struct r600_context
*rctx
, struct r600_atom
*atom
, unsigned id
,
626 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
628 void r600_vertex_buffers_dirty(struct r600_context
*rctx
);
629 void r600_sampler_views_dirty(struct r600_context
*rctx
,
630 struct r600_samplerview_state
*state
);
631 void r600_sampler_states_dirty(struct r600_context
*rctx
,
632 struct r600_sampler_states
*state
);
633 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
);
634 void r600_draw_rectangle(struct blitter_context
*blitter
,
635 int x1
, int y1
, int x2
, int y2
, float depth
,
636 enum blitter_attrib_type type
, const union pipe_color_union
*attrib
);
637 uint32_t r600_translate_stencil_op(int s_op
);
638 uint32_t r600_translate_fill(uint32_t func
);
639 unsigned r600_tex_wrap(unsigned wrap
);
640 unsigned r600_tex_filter(unsigned filter
);
641 unsigned r600_tex_mipfilter(unsigned filter
);
642 unsigned r600_tex_compare(unsigned compare
);
643 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
);
644 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
645 struct pipe_resource
*texture
,
646 const struct pipe_surface
*templ
,
647 unsigned width
, unsigned height
);
648 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
649 const unsigned char *swizzle_view
,
651 uint32_t r600_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
652 const unsigned char *swizzle_view
,
653 uint32_t *word4_p
, uint32_t *yuv_format_p
);
654 uint32_t r600_translate_colorformat(enum chip_class chip
, enum pipe_format format
);
655 uint32_t r600_colorformat_endian_swap(uint32_t colorformat
);
658 struct pipe_video_codec
*r600_uvd_create_decoder(struct pipe_context
*context
,
659 const struct pipe_video_codec
*decoder
);
661 struct pipe_video_buffer
*r600_video_buffer_create(struct pipe_context
*pipe
,
662 const struct pipe_video_buffer
*tmpl
);
665 * Helpers for building command buffers
668 #define PKT3_SET_CONFIG_REG 0x68
669 #define PKT3_SET_CONTEXT_REG 0x69
670 #define PKT3_SET_CTL_CONST 0x6F
671 #define PKT3_SET_LOOP_CONST 0x6C
673 #define R600_CONFIG_REG_OFFSET 0x08000
674 #define R600_CONTEXT_REG_OFFSET 0x28000
675 #define R600_CTL_CONST_OFFSET 0x3CFF0
676 #define R600_LOOP_CONST_OFFSET 0X0003E200
677 #define EG_LOOP_CONST_OFFSET 0x0003A200
679 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
680 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
681 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
682 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
683 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
685 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
687 /*Evergreen Compute packet3*/
688 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
690 static INLINE
void r600_store_value(struct r600_command_buffer
*cb
, unsigned value
)
692 cb
->buf
[cb
->num_dw
++] = value
;
695 static INLINE
void r600_store_array(struct r600_command_buffer
*cb
, unsigned num
, unsigned *ptr
)
697 assert(cb
->num_dw
+num
<= cb
->max_num_dw
);
698 memcpy(&cb
->buf
[cb
->num_dw
], ptr
, num
* sizeof(ptr
[0]));
702 static INLINE
void r600_store_config_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
704 assert(reg
< R600_CONTEXT_REG_OFFSET
);
705 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
706 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CONFIG_REG
, num
, 0);
707 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CONFIG_REG_OFFSET
) >> 2;
711 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
714 static INLINE
void r600_store_context_reg_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
716 assert(reg
>= R600_CONTEXT_REG_OFFSET
&& reg
< R600_CTL_CONST_OFFSET
);
717 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
718 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CONTEXT_REG
, num
, 0) | cb
->pkt_flags
;
719 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CONTEXT_REG_OFFSET
) >> 2;
723 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
726 static INLINE
void r600_store_ctl_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
728 assert(reg
>= R600_CTL_CONST_OFFSET
);
729 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
730 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0) | cb
->pkt_flags
;
731 cb
->buf
[cb
->num_dw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
734 static INLINE
void r600_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
736 assert(reg
>= R600_LOOP_CONST_OFFSET
);
737 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
738 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0);
739 cb
->buf
[cb
->num_dw
++] = (reg
- R600_LOOP_CONST_OFFSET
) >> 2;
743 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
746 static INLINE
void eg_store_loop_const_seq(struct r600_command_buffer
*cb
, unsigned reg
, unsigned num
)
748 assert(reg
>= EG_LOOP_CONST_OFFSET
);
749 assert(cb
->num_dw
+2+num
<= cb
->max_num_dw
);
750 cb
->buf
[cb
->num_dw
++] = PKT3(PKT3_SET_LOOP_CONST
, num
, 0) | cb
->pkt_flags
;
751 cb
->buf
[cb
->num_dw
++] = (reg
- EG_LOOP_CONST_OFFSET
) >> 2;
754 static INLINE
void r600_store_config_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
756 r600_store_config_reg_seq(cb
, reg
, 1);
757 r600_store_value(cb
, value
);
760 static INLINE
void r600_store_context_reg(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
762 r600_store_context_reg_seq(cb
, reg
, 1);
763 r600_store_value(cb
, value
);
766 static INLINE
void r600_store_ctl_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
768 r600_store_ctl_const_seq(cb
, reg
, 1);
769 r600_store_value(cb
, value
);
772 static INLINE
void r600_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
774 r600_store_loop_const_seq(cb
, reg
, 1);
775 r600_store_value(cb
, value
);
778 static INLINE
void eg_store_loop_const(struct r600_command_buffer
*cb
, unsigned reg
, unsigned value
)
780 eg_store_loop_const_seq(cb
, reg
, 1);
781 r600_store_value(cb
, value
);
784 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
);
785 void r600_release_command_buffer(struct r600_command_buffer
*cb
);
787 static INLINE
void r600_write_compute_context_reg_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
789 r600_write_context_reg_seq(cs
, reg
, num
);
790 /* Set the compute bit on the packet header */
791 cs
->buf
[cs
->cdw
- 2] |= RADEON_CP_PACKET3_COMPUTE_MODE
;
794 static INLINE
void r600_write_ctl_const_seq(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned num
)
796 assert(reg
>= R600_CTL_CONST_OFFSET
);
797 assert(cs
->cdw
+2+num
<= RADEON_MAX_CMDBUF_DWORDS
);
798 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_SET_CTL_CONST
, num
, 0);
799 cs
->buf
[cs
->cdw
++] = (reg
- R600_CTL_CONST_OFFSET
) >> 2;
802 static INLINE
void r600_write_compute_context_reg(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
804 r600_write_compute_context_reg_seq(cs
, reg
, 1);
805 radeon_emit(cs
, value
);
808 static INLINE
void r600_write_context_reg_flag(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
, unsigned flag
)
810 if (flag
& RADEON_CP_PACKET3_COMPUTE_MODE
) {
811 r600_write_compute_context_reg(cs
, reg
, value
);
813 r600_write_context_reg(cs
, reg
, value
);
817 static INLINE
void r600_write_ctl_const(struct radeon_winsys_cs
*cs
, unsigned reg
, unsigned value
)
819 r600_write_ctl_const_seq(cs
, reg
, 1);
820 radeon_emit(cs
, value
);
826 static INLINE
uint32_t S_FIXED(float value
, uint32_t frac_bits
)
828 return value
* (1 << frac_bits
);
830 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
832 static inline unsigned r600_tex_aniso_filter(unsigned filter
)
834 if (filter
<= 1) return 0;
835 if (filter
<= 2) return 1;
836 if (filter
<= 4) return 2;
837 if (filter
<= 8) return 3;
841 /* 12.4 fixed-point */
842 static INLINE
unsigned r600_pack_float_12p4(float x
)
845 x
>= 4096 ? 0xffff : x
* 16;
848 /* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */
849 static INLINE
bool r600_can_read_depth(struct r600_texture
*rtex
)
851 return rtex
->resource
.b
.b
.nr_samples
<= 1 &&
852 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
853 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
);