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r600/atomic: fix ATOMCAS instruction.
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "r600_pipe_common.h"
30 #include "r600_cs.h"
31 #include "r600_public.h"
32 #include "pipe/p_defines.h"
33
34 #include "util/u_suballoc.h"
35 #include "util/list.h"
36 #include "util/u_transfer.h"
37 #include "util/u_memory.h"
38
39 #include "tgsi/tgsi_scan.h"
40
41 #define R600_NUM_ATOMS 56
42
43 #define R600_MAX_IMAGES 8
44 /*
45 * ranges reserved for images on evergreen
46 * first set for the immediate buffers,
47 * second for the actual resources for RESQ.
48 */
49 #define R600_IMAGE_IMMED_RESOURCE_OFFSET 160
50 #define R600_IMAGE_REAL_RESOURCE_OFFSET 168
51
52 /* read caches */
53 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
54 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
55 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
56 /* read-write caches */
57 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
58 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
59 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
60 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
61 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
62 /* engine synchronization */
63 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
64 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
65 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
66 #define R600_CONTEXT_CS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 11)
67
68 /* the number of CS dwords for flushing and drawing */
69 #define R600_MAX_FLUSH_CS_DWORDS 18
70 #define R600_MAX_DRAW_CS_DWORDS 58
71 #define R600_MAX_PFP_SYNC_ME_DWORDS 16
72
73 #define EG_MAX_ATOMIC_BUFFERS 8
74
75 #define R600_MAX_USER_CONST_BUFFERS 15
76 #define R600_MAX_DRIVER_CONST_BUFFERS 3
77 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
78 #define R600_MAX_HW_CONST_BUFFERS 16
79
80 /* start driver buffers after user buffers */
81 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
82 #define R600_UCP_SIZE (4*4*8)
83 #define R600_CS_BLOCK_GRID_SIZE (8 * 4)
84 #define R600_TCS_DEFAULT_LEVELS_SIZE (6 * 4)
85 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
86
87 /*
88 * We only access this buffer through vtx clauses hence it's fine to exist
89 * at index beyond 15.
90 */
91 #define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
92 /*
93 * Note GS doesn't use a constant buffer binding, just a resource index,
94 * so it's fine to have it exist at index beyond 15. I.e. it's not actually
95 * a const buffer, just a buffer resource.
96 */
97 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
98 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
99 * of 16 const buffers.
100 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
101 *
102 * In order to support d3d 11 mandated minimum of 15 user const buffers
103 * we'd have to squash all use cases into one driver buffer.
104 */
105 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
106
107 /* HW stages */
108 #define R600_HW_STAGE_PS 0
109 #define R600_HW_STAGE_VS 1
110 #define R600_HW_STAGE_GS 2
111 #define R600_HW_STAGE_ES 3
112 #define EG_HW_STAGE_LS 4
113 #define EG_HW_STAGE_HS 5
114
115 #define R600_NUM_HW_STAGES 4
116 #define EG_NUM_HW_STAGES 6
117
118 struct r600_context;
119 struct r600_bytecode;
120 union r600_shader_key;
121
122 /* This is an atom containing GPU commands that never change.
123 * This is supposed to be copied directly into the CS. */
124 struct r600_command_buffer {
125 uint32_t *buf;
126 unsigned num_dw;
127 unsigned max_num_dw;
128 unsigned pkt_flags;
129 };
130
131 struct r600_db_state {
132 struct r600_atom atom;
133 struct r600_surface *rsurf;
134 };
135
136 struct r600_db_misc_state {
137 struct r600_atom atom;
138 bool occlusion_queries_disabled;
139 bool flush_depthstencil_through_cb;
140 bool flush_depth_inplace;
141 bool flush_stencil_inplace;
142 bool copy_depth, copy_stencil;
143 unsigned copy_sample;
144 unsigned log_samples;
145 unsigned db_shader_control;
146 bool htile_clear;
147 uint8_t ps_conservative_z;
148 };
149
150 struct r600_cb_misc_state {
151 struct r600_atom atom;
152 unsigned cb_color_control; /* this comes from blend state */
153 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
154 unsigned nr_cbufs;
155 unsigned nr_ps_color_outputs;
156 unsigned image_rat_enabled_mask;
157 unsigned buffer_rat_enabled_mask;
158 bool multiwrite;
159 bool dual_src_blend;
160 };
161
162 struct r600_clip_misc_state {
163 struct r600_atom atom;
164 unsigned pa_cl_clip_cntl; /* from rasterizer */
165 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
166 unsigned clip_plane_enable; /* from rasterizer */
167 unsigned cc_dist_mask; /* from vertex shader */
168 unsigned clip_dist_write; /* from vertex shader */
169 unsigned cull_dist_write; /* from vertex shader */
170 boolean clip_disable; /* from vertex shader */
171 boolean vs_out_viewport; /* from vertex shader */
172 };
173
174 struct r600_alphatest_state {
175 struct r600_atom atom;
176 unsigned sx_alpha_test_control; /* this comes from dsa state */
177 unsigned sx_alpha_ref; /* this comes from dsa state */
178 bool bypass;
179 bool cb0_export_16bpc; /* from set_framebuffer_state */
180 };
181
182 struct r600_vgt_state {
183 struct r600_atom atom;
184 uint32_t vgt_multi_prim_ib_reset_en;
185 uint32_t vgt_multi_prim_ib_reset_indx;
186 uint32_t vgt_indx_offset;
187 bool last_draw_was_indirect;
188 };
189
190 struct r600_blend_color {
191 struct r600_atom atom;
192 struct pipe_blend_color state;
193 };
194
195 struct r600_clip_state {
196 struct r600_atom atom;
197 struct pipe_clip_state state;
198 };
199
200 struct r600_cs_shader_state {
201 struct r600_atom atom;
202 unsigned kernel_index;
203 unsigned pc;
204 struct r600_pipe_compute *shader;
205 };
206
207 struct r600_framebuffer {
208 struct r600_atom atom;
209 struct pipe_framebuffer_state state;
210 unsigned compressed_cb_mask;
211 unsigned nr_samples;
212 bool export_16bpc;
213 bool cb0_is_integer;
214 bool is_msaa_resolve;
215 bool dual_src_blend;
216 bool do_update_surf_dirtiness;
217 };
218
219 struct r600_sample_mask {
220 struct r600_atom atom;
221 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
222 };
223
224 struct r600_config_state {
225 struct r600_atom atom;
226 unsigned sq_gpr_resource_mgmt_1;
227 unsigned sq_gpr_resource_mgmt_2;
228 unsigned sq_gpr_resource_mgmt_3;
229 bool dyn_gpr_enabled;
230 };
231
232 struct r600_stencil_ref
233 {
234 ubyte ref_value[2];
235 ubyte valuemask[2];
236 ubyte writemask[2];
237 };
238
239 struct r600_stencil_ref_state {
240 struct r600_atom atom;
241 struct r600_stencil_ref state;
242 struct pipe_stencil_ref pipe_state;
243 };
244
245 struct r600_shader_stages_state {
246 struct r600_atom atom;
247 unsigned geom_enable;
248 };
249
250 struct r600_gs_rings_state {
251 struct r600_atom atom;
252 unsigned enable;
253 struct pipe_constant_buffer esgs_ring;
254 struct pipe_constant_buffer gsvs_ring;
255 };
256
257 /* This must start from 16. */
258 /* features */
259 #define DBG_NO_CP_DMA (1 << 30)
260 /* shader backend */
261 #define DBG_NO_SB (1 << 21)
262 #define DBG_SB_CS (1 << 22)
263 #define DBG_SB_DRY_RUN (1 << 23)
264 #define DBG_SB_STAT (1 << 24)
265 #define DBG_SB_DUMP (1 << 25)
266 #define DBG_SB_NO_FALLBACK (1 << 26)
267 #define DBG_SB_DISASM (1 << 27)
268 #define DBG_SB_SAFEMATH (1 << 28)
269
270 struct r600_screen {
271 struct r600_common_screen b;
272 bool has_msaa;
273 bool has_compressed_msaa_texturing;
274 bool has_atomics;
275
276 /*for compute global memory binding, we allocate stuff here, instead of
277 * buffers.
278 * XXX: Not sure if this is the best place for global_pool. Also,
279 * it's not thread safe, so it won't work with multiple contexts. */
280 struct compute_memory_pool *global_pool;
281 };
282
283 struct r600_pipe_sampler_view {
284 struct pipe_sampler_view base;
285 struct list_head list;
286 struct r600_resource *tex_resource;
287 uint32_t tex_resource_words[8];
288 bool skip_mip_address_reloc;
289 bool is_stencil_sampler;
290 };
291
292 struct r600_rasterizer_state {
293 struct r600_command_buffer buffer;
294 boolean flatshade;
295 boolean two_side;
296 unsigned sprite_coord_enable;
297 unsigned clip_plane_enable;
298 unsigned pa_sc_line_stipple;
299 unsigned pa_cl_clip_cntl;
300 unsigned pa_su_sc_mode_cntl;
301 float offset_units;
302 float offset_scale;
303 bool offset_enable;
304 bool offset_units_unscaled;
305 bool scissor_enable;
306 bool multisample_enable;
307 bool clip_halfz;
308 bool rasterizer_discard;
309 };
310
311 struct r600_poly_offset_state {
312 struct r600_atom atom;
313 enum pipe_format zs_format;
314 float offset_units;
315 float offset_scale;
316 bool offset_units_unscaled;
317 };
318
319 struct r600_blend_state {
320 struct r600_command_buffer buffer;
321 struct r600_command_buffer buffer_no_blend;
322 unsigned cb_target_mask;
323 unsigned cb_color_control;
324 unsigned cb_color_control_no_blend;
325 bool dual_src_blend;
326 bool alpha_to_one;
327 };
328
329 struct r600_dsa_state {
330 struct r600_command_buffer buffer;
331 unsigned alpha_ref;
332 ubyte valuemask[2];
333 ubyte writemask[2];
334 unsigned zwritemask;
335 unsigned sx_alpha_test_control;
336 };
337
338 struct r600_pipe_shader;
339
340 struct r600_pipe_shader_selector {
341 struct r600_pipe_shader *current;
342
343 struct tgsi_token *tokens;
344 struct pipe_stream_output_info so;
345 struct tgsi_shader_info info;
346
347 unsigned num_shaders;
348
349 enum pipe_shader_type type;
350
351 /* geometry shader properties */
352 enum pipe_prim_type gs_output_prim;
353 unsigned gs_max_out_vertices;
354 unsigned gs_num_invocations;
355
356 /* TCS/VS */
357 uint64_t lds_patch_outputs_written_mask;
358 uint64_t lds_outputs_written_mask;
359 unsigned nr_ps_max_color_exports;
360 };
361
362 struct r600_pipe_sampler_state {
363 uint32_t tex_sampler_words[3];
364 union pipe_color_union border_color;
365 bool border_color_use;
366 bool seamless_cube_map;
367 };
368
369 /* needed for blitter save */
370 #define NUM_TEX_UNITS 16
371
372 struct r600_seamless_cube_map {
373 struct r600_atom atom;
374 bool enabled;
375 };
376
377 struct r600_samplerview_state {
378 struct r600_atom atom;
379 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
380 uint32_t enabled_mask;
381 uint32_t dirty_mask;
382 uint32_t compressed_depthtex_mask; /* which textures are depth */
383 uint32_t compressed_colortex_mask;
384 boolean dirty_buffer_constants;
385 };
386
387 struct r600_sampler_states {
388 struct r600_atom atom;
389 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
390 uint32_t enabled_mask;
391 uint32_t dirty_mask;
392 uint32_t has_bordercolor_mask; /* which states contain the border color */
393 };
394
395 struct r600_textures_info {
396 struct r600_samplerview_state views;
397 struct r600_sampler_states states;
398 bool is_array_sampler[NUM_TEX_UNITS];
399 };
400
401 struct r600_shader_driver_constants_info {
402 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
403 uint32_t *constants;
404 uint32_t alloc_size;
405 bool texture_const_dirty;
406 bool vs_ucp_dirty;
407 bool ps_sample_pos_dirty;
408 bool cs_block_grid_size_dirty;
409 bool tcs_default_levels_dirty;
410 };
411
412 struct r600_constbuf_state
413 {
414 struct r600_atom atom;
415 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
416 uint32_t enabled_mask;
417 uint32_t dirty_mask;
418 };
419
420 struct r600_vertexbuf_state
421 {
422 struct r600_atom atom;
423 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
424 uint32_t enabled_mask; /* non-NULL buffers */
425 uint32_t dirty_mask;
426 };
427
428 /* CSO (constant state object, in other words, immutable state). */
429 struct r600_cso_state
430 {
431 struct r600_atom atom;
432 void *cso; /* e.g. r600_blend_state */
433 struct r600_command_buffer *cb;
434 };
435
436 struct r600_fetch_shader {
437 struct r600_resource *buffer;
438 unsigned offset;
439 };
440
441 struct r600_shader_state {
442 struct r600_atom atom;
443 struct r600_pipe_shader *shader;
444 };
445
446 struct r600_atomic_buffer_state {
447 uint32_t enabled_mask;
448 uint32_t dirty_mask;
449 struct pipe_shader_buffer buffer[EG_MAX_ATOMIC_BUFFERS];
450 };
451
452 struct r600_image_view {
453 struct pipe_image_view base;
454 uint32_t cb_color_base;
455 uint32_t cb_color_pitch;
456 uint32_t cb_color_slice;
457 uint32_t cb_color_view;
458 uint32_t cb_color_info;
459 uint32_t cb_color_attrib;
460 uint32_t cb_color_dim;
461 uint32_t cb_color_fmask;
462 uint32_t cb_color_fmask_slice;
463 uint32_t immed_resource_words[8];
464 uint32_t resource_words[8];
465 bool skip_mip_address_reloc;
466 uint32_t buf_size;
467 };
468
469 struct r600_image_state {
470 struct r600_atom atom;
471 uint32_t enabled_mask;
472 uint32_t dirty_mask;
473 uint32_t compressed_depthtex_mask;
474 uint32_t compressed_colortex_mask;
475 boolean dirty_buffer_constants;
476 struct r600_image_view views[R600_MAX_IMAGES];
477 };
478
479 struct r600_context {
480 struct r600_common_context b;
481 struct r600_screen *screen;
482 struct blitter_context *blitter;
483 struct u_suballocator *allocator_fetch_shader;
484
485 /* Hardware info. */
486 boolean has_vertex_cache;
487 unsigned default_gprs[EG_NUM_HW_STAGES];
488 unsigned current_gprs[EG_NUM_HW_STAGES];
489 unsigned r6xx_num_clause_temp_gprs;
490
491 /* Miscellaneous state objects. */
492 void *custom_dsa_flush;
493 void *custom_blend_resolve;
494 void *custom_blend_decompress;
495 void *custom_blend_fastclear;
496 /* With rasterizer discard, there doesn't have to be a pixel shader.
497 * In that case, we bind this one: */
498 void *dummy_pixel_shader;
499 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
500 * bug where valid CMASK and FMASK are required to be present to avoid
501 * a hardlock in certain operations but aren't actually used
502 * for anything useful. */
503 struct r600_resource *dummy_fmask;
504 struct r600_resource *dummy_cmask;
505
506 /* State binding slots are here. */
507 struct r600_atom *atoms[R600_NUM_ATOMS];
508 /* Dirty atom bitmask for fast tests */
509 uint64_t dirty_atoms;
510 /* States for CS initialization. */
511 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
512 /** Compute specific registers initializations. The start_cs_cmd atom
513 * must be emitted before start_compute_cs_cmd. */
514 struct r600_command_buffer start_compute_cs_cmd;
515 /* Register states. */
516 struct r600_alphatest_state alphatest_state;
517 struct r600_cso_state blend_state;
518 struct r600_blend_color blend_color;
519 struct r600_cb_misc_state cb_misc_state;
520 struct r600_clip_misc_state clip_misc_state;
521 struct r600_clip_state clip_state;
522 struct r600_db_misc_state db_misc_state;
523 struct r600_db_state db_state;
524 struct r600_cso_state dsa_state;
525 struct r600_framebuffer framebuffer;
526 struct r600_poly_offset_state poly_offset_state;
527 struct r600_cso_state rasterizer_state;
528 struct r600_sample_mask sample_mask;
529 struct r600_seamless_cube_map seamless_cube_map;
530 struct r600_config_state config_state;
531 struct r600_stencil_ref_state stencil_ref;
532 struct r600_vgt_state vgt_state;
533 struct r600_atomic_buffer_state atomic_buffer_state;
534 /* only have images on fragment shader */
535 struct r600_image_state fragment_images;
536 struct r600_image_state compute_images;
537 struct r600_image_state fragment_buffers;
538 struct r600_image_state compute_buffers;
539 /* Shaders and shader resources. */
540 struct r600_cso_state vertex_fetch_shader;
541 struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES];
542 struct r600_cs_shader_state cs_shader_state;
543 struct r600_shader_stages_state shader_stages;
544 struct r600_gs_rings_state gs_rings;
545 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
546 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
547
548 struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES];
549
550 /** Vertex buffers for fetch shaders */
551 struct r600_vertexbuf_state vertex_buffer_state;
552 /** Vertex buffers for compute shaders */
553 struct r600_vertexbuf_state cs_vertex_buffer_state;
554
555 /* Additional context states. */
556 unsigned compute_cb_target_mask;
557 struct r600_pipe_shader_selector *ps_shader;
558 struct r600_pipe_shader_selector *vs_shader;
559 struct r600_pipe_shader_selector *gs_shader;
560
561 struct r600_pipe_shader_selector *tcs_shader;
562 struct r600_pipe_shader_selector *tes_shader;
563
564 struct r600_pipe_shader_selector *fixed_func_tcs_shader;
565
566 struct r600_rasterizer_state *rasterizer;
567 bool alpha_to_one;
568 bool force_blend_disable;
569 bool gs_tri_strip_adj_fix;
570 boolean dual_src_blend;
571 unsigned zwritemask;
572 int ps_iter_samples;
573
574 /* The list of all texture buffer objects in this context.
575 * This list is walked when a buffer is invalidated/reallocated and
576 * the GPU addresses are updated. */
577 struct list_head texture_buffers;
578
579 /* Last draw state (-1 = unset). */
580 enum pipe_prim_type last_primitive_type; /* Last primitive type used in draw_vbo. */
581 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
582 enum pipe_prim_type last_rast_prim;
583 unsigned last_start_instance;
584
585 void *sb_context;
586 struct r600_isa *isa;
587 float sample_positions[4 * 16];
588 float tess_state[8];
589 uint32_t cs_block_grid_sizes[8]; /* 3 for grid + 1 pad, 3 for block + 1 pad*/
590 struct r600_pipe_shader_selector *last_ls;
591 struct r600_pipe_shader_selector *last_tcs;
592 unsigned last_num_tcs_input_cp;
593 unsigned lds_alloc;
594
595 /* Debug state. */
596 bool is_debug;
597 struct radeon_saved_cs last_gfx;
598 struct r600_resource *last_trace_buf;
599 struct r600_resource *trace_buf;
600 unsigned trace_id;
601
602 bool cmd_buf_is_compute;
603 struct pipe_resource *append_fence;
604 uint32_t append_fence_id;
605 };
606
607 static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
608 struct r600_command_buffer *cb)
609 {
610 assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw);
611 memcpy(cs->current.buf + cs->current.cdw, cb->buf, 4 * cb->num_dw);
612 cs->current.cdw += cb->num_dw;
613 }
614
615 static inline void r600_set_atom_dirty(struct r600_context *rctx,
616 struct r600_atom *atom,
617 bool dirty)
618 {
619 uint64_t mask;
620
621 assert(atom->id != 0);
622 assert(atom->id < sizeof(mask) * 8);
623 mask = 1ull << atom->id;
624 if (dirty)
625 rctx->dirty_atoms |= mask;
626 else
627 rctx->dirty_atoms &= ~mask;
628 }
629
630 static inline void r600_mark_atom_dirty(struct r600_context *rctx,
631 struct r600_atom *atom)
632 {
633 r600_set_atom_dirty(rctx, atom, true);
634 }
635
636 static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
637 {
638 atom->emit(&rctx->b, atom);
639 r600_set_atom_dirty(rctx, atom, false);
640 }
641
642 static inline void r600_set_cso_state(struct r600_context *rctx,
643 struct r600_cso_state *state, void *cso)
644 {
645 state->cso = cso;
646 r600_set_atom_dirty(rctx, &state->atom, cso != NULL);
647 }
648
649 static inline void r600_set_cso_state_with_cb(struct r600_context *rctx,
650 struct r600_cso_state *state, void *cso,
651 struct r600_command_buffer *cb)
652 {
653 state->cb = cb;
654 state->atom.num_dw = cb ? cb->num_dw : 0;
655 r600_set_cso_state(rctx, state, cso);
656 }
657
658 /* compute_memory_pool.c */
659 struct compute_memory_pool;
660 void compute_memory_pool_delete(struct compute_memory_pool* pool);
661 struct compute_memory_pool* compute_memory_pool_new(
662 struct r600_screen *rscreen);
663
664 /* evergreen_state.c */
665 struct pipe_sampler_view *
666 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
667 struct pipe_resource *texture,
668 const struct pipe_sampler_view *state,
669 unsigned width0, unsigned height0,
670 unsigned force_level);
671 void evergreen_init_common_regs(struct r600_context *ctx,
672 struct r600_command_buffer *cb,
673 enum chip_class ctx_chip_class,
674 enum radeon_family ctx_family,
675 int ctx_drm_minor);
676 void cayman_init_common_regs(struct r600_command_buffer *cb,
677 enum chip_class ctx_chip_class,
678 enum radeon_family ctx_family,
679 int ctx_drm_minor);
680
681 void evergreen_init_state_functions(struct r600_context *rctx);
682 void evergreen_init_atom_start_cs(struct r600_context *rctx);
683 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
684 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
685 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
686 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
687 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
688 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
689 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
690 void *evergreen_create_resolve_blend(struct r600_context *rctx);
691 void *evergreen_create_decompress_blend(struct r600_context *rctx);
692 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
693 boolean evergreen_is_format_supported(struct pipe_screen *screen,
694 enum pipe_format format,
695 enum pipe_texture_target target,
696 unsigned sample_count,
697 unsigned usage);
698 void evergreen_init_color_surface(struct r600_context *rctx,
699 struct r600_surface *surf);
700 void evergreen_init_color_surface_rat(struct r600_context *rctx,
701 struct r600_surface *surf);
702 void evergreen_update_db_shader_control(struct r600_context * rctx);
703 bool evergreen_adjust_gprs(struct r600_context *rctx);
704
705 uint32_t evergreen_construct_rat_mask(struct r600_context *rctx, struct r600_cb_misc_state *a,
706 unsigned nr_cbufs);
707 /* r600_blit.c */
708 void r600_init_blit_functions(struct r600_context *rctx);
709 void r600_decompress_depth_textures(struct r600_context *rctx,
710 struct r600_samplerview_state *textures);
711 void r600_decompress_depth_images(struct r600_context *rctx,
712 struct r600_image_state *images);
713 void r600_decompress_color_textures(struct r600_context *rctx,
714 struct r600_samplerview_state *textures);
715 void r600_decompress_color_images(struct r600_context *rctx,
716 struct r600_image_state *images);
717 void r600_resource_copy_region(struct pipe_context *ctx,
718 struct pipe_resource *dst,
719 unsigned dst_level,
720 unsigned dstx, unsigned dsty, unsigned dstz,
721 struct pipe_resource *src,
722 unsigned src_level,
723 const struct pipe_box *src_box);
724
725 /* r600_shader.c */
726 int r600_pipe_shader_create(struct pipe_context *ctx,
727 struct r600_pipe_shader *shader,
728 union r600_shader_key key);
729
730 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
731
732 /* r600_state.c */
733 struct pipe_sampler_view *
734 r600_create_sampler_view_custom(struct pipe_context *ctx,
735 struct pipe_resource *texture,
736 const struct pipe_sampler_view *state,
737 unsigned width_first_level, unsigned height_first_level);
738 void r600_init_state_functions(struct r600_context *rctx);
739 void r600_init_atom_start_cs(struct r600_context *rctx);
740 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
741 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
742 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
743 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
744 void *r600_create_db_flush_dsa(struct r600_context *rctx);
745 void *r600_create_resolve_blend(struct r600_context *rctx);
746 void *r700_create_resolve_blend(struct r600_context *rctx);
747 void *r600_create_decompress_blend(struct r600_context *rctx);
748 bool r600_adjust_gprs(struct r600_context *rctx);
749 boolean r600_is_format_supported(struct pipe_screen *screen,
750 enum pipe_format format,
751 enum pipe_texture_target target,
752 unsigned sample_count,
753 unsigned usage);
754 void r600_update_db_shader_control(struct r600_context * rctx);
755
756 /* r600_hw_context.c */
757 void r600_context_gfx_flush(void *context, unsigned flags,
758 struct pipe_fence_handle **fence);
759 void r600_begin_new_cs(struct r600_context *ctx);
760 void r600_flush_emit(struct r600_context *ctx);
761 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
762 void r600_emit_pfp_sync_me(struct r600_context *rctx);
763 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
764 struct pipe_resource *dst, uint64_t dst_offset,
765 struct pipe_resource *src, uint64_t src_offset,
766 unsigned size);
767 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
768 struct pipe_resource *dst, uint64_t offset,
769 unsigned size, uint32_t clear_value,
770 enum r600_coherency coher);
771 void r600_dma_copy_buffer(struct r600_context *rctx,
772 struct pipe_resource *dst,
773 struct pipe_resource *src,
774 uint64_t dst_offset,
775 uint64_t src_offset,
776 uint64_t size);
777
778 /*
779 * evergreen_hw_context.c
780 */
781 void evergreen_dma_copy_buffer(struct r600_context *rctx,
782 struct pipe_resource *dst,
783 struct pipe_resource *src,
784 uint64_t dst_offset,
785 uint64_t src_offset,
786 uint64_t size);
787 void evergreen_setup_tess_constants(struct r600_context *rctx,
788 const struct pipe_draw_info *info,
789 unsigned *num_patches);
790 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
791 const struct pipe_draw_info *info,
792 unsigned num_patches);
793 void evergreen_set_ls_hs_config(struct r600_context *rctx,
794 struct radeon_winsys_cs *cs,
795 uint32_t ls_hs_config);
796 void evergreen_set_lds_alloc(struct r600_context *rctx,
797 struct radeon_winsys_cs *cs,
798 uint32_t lds_alloc);
799
800 /* r600_state_common.c */
801 void r600_init_common_state_functions(struct r600_context *rctx);
802 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
803 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
804 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
805 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
806 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
807 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
808 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
809 void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
810 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
811 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
812 unsigned num_dw);
813 void r600_vertex_buffers_dirty(struct r600_context *rctx);
814 void r600_sampler_views_dirty(struct r600_context *rctx,
815 struct r600_samplerview_state *state);
816 void r600_sampler_states_dirty(struct r600_context *rctx,
817 struct r600_sampler_states *state);
818 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
819 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
820 uint32_t r600_translate_stencil_op(int s_op);
821 uint32_t r600_translate_fill(uint32_t func);
822 unsigned r600_tex_wrap(unsigned wrap);
823 unsigned r600_tex_mipfilter(unsigned filter);
824 unsigned r600_tex_compare(unsigned compare);
825 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
826 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
827 const unsigned char *swizzle_view,
828 boolean vtx);
829 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
830 const unsigned char *swizzle_view,
831 uint32_t *word4_p, uint32_t *yuv_format_p,
832 bool do_endian_swap);
833 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format,
834 bool do_endian_swap);
835 uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap);
836
837 /* r600_uvd.c */
838 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
839 const struct pipe_video_codec *decoder);
840
841 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
842 const struct pipe_video_buffer *tmpl);
843
844 /*
845 * Helpers for building command buffers
846 */
847
848 #define PKT3_SET_CONFIG_REG 0x68
849 #define PKT3_SET_CONTEXT_REG 0x69
850 #define PKT3_SET_CTL_CONST 0x6F
851 #define PKT3_SET_LOOP_CONST 0x6C
852
853 #define R600_CONFIG_REG_OFFSET 0x08000
854 #define R600_CONTEXT_REG_OFFSET 0x28000
855 #define R600_CTL_CONST_OFFSET 0x3CFF0
856 #define R600_LOOP_CONST_OFFSET 0X0003E200
857 #define EG_LOOP_CONST_OFFSET 0x0003A200
858
859 #define PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30)
860 #define PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16)
861 #define PKT3_IT_OPCODE_S(x) (((unsigned)(x) & 0xFF) << 8)
862 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
863 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
864
865 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
866
867 /*Evergreen Compute packet3*/
868 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
869
870 static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value)
871 {
872 cb->buf[cb->num_dw++] = value;
873 }
874
875 static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
876 {
877 assert(cb->num_dw+num <= cb->max_num_dw);
878 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
879 cb->num_dw += num;
880 }
881
882 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
883 {
884 assert(reg < R600_CONTEXT_REG_OFFSET);
885 assert(cb->num_dw+2+num <= cb->max_num_dw);
886 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
887 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
888 }
889
890 /**
891 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
892 * shaders.
893 */
894 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
895 {
896 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
897 assert(cb->num_dw+2+num <= cb->max_num_dw);
898 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
899 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
900 }
901
902 /**
903 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
904 * shaders.
905 */
906 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
907 {
908 assert(reg >= R600_CTL_CONST_OFFSET);
909 assert(cb->num_dw+2+num <= cb->max_num_dw);
910 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
911 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
912 }
913
914 static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
915 {
916 assert(reg >= R600_LOOP_CONST_OFFSET);
917 assert(cb->num_dw+2+num <= cb->max_num_dw);
918 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
919 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
920 }
921
922 /**
923 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
924 * shaders.
925 */
926 static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
927 {
928 assert(reg >= EG_LOOP_CONST_OFFSET);
929 assert(cb->num_dw+2+num <= cb->max_num_dw);
930 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
931 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
932 }
933
934 static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
935 {
936 r600_store_config_reg_seq(cb, reg, 1);
937 r600_store_value(cb, value);
938 }
939
940 static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
941 {
942 r600_store_context_reg_seq(cb, reg, 1);
943 r600_store_value(cb, value);
944 }
945
946 static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
947 {
948 r600_store_ctl_const_seq(cb, reg, 1);
949 r600_store_value(cb, value);
950 }
951
952 static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
953 {
954 r600_store_loop_const_seq(cb, reg, 1);
955 r600_store_value(cb, value);
956 }
957
958 static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
959 {
960 eg_store_loop_const_seq(cb, reg, 1);
961 r600_store_value(cb, value);
962 }
963
964 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
965 void r600_release_command_buffer(struct r600_command_buffer *cb);
966
967 static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
968 {
969 radeon_set_context_reg_seq(cs, reg, num);
970 /* Set the compute bit on the packet header */
971 cs->current.buf[cs->current.cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
972 }
973
974 static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
975 {
976 assert(reg >= R600_CTL_CONST_OFFSET);
977 assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
978 radeon_emit(cs, PKT3(PKT3_SET_CTL_CONST, num, 0));
979 radeon_emit(cs, (reg - R600_CTL_CONST_OFFSET) >> 2);
980 }
981
982 static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
983 {
984 radeon_compute_set_context_reg_seq(cs, reg, 1);
985 radeon_emit(cs, value);
986 }
987
988 static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
989 {
990 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
991 radeon_compute_set_context_reg(cs, reg, value);
992 } else {
993 radeon_set_context_reg(cs, reg, value);
994 }
995 }
996
997 static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
998 {
999 radeon_set_ctl_const_seq(cs, reg, 1);
1000 radeon_emit(cs, value);
1001 }
1002
1003 /*
1004 * common helpers
1005 */
1006
1007 /* 12.4 fixed-point */
1008 static inline unsigned r600_pack_float_12p4(float x)
1009 {
1010 return x <= 0 ? 0 :
1011 x >= 4096 ? 0xffff : x * 16;
1012 }
1013
1014 static inline unsigned r600_get_flush_flags(enum r600_coherency coher)
1015 {
1016 switch (coher) {
1017 default:
1018 case R600_COHERENCY_NONE:
1019 return 0;
1020 case R600_COHERENCY_SHADER:
1021 return R600_CONTEXT_INV_CONST_CACHE |
1022 R600_CONTEXT_INV_VERTEX_CACHE |
1023 R600_CONTEXT_INV_TEX_CACHE |
1024 R600_CONTEXT_STREAMOUT_FLUSH;
1025 case R600_COHERENCY_CB_META:
1026 return R600_CONTEXT_FLUSH_AND_INV_CB |
1027 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1028 }
1029 }
1030
1031 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
1032 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
1033 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
1034
1035 unsigned r600_conv_prim_to_gs_out(unsigned mode);
1036
1037 void eg_trace_emit(struct r600_context *rctx);
1038 void eg_dump_debug_state(struct pipe_context *ctx, FILE *f,
1039 unsigned flags);
1040
1041 struct r600_pipe_shader_selector *r600_create_shader_state_tokens(struct pipe_context *ctx,
1042 const struct tgsi_token *tokens,
1043 unsigned pipe_shader_type);
1044 int r600_shader_select(struct pipe_context *ctx,
1045 struct r600_pipe_shader_selector* sel,
1046 bool *dirty);
1047
1048 void r600_delete_shader_selector(struct pipe_context *ctx,
1049 struct r600_pipe_shader_selector *sel);
1050
1051 struct r600_shader_atomic;
1052 bool evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
1053 struct r600_pipe_shader *cs_shader,
1054 struct r600_shader_atomic *combined_atomics,
1055 uint8_t *atomic_used_mask_p);
1056 void evergreen_emit_atomic_buffer_save(struct r600_context *rctx,
1057 bool is_compute,
1058 struct r600_shader_atomic *combined_atomics,
1059 uint8_t *atomic_used_mask_p);
1060 void r600_update_compressed_resource_state(struct r600_context *rctx, bool compute_only);
1061
1062 void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type);
1063 void r600_update_driver_const_buffers(struct r600_context *rctx, bool compute_only);
1064 #endif