projects / mesa.git / blob
? search:


f31fa45acb01e9259e38b3e5e9a016fd3ecb1e2a
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "../radeon/r600_pipe_common.h"
30 #include "../radeon/r600_cs.h"
31
32 #include "r600_llvm.h"
33 #include "r600_public.h"
34
35 #include "util/u_blitter.h"
36 #include "util/u_suballoc.h"
37 #include "util/u_double_list.h"
38 #include "util/u_transfer.h"
39
40 #define R600_NUM_ATOMS 73
41
42 /* the number of CS dwords for flushing and drawing */
43 #define R600_MAX_FLUSH_CS_DWORDS 16
44 #define R600_MAX_DRAW_CS_DWORDS 34
45 #define R600_TRACE_CS_DWORDS 7
46
47 #define R600_MAX_USER_CONST_BUFFERS 13
48 #define R600_MAX_DRIVER_CONST_BUFFERS 4
49 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
50
51 /* start driver buffers after user buffers */
52 #define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
53 #define R600_TXQ_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
54 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
55 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 3)
56
57 #define R600_MAX_CONST_BUFFER_SIZE 4096
58
59 #ifdef PIPE_ARCH_BIG_ENDIAN
60 #define R600_BIG_ENDIAN 1
61 #else
62 #define R600_BIG_ENDIAN 0
63 #endif
64
65 struct r600_context;
66 struct r600_bytecode;
67 struct r600_shader_key;
68
69 /* This is an atom containing GPU commands that never change.
70 * This is supposed to be copied directly into the CS. */
71 struct r600_command_buffer {
72 uint32_t *buf;
73 unsigned num_dw;
74 unsigned max_num_dw;
75 unsigned pkt_flags;
76 };
77
78 struct r600_db_state {
79 struct r600_atom atom;
80 struct r600_surface *rsurf;
81 };
82
83 struct r600_db_misc_state {
84 struct r600_atom atom;
85 bool occlusion_query_enabled;
86 bool flush_depthstencil_through_cb;
87 bool flush_depthstencil_in_place;
88 bool copy_depth, copy_stencil;
89 unsigned copy_sample;
90 unsigned log_samples;
91 unsigned db_shader_control;
92 bool htile_clear;
93 };
94
95 struct r600_cb_misc_state {
96 struct r600_atom atom;
97 unsigned cb_color_control; /* this comes from blend state */
98 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
99 unsigned nr_cbufs;
100 unsigned nr_ps_color_outputs;
101 bool multiwrite;
102 bool dual_src_blend;
103 };
104
105 struct r600_clip_misc_state {
106 struct r600_atom atom;
107 unsigned pa_cl_clip_cntl; /* from rasterizer */
108 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
109 unsigned clip_plane_enable; /* from rasterizer */
110 unsigned clip_dist_write; /* from vertex shader */
111 };
112
113 struct r600_alphatest_state {
114 struct r600_atom atom;
115 unsigned sx_alpha_test_control; /* this comes from dsa state */
116 unsigned sx_alpha_ref; /* this comes from dsa state */
117 bool bypass;
118 bool cb0_export_16bpc; /* from set_framebuffer_state */
119 };
120
121 struct r600_vgt_state {
122 struct r600_atom atom;
123 uint32_t vgt_multi_prim_ib_reset_en;
124 uint32_t vgt_multi_prim_ib_reset_indx;
125 uint32_t vgt_indx_offset;
126 };
127
128 struct r600_blend_color {
129 struct r600_atom atom;
130 struct pipe_blend_color state;
131 };
132
133 struct r600_clip_state {
134 struct r600_atom atom;
135 struct pipe_clip_state state;
136 };
137
138 struct r600_cs_shader_state {
139 struct r600_atom atom;
140 unsigned kernel_index;
141 struct r600_pipe_compute *shader;
142 };
143
144 struct r600_framebuffer {
145 struct r600_atom atom;
146 struct pipe_framebuffer_state state;
147 unsigned compressed_cb_mask;
148 unsigned nr_samples;
149 bool export_16bpc;
150 bool cb0_is_integer;
151 bool is_msaa_resolve;
152 };
153
154 struct r600_sample_mask {
155 struct r600_atom atom;
156 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
157 };
158
159 struct r600_config_state {
160 struct r600_atom atom;
161 unsigned sq_gpr_resource_mgmt_1;
162 unsigned sq_gpr_resource_mgmt_2;
163 };
164
165 struct r600_stencil_ref
166 {
167 ubyte ref_value[2];
168 ubyte valuemask[2];
169 ubyte writemask[2];
170 };
171
172 struct r600_stencil_ref_state {
173 struct r600_atom atom;
174 struct r600_stencil_ref state;
175 struct pipe_stencil_ref pipe_state;
176 };
177
178 struct r600_viewport_state {
179 struct r600_atom atom;
180 struct pipe_viewport_state state;
181 int idx;
182 };
183
184 struct r600_shader_stages_state {
185 struct r600_atom atom;
186 unsigned geom_enable;
187 };
188
189 struct r600_gs_rings_state {
190 struct r600_atom atom;
191 unsigned enable;
192 struct pipe_constant_buffer esgs_ring;
193 struct pipe_constant_buffer gsvs_ring;
194 };
195
196 /* This must start from 16. */
197 /* features */
198 #define DBG_LLVM (1 << 17)
199 #define DBG_NO_CP_DMA (1 << 18)
200 /* shader backend */
201 #define DBG_NO_SB (1 << 21)
202 #define DBG_SB_CS (1 << 22)
203 #define DBG_SB_DRY_RUN (1 << 23)
204 #define DBG_SB_STAT (1 << 24)
205 #define DBG_SB_DUMP (1 << 25)
206 #define DBG_SB_NO_FALLBACK (1 << 26)
207 #define DBG_SB_DISASM (1 << 27)
208 #define DBG_SB_SAFEMATH (1 << 28)
209
210 struct r600_screen {
211 struct r600_common_screen b;
212 bool has_msaa;
213 bool has_compressed_msaa_texturing;
214
215 /*for compute global memory binding, we allocate stuff here, instead of
216 * buffers.
217 * XXX: Not sure if this is the best place for global_pool. Also,
218 * it's not thread safe, so it won't work with multiple contexts. */
219 struct compute_memory_pool *global_pool;
220 };
221
222 struct r600_pipe_sampler_view {
223 struct pipe_sampler_view base;
224 struct r600_resource *tex_resource;
225 uint32_t tex_resource_words[8];
226 bool skip_mip_address_reloc;
227 };
228
229 struct r600_rasterizer_state {
230 struct r600_command_buffer buffer;
231 boolean flatshade;
232 boolean two_side;
233 unsigned sprite_coord_enable;
234 unsigned clip_plane_enable;
235 unsigned pa_sc_line_stipple;
236 unsigned pa_cl_clip_cntl;
237 float offset_units;
238 float offset_scale;
239 bool offset_enable;
240 bool scissor_enable;
241 bool multisample_enable;
242 };
243
244 struct r600_poly_offset_state {
245 struct r600_atom atom;
246 enum pipe_format zs_format;
247 float offset_units;
248 float offset_scale;
249 };
250
251 struct r600_blend_state {
252 struct r600_command_buffer buffer;
253 struct r600_command_buffer buffer_no_blend;
254 unsigned cb_target_mask;
255 unsigned cb_color_control;
256 unsigned cb_color_control_no_blend;
257 bool dual_src_blend;
258 bool alpha_to_one;
259 };
260
261 struct r600_dsa_state {
262 struct r600_command_buffer buffer;
263 unsigned alpha_ref;
264 ubyte valuemask[2];
265 ubyte writemask[2];
266 unsigned zwritemask;
267 unsigned sx_alpha_test_control;
268 };
269
270 struct r600_pipe_shader;
271
272 struct r600_pipe_shader_selector {
273 struct r600_pipe_shader *current;
274
275 struct tgsi_token *tokens;
276 struct pipe_stream_output_info so;
277
278 unsigned num_shaders;
279
280 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
281 unsigned type;
282
283 unsigned nr_ps_max_color_exports;
284 };
285
286 struct r600_pipe_sampler_state {
287 uint32_t tex_sampler_words[3];
288 union pipe_color_union border_color;
289 bool border_color_use;
290 bool seamless_cube_map;
291 };
292
293 /* needed for blitter save */
294 #define NUM_TEX_UNITS 16
295
296 struct r600_seamless_cube_map {
297 struct r600_atom atom;
298 bool enabled;
299 };
300
301 struct r600_samplerview_state {
302 struct r600_atom atom;
303 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
304 uint32_t enabled_mask;
305 uint32_t dirty_mask;
306 uint32_t compressed_depthtex_mask; /* which textures are depth */
307 uint32_t compressed_colortex_mask;
308 boolean dirty_txq_constants;
309 boolean dirty_buffer_constants;
310 };
311
312 struct r600_sampler_states {
313 struct r600_atom atom;
314 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
315 uint32_t enabled_mask;
316 uint32_t dirty_mask;
317 uint32_t has_bordercolor_mask; /* which states contain the border color */
318 };
319
320 struct r600_textures_info {
321 struct r600_samplerview_state views;
322 struct r600_sampler_states states;
323 bool is_array_sampler[NUM_TEX_UNITS];
324
325 /* cube array txq workaround */
326 uint32_t *txq_constants;
327 /* buffer related workarounds */
328 uint32_t *buffer_constants;
329 };
330
331 struct r600_constbuf_state
332 {
333 struct r600_atom atom;
334 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
335 uint32_t enabled_mask;
336 uint32_t dirty_mask;
337 };
338
339 struct r600_vertexbuf_state
340 {
341 struct r600_atom atom;
342 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
343 uint32_t enabled_mask; /* non-NULL buffers */
344 uint32_t dirty_mask;
345 };
346
347 /* CSO (constant state object, in other words, immutable state). */
348 struct r600_cso_state
349 {
350 struct r600_atom atom;
351 void *cso; /* e.g. r600_blend_state */
352 struct r600_command_buffer *cb;
353 };
354
355 struct r600_scissor_state
356 {
357 struct r600_atom atom;
358 struct pipe_scissor_state scissor;
359 bool enable; /* r6xx only */
360 int idx;
361 };
362
363 struct r600_fetch_shader {
364 struct r600_resource *buffer;
365 unsigned offset;
366 };
367
368 struct r600_shader_state {
369 struct r600_atom atom;
370 struct r600_pipe_shader *shader;
371 };
372
373 struct r600_context {
374 struct r600_common_context b;
375 struct r600_screen *screen;
376 struct blitter_context *blitter;
377 struct u_suballocator *allocator_fetch_shader;
378
379 /* Hardware info. */
380 boolean has_vertex_cache;
381 boolean keep_tiling_flags;
382 unsigned default_ps_gprs, default_vs_gprs;
383 unsigned r6xx_num_clause_temp_gprs;
384
385 /* Miscellaneous state objects. */
386 void *custom_dsa_flush;
387 void *custom_blend_resolve;
388 void *custom_blend_decompress;
389 void *custom_blend_fastclear;
390 /* With rasterizer discard, there doesn't have to be a pixel shader.
391 * In that case, we bind this one: */
392 void *dummy_pixel_shader;
393 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
394 * bug where valid CMASK and FMASK are required to be present to avoid
395 * a hardlock in certain operations but aren't actually used
396 * for anything useful. */
397 struct r600_resource *dummy_fmask;
398 struct r600_resource *dummy_cmask;
399
400 /* State binding slots are here. */
401 struct r600_atom *atoms[R600_NUM_ATOMS];
402 /* States for CS initialization. */
403 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
404 /** Compute specific registers initializations. The start_cs_cmd atom
405 * must be emitted before start_compute_cs_cmd. */
406 struct r600_command_buffer start_compute_cs_cmd;
407 /* Register states. */
408 struct r600_alphatest_state alphatest_state;
409 struct r600_cso_state blend_state;
410 struct r600_blend_color blend_color;
411 struct r600_cb_misc_state cb_misc_state;
412 struct r600_clip_misc_state clip_misc_state;
413 struct r600_clip_state clip_state;
414 struct r600_db_misc_state db_misc_state;
415 struct r600_db_state db_state;
416 struct r600_cso_state dsa_state;
417 struct r600_framebuffer framebuffer;
418 struct r600_poly_offset_state poly_offset_state;
419 struct r600_cso_state rasterizer_state;
420 struct r600_sample_mask sample_mask;
421 struct r600_scissor_state scissor[16];
422 struct r600_seamless_cube_map seamless_cube_map;
423 struct r600_config_state config_state;
424 struct r600_stencil_ref_state stencil_ref;
425 struct r600_vgt_state vgt_state;
426 struct r600_viewport_state viewport[16];
427 /* Shaders and shader resources. */
428 struct r600_cso_state vertex_fetch_shader;
429 struct r600_shader_state vertex_shader;
430 struct r600_shader_state pixel_shader;
431 struct r600_shader_state geometry_shader;
432 struct r600_shader_state export_shader;
433 struct r600_cs_shader_state cs_shader_state;
434 struct r600_shader_stages_state shader_stages;
435 struct r600_gs_rings_state gs_rings;
436 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
437 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
438 /** Vertex buffers for fetch shaders */
439 struct r600_vertexbuf_state vertex_buffer_state;
440 /** Vertex buffers for compute shaders */
441 struct r600_vertexbuf_state cs_vertex_buffer_state;
442
443 /* Additional context states. */
444 unsigned compute_cb_target_mask;
445 struct r600_pipe_shader_selector *ps_shader;
446 struct r600_pipe_shader_selector *vs_shader;
447 struct r600_pipe_shader_selector *gs_shader;
448 struct r600_rasterizer_state *rasterizer;
449 bool alpha_to_one;
450 bool force_blend_disable;
451 boolean dual_src_blend;
452 unsigned zwritemask;
453
454 /* Index buffer. */
455 struct pipe_index_buffer index_buffer;
456
457 /* Last draw state (-1 = unset). */
458 int last_primitive_type; /* Last primitive type used in draw_vbo. */
459 int last_start_instance;
460
461 void *sb_context;
462 struct r600_isa *isa;
463 };
464
465 static INLINE void r600_emit_command_buffer(struct radeon_winsys_cs *cs,
466 struct r600_command_buffer *cb)
467 {
468 assert(cs->cdw + cb->num_dw <= RADEON_MAX_CMDBUF_DWORDS);
469 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->num_dw);
470 cs->cdw += cb->num_dw;
471 }
472
473 void r600_trace_emit(struct r600_context *rctx);
474
475 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
476 {
477 atom->emit(&rctx->b, atom);
478 atom->dirty = false;
479 if (rctx->screen->b.trace_bo) {
480 r600_trace_emit(rctx);
481 }
482 }
483
484 static INLINE void r600_set_cso_state(struct r600_cso_state *state, void *cso)
485 {
486 state->cso = cso;
487 state->atom.dirty = cso != NULL;
488 }
489
490 static INLINE void r600_set_cso_state_with_cb(struct r600_cso_state *state, void *cso,
491 struct r600_command_buffer *cb)
492 {
493 state->cb = cb;
494 state->atom.num_dw = cb ? cb->num_dw : 0;
495 r600_set_cso_state(state, cso);
496 }
497
498 /* compute_memory_pool.c */
499 struct compute_memory_pool;
500 void compute_memory_pool_delete(struct compute_memory_pool* pool);
501 struct compute_memory_pool* compute_memory_pool_new(
502 struct r600_screen *rscreen);
503
504 /* evergreen_compute.c */
505 void evergreen_set_cs_sampler_view(struct pipe_context *ctx_,
506 unsigned start_slot, unsigned count,
507 struct pipe_sampler_view **views);
508
509 /* evergreen_state.c */
510 struct pipe_sampler_view *
511 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
512 struct pipe_resource *texture,
513 const struct pipe_sampler_view *state,
514 unsigned width0, unsigned height0,
515 unsigned force_level);
516 void evergreen_init_common_regs(struct r600_command_buffer *cb,
517 enum chip_class ctx_chip_class,
518 enum radeon_family ctx_family,
519 int ctx_drm_minor);
520 void cayman_init_common_regs(struct r600_command_buffer *cb,
521 enum chip_class ctx_chip_class,
522 enum radeon_family ctx_family,
523 int ctx_drm_minor);
524
525 void evergreen_init_state_functions(struct r600_context *rctx);
526 void evergreen_init_atom_start_cs(struct r600_context *rctx);
527 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
528 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
529 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
530 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
531 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
532 void *evergreen_create_resolve_blend(struct r600_context *rctx);
533 void *evergreen_create_decompress_blend(struct r600_context *rctx);
534 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
535 boolean evergreen_is_format_supported(struct pipe_screen *screen,
536 enum pipe_format format,
537 enum pipe_texture_target target,
538 unsigned sample_count,
539 unsigned usage);
540 void evergreen_init_color_surface(struct r600_context *rctx,
541 struct r600_surface *surf);
542 void evergreen_init_color_surface_rat(struct r600_context *rctx,
543 struct r600_surface *surf);
544 void evergreen_update_db_shader_control(struct r600_context * rctx);
545
546 /* r600_blit.c */
547 void r600_init_blit_functions(struct r600_context *rctx);
548 void r600_decompress_depth_textures(struct r600_context *rctx,
549 struct r600_samplerview_state *textures);
550 void r600_decompress_color_textures(struct r600_context *rctx,
551 struct r600_samplerview_state *textures);
552
553 /* r600_shader.c */
554 int r600_pipe_shader_create(struct pipe_context *ctx,
555 struct r600_pipe_shader *shader,
556 struct r600_shader_key key);
557
558 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
559
560 /* r600_state.c */
561 struct pipe_sampler_view *
562 r600_create_sampler_view_custom(struct pipe_context *ctx,
563 struct pipe_resource *texture,
564 const struct pipe_sampler_view *state,
565 unsigned width_first_level, unsigned height_first_level);
566 void r600_init_state_functions(struct r600_context *rctx);
567 void r600_init_atom_start_cs(struct r600_context *rctx);
568 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
569 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
570 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
571 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
572 void *r600_create_db_flush_dsa(struct r600_context *rctx);
573 void *r600_create_resolve_blend(struct r600_context *rctx);
574 void *r700_create_resolve_blend(struct r600_context *rctx);
575 void *r600_create_decompress_blend(struct r600_context *rctx);
576 bool r600_adjust_gprs(struct r600_context *rctx);
577 boolean r600_is_format_supported(struct pipe_screen *screen,
578 enum pipe_format format,
579 enum pipe_texture_target target,
580 unsigned sample_count,
581 unsigned usage);
582 void r600_update_db_shader_control(struct r600_context * rctx);
583
584 /* r600_hw_context.c */
585 void r600_context_gfx_flush(void *context, unsigned flags,
586 struct pipe_fence_handle **fence);
587 void r600_begin_new_cs(struct r600_context *ctx);
588 void r600_flush_emit(struct r600_context *ctx);
589 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
590 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
591 struct pipe_resource *dst, uint64_t dst_offset,
592 struct pipe_resource *src, uint64_t src_offset,
593 unsigned size);
594 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
595 struct pipe_resource *dst, uint64_t offset,
596 unsigned size, uint32_t clear_value);
597 void r600_dma_copy_buffer(struct r600_context *rctx,
598 struct pipe_resource *dst,
599 struct pipe_resource *src,
600 uint64_t dst_offset,
601 uint64_t src_offset,
602 uint64_t size);
603
604 /*
605 * evergreen_hw_context.c
606 */
607 void evergreen_dma_copy_buffer(struct r600_context *rctx,
608 struct pipe_resource *dst,
609 struct pipe_resource *src,
610 uint64_t dst_offset,
611 uint64_t src_offset,
612 uint64_t size);
613
614 /* r600_state_common.c */
615 void r600_init_common_state_functions(struct r600_context *rctx);
616 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
617 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
618 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
619 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
620 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
621 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
622 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom);
623 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
624 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
625 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
626 unsigned num_dw);
627 void r600_vertex_buffers_dirty(struct r600_context *rctx);
628 void r600_sampler_views_dirty(struct r600_context *rctx,
629 struct r600_samplerview_state *state);
630 void r600_sampler_states_dirty(struct r600_context *rctx,
631 struct r600_sampler_states *state);
632 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
633 void r600_draw_rectangle(struct blitter_context *blitter,
634 int x1, int y1, int x2, int y2, float depth,
635 enum blitter_attrib_type type, const union pipe_color_union *attrib);
636 uint32_t r600_translate_stencil_op(int s_op);
637 uint32_t r600_translate_fill(uint32_t func);
638 unsigned r600_tex_wrap(unsigned wrap);
639 unsigned r600_tex_filter(unsigned filter);
640 unsigned r600_tex_mipfilter(unsigned filter);
641 unsigned r600_tex_compare(unsigned compare);
642 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
643 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
644 struct pipe_resource *texture,
645 const struct pipe_surface *templ,
646 unsigned width, unsigned height);
647 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
648 const unsigned char *swizzle_view,
649 boolean vtx);
650 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
651 const unsigned char *swizzle_view,
652 uint32_t *word4_p, uint32_t *yuv_format_p);
653 uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format);
654 uint32_t r600_colorformat_endian_swap(uint32_t colorformat);
655
656 /* r600_uvd.c */
657 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
658 const struct pipe_video_codec *decoder);
659
660 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
661 const struct pipe_video_buffer *tmpl);
662
663 /*
664 * Helpers for building command buffers
665 */
666
667 #define PKT3_SET_CONFIG_REG 0x68
668 #define PKT3_SET_CONTEXT_REG 0x69
669 #define PKT3_SET_CTL_CONST 0x6F
670 #define PKT3_SET_LOOP_CONST 0x6C
671
672 #define R600_CONFIG_REG_OFFSET 0x08000
673 #define R600_CONTEXT_REG_OFFSET 0x28000
674 #define R600_CTL_CONST_OFFSET 0x3CFF0
675 #define R600_LOOP_CONST_OFFSET 0X0003E200
676 #define EG_LOOP_CONST_OFFSET 0x0003A200
677
678 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
679 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
680 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
681 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
682 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
683
684 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
685
686 /*Evergreen Compute packet3*/
687 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
688
689 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
690 {
691 cb->buf[cb->num_dw++] = value;
692 }
693
694 static INLINE void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
695 {
696 assert(cb->num_dw+num <= cb->max_num_dw);
697 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
698 cb->num_dw += num;
699 }
700
701 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
702 {
703 assert(reg < R600_CONTEXT_REG_OFFSET);
704 assert(cb->num_dw+2+num <= cb->max_num_dw);
705 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
706 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
707 }
708
709 /**
710 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
711 * shaders.
712 */
713 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
714 {
715 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
716 assert(cb->num_dw+2+num <= cb->max_num_dw);
717 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
718 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
719 }
720
721 /**
722 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
723 * shaders.
724 */
725 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
726 {
727 assert(reg >= R600_CTL_CONST_OFFSET);
728 assert(cb->num_dw+2+num <= cb->max_num_dw);
729 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
730 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
731 }
732
733 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
734 {
735 assert(reg >= R600_LOOP_CONST_OFFSET);
736 assert(cb->num_dw+2+num <= cb->max_num_dw);
737 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
738 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
739 }
740
741 /**
742 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
743 * shaders.
744 */
745 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
746 {
747 assert(reg >= EG_LOOP_CONST_OFFSET);
748 assert(cb->num_dw+2+num <= cb->max_num_dw);
749 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
750 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
751 }
752
753 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
754 {
755 r600_store_config_reg_seq(cb, reg, 1);
756 r600_store_value(cb, value);
757 }
758
759 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
760 {
761 r600_store_context_reg_seq(cb, reg, 1);
762 r600_store_value(cb, value);
763 }
764
765 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
766 {
767 r600_store_ctl_const_seq(cb, reg, 1);
768 r600_store_value(cb, value);
769 }
770
771 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
772 {
773 r600_store_loop_const_seq(cb, reg, 1);
774 r600_store_value(cb, value);
775 }
776
777 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
778 {
779 eg_store_loop_const_seq(cb, reg, 1);
780 r600_store_value(cb, value);
781 }
782
783 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
784 void r600_release_command_buffer(struct r600_command_buffer *cb);
785
786 static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
787 {
788 r600_write_context_reg_seq(cs, reg, num);
789 /* Set the compute bit on the packet header */
790 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
791 }
792
793 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
794 {
795 assert(reg >= R600_CTL_CONST_OFFSET);
796 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
797 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
798 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
799 }
800
801 static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
802 {
803 r600_write_compute_context_reg_seq(cs, reg, 1);
804 radeon_emit(cs, value);
805 }
806
807 static INLINE void r600_write_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag)
808 {
809 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
810 r600_write_compute_context_reg(cs, reg, value);
811 } else {
812 r600_write_context_reg(cs, reg, value);
813 }
814 }
815
816 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
817 {
818 r600_write_ctl_const_seq(cs, reg, 1);
819 radeon_emit(cs, value);
820 }
821
822 /*
823 * common helpers
824 */
825 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
826 {
827 return value * (1 << frac_bits);
828 }
829 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
830
831 static inline unsigned r600_tex_aniso_filter(unsigned filter)
832 {
833 if (filter <= 1) return 0;
834 if (filter <= 2) return 1;
835 if (filter <= 4) return 2;
836 if (filter <= 8) return 3;
837 /* else */ return 4;
838 }
839
840 /* 12.4 fixed-point */
841 static INLINE unsigned r600_pack_float_12p4(float x)
842 {
843 return x <= 0 ? 0 :
844 x >= 4096 ? 0xffff : x * 16;
845 }
846
847 /* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */
848 static INLINE bool r600_can_read_depth(struct r600_texture *rtex)
849 {
850 return rtex->resource.b.b.nr_samples <= 1 &&
851 (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
852 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT);
853 }
854
855 #endif